End of Life. Last Available Purchase Date is 31-Dec-2014
Si9112
Vishay Siliconix
High-Voltage Switchmode Controller
FEATURES
9- to 80-V Input Range
Current-Mode Control
High-Speed, Source-Sink Output Drive
High Efficiency Operation (> 80%)
Internal Start-Up Circuit
Internal Oscillator (1 MHz)
SHUTDOWN and RESET
DESCRIPTION
The Si9112 is a BiC/DMOS integrated circuit designed for use
in high-efficiency switchmode power converters. A
high-voltage DMOS input allows this controller to work over a
wide range of input voltages (9- to 80-VDC). Current-mode
PWM control circuitry is implemented in CMOS to reduce
internal power consumption to less than 10 mW.
power. When combined with an output MOSFET and
transformer, the Si9112 can be used to implement
single-ended power converter topologies (i.e., flyback,
forward, and cuk).
The Si9112 is available in both standard and lead (Pb)-free
14-pin plastic DIP and SOIC packages which are specified to
operate over the industrial temperature range of −40 C to
85 C.
A CMOS output driver provides high-speed switching of
MOSPOWER devices large enough to supply 50 W of output
FUNCTIONAL BLOCK DIAGRAM
FB
COMP
14
DISCHARGE
13
9
OSC
IN
8
Error
Amplifier
VREF
OSC
OUT
7
OSC
To
VCC
−
10
Clock
+
(1/2 fOSC)
4 V (2%)
2V
Ref
Gen
−
Current-Mode
Comparator
4
R
+
Q
5
OUTPUT
−VIN
S
+
−
1
BIAS
VCC
+VIN
Current
Sources
6
To
Internal
Circuits
2
1.2 V
3
VCC
−
8.1 V
C/L
Comparator
+
Undervoltage Comparator
S
Q
R
11
12
SENSE
SHUTDOWN
RESET
−
+
8.7 V
Pre-Regulator/Start-Up
Applications information, see AN703.
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
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1
Si9112
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to −VIN (VCC < +VIN + 0.3 V)
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Power Dissipation (Package)a
14-Pin Plastic DIP (J Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW
14-Pin SOIC (Y Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
+VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 V
Logic Inputs
(RESET, SHUTDOWN, OSC IN) . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Linear Inputs (FEEDBACK, SENSE) . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . 25 mA
(Power Dissipation Limited)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150_C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 85_C
Thermal Impedance (JA)
14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167_C/W
14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 6 mW/_C above 25_C.
c. Derate 7.2 mW/_C above 25_C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltages Referenced to −VIN
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 13.5 V
ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 k to 1 M
+VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 80 V
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC − 3 V
fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Limits
D Suffix −40 to 85_C
DISCHARGE = −VIN = 0 V
VCC = 9 V, +VIN = 12 V
RBIAS = 270 k , ROSC = 330 k
Tempb
Mind
Typc
Maxe
Unit
OSC IN = − VIN (OSC Disabled)
RL = 10 M
Room
Fulle
3.88
3.82
4.0
4.12
4.14
V
Room
15
30
45
k
Room
70
100
130
A
0.5
1.0
mV/_C
Reference
Output Voltage
VR
Output Impedancee
ZOUT
Short Circuit Current
ISREF
Temperature
Stabilitye
VREF = −VIN
TREF
Full
Oscillator
Maximum Frequencye
Initial Accuracy
Voltage Stability
Temperature Coefficiente
fMAX
fOSC
f/f
ROSC = 0
Room
1
3
ROSC = 330 k, See Note f
Room
80
100
120
ROSC = 150 k, See Note f
Room
160
200
240
f/f = f(13.5 V) − f(9.5 V) / f(9.5 V)
Room
9
15
%
Full
200
500
ppm/_C
4.00
4.08
V
TOSC
MHz
kHz
Error Amplifier
Feedback Input Voltage
VFB
FB Tied to COMP
OSC IN = − VIN (OSC Disabled)
Room
Input Offset Voltage
VOS
OSC IN = − VIN (OSC Disabled)
Room
"15
"40
mV
Input BIAS Current
IFB
OSC IN = − VIN, VFB = 4 V
Room
25
500
nA
AVOL
OSC IN = − VIN
Room
60
BW
OSC IN = − VIN (OSC Disabled)
Room
1
ZOUT
Error Amp Configured for 60 dB gain
Room
1000
2000
Source VFB = 3.4 V
Room
−2.0
−1.4
Sink VFB = 4.5 V
Room
0.12
0.15
9 V v VCC v 13.5 V
Room
50
70
Open Loop Voltage Gaine
Unity Gain
Bandwidthe
Dynamic Output Impedancee
Output Current
Power Supply Rejectione
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2
IOUT
PSRR
3.92
80
dB
1.5
MHz
mA
dB
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
Si9112
Vishay Siliconix
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified
Parameter
Limits
D Suffix −40 to 85_C
DISCHARGE = −VIN = 0 V
VCC = 9 V, +VIN = 12 V
RBIAS = 270 k , ROSC = 330 k
Tempb
Mind
VSOURCE
VFB = 0 V
Room
1.1
td
VSENSE = 1.5 V, See Figure 1
Room
Symbol
Typc
Maxe
Unit
Current Limit
Threshold Voltage
Delay to Outpute
1.3
1.5
V
100
150
ns
10
A
Pre-Regulator/Start-Up
Input Voltage
+VIN
IIN = 10 A
Room
Input Leakage Current
+IIN
VCC w 9.4 V
Room
ISTART
+VIN = 48 V
Room
12
Pre-Regulator Start-Up Current
80
V
20
mA
VCC
+VIN = 10 V, RLOAD = 4 k at Pin 6
Room
VUVLO
+0.1
VCC Pre-Regulator Turn-Off
Threshold Voltage
VREG
IPRE-REGULATOR = 10 A
Room
8.0
8.7
9.4
Undervoltage Lockout
VUVLO
See Detailed Description
Room
7.2
8.1
8.9
VREG −VUVLO
VDELTA
Room
0.3
0.6
Pre-Regulator Dropout Voltage
V
Supply
Supply Current
ICC
Bias Current
CL v 75 pF (Pin 4)
IBIAS
Room
0.6
Room
15
Room
50
1.0
mA
A
Logic
SHUTDOWN Delaye
SHUTDOWN Pulse
Widthe
tSD
CL = 500 pF
VSENSE = −VIN, See Figure 2
100
tSW
Room
50
RESET Pulse Widthe
tRW
Room
50
Latching Pulse Width
SHUTDOWN and RESET Lowe
tLW
Room
25
Input Low Voltage
VIL
Room
Input High Voltage
VIH
Room
Input Current Input Voltage High
IIH
VLOGIC = VCC
Room
Input Current Input Voltage Low
IIL
VIN = 0 V
Room
−35
Output High Voltage
VOH
IOUT = −10 mA
Room
Full
8.7
8.5
Output Low Voltage
VOL
IOUT = 10 mA
Room
Full
Output Resistancee
ROUT
IOUT = 10 mA, Source or Sink
Room
Full
20
25
30
50
Room
40
75
Room
40
75
See Figure 3
ns
2.0
V
5
A
7.0
1
25
Output
Rise Timee
Fall
Timee
tr
tf
CL = 500 pF
0.3
0.5
V
ns
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f.
CSTRAY Pin 8 = v 5 pF.
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
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3
Si9112
Vishay Siliconix
TIMING WAVEFORMS
SENSE
1.5 V −
50%
0
VCC
SHUTDOWN
0
tr v 10 ns
50%
tf v 10 ns
−
tSD
td
VCC
VCC
90%
OUTPUT
0 −
90%
OUTPUT
0
−
FIGURE 1.
FIGURE 2.
tSW
VCC
SHUTDOWN
0
50%
50%
−
tf, tf v 10 ns
tLW
VCC
RESET
0
50%
50%
50%
−
tRW
FIGURE 3.
TYPICAL CHARACTERISTICS
Output Switching Frequency
vs. Oscillator Resistance
+VIN vs. +IIN at Start-Up
140
1M
VCC = −VIN
120
f OUT (Hz)
+V IN (V)
100
80
60
100 k
40
20
0
10 k
10
15
+IIN (mA)
FIGURE 4.
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4
20
10 k
100 k
1M
rOSC − Oscillator Resistance ()
FIGURE 5.
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
Si9112
Vishay Siliconix
PIN CONFIGURATIONS AND ORDERING INFORMATION
Dual-In-Line and SOIC
BIAS
1
14 FB
+VIN
2
13 COMP
SENSE
3
12 RESET
OUTPUT
4
11 SHUTDOWN
−VIN
5
10 VREF
VCC
6
9
DISCHARGE
OSC OUT
7
8
OSC IN
ORDERING INFORMATION
Part Number
Temperature Range
Package
Si9112DY
Si9112DY-T1
Si9112DY-T1—E3
Si9112DJ
Si9112DJ—E3
SOIC-14
−40 to 85_C
PDIP-14
Top View
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section
Due to the low quiescent current requirement of the Si9112
control circuitry, bias power can be supplied from the
unregulated input power source, from an external regulated
low-voltage supply, or from an auxiliary “bootstrap” winding on
the output inductor or transformer.
When power is first applied during start-up, +VIN (pin 2) will
draw a constant current. The magnitude of this current is
determined by a high-voltage depletion MOSFET device
which is connected between +VIN and VCC (pin 6). This
start-up circuitry provides initial power to the IC by charging an
external bypass capacitance connected to the VCC pin. The
charging current is disabled when VCC exceeds 8.7 V. If VCC is
not forced to exceed the 8.7-V threshold, then VCC will be
regulated to a nominal value of 8.7 V by the pre-regulator
circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (UV) lockout circuit keeps
the output driver disabled until VCC exceeds the UV lockout
threshold (typically 8.1 V). This guarantees that the control
logic will be functioning properly and that sufficient gate drive
voltage is available before the MOSFET turns on. The design
of the IC is such that the undervoltage lockout threshold will be
at least 300 mV less than the pre-regulator turn-off voltage.
Power dissipation can be minimized by providing an external
power source to VCC such that the pre-regulator circuit is
disabled.
BIAS
To properly set the bias for the Si9112, a 270-k resistor
should be tied from BIAS (pin 1) to −VIN (pin 5). This
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
determines the magnitude of bias current in all of the analog
sections and the pull-up current for the SHUTDOWN and
RESET pins. The current flowing in the bias resistor is
nominally 15 A.
Reference Section
The reference section of the Si9112 consists of a temperature
compensated buried zener and trimmable divider network.
The output of the reference section is connected internally to
the non-inverting input of the error amplifier. Nominal reference
output voltage is 4 V. The trimming procedure that is used on
the Si9112 brings the output of the error amplifier (which is
configured for unity gain during trimming) to within "2% of 4 V.
This automatically compensates for input offset voltage in the
error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external voltage
source can be used to override the internal voltage source, if
desired, without otherwise altering the performance of the
device.
Error Amplifier
Closed-loop regulation is provided by the error amplifier. The
emitter follower output has a typical dynamic output
impedance of 1000 , and is intended for use with
“around-the-amplifier” compensation. A MOS differential input
stage provides low input leakage current. The noninverting
input to the error amplifier (VREF) is internally connected to the
output of the reference supply and should be bypassed with a
small capacitor to ground.
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Si9112
Vishay Siliconix
DETAILED DESCRIPTION (CONT’D)
Oscillator Section
The oscillator consists of a ring of CMOS inverters, capacitors,
and a capacitor discharge switch. Frequency is set by an
external resistor between the OSC IN and OSC OUT pins.
(See Typical Characteristics for details of resistor value vs.
frequency.) The DISCHARGE pin should be tied to −VIN for
normal internal oscillator operation. A frequency divider in the
logic section limits switch duty cycle to v50% by locking the
switching frequency to one half of the oscillator frequency.
Remote synchronization can be accomplished by capacitive
coupling of a SYNC pulse into the OSC IN (pin 8) terminal. For
a 5-V pulse amplitude and 0.5-s pulse width, typical values
would be 100 pF in series with 3 k to pin 8.
SHUTDOWN and RESET
SHUTDOWN (pin 11) and RESET (pin 12) are intended for
overriding the output MOSFET switch via external control
logic. The two inputs are fed through a latch preceding the
output switch. Depending on the logic state of RESET,
SHUTDOWN can be either a latched or unlatched input. The
output is off whenever SHUTDOWN is low. By simultaneously
having SHUTDOWN and RESET low, the latch is set and
SHUTDOWN has no effect until RESET goes high. The truth
table for these inputs is given in Table 1.
Table 1: Truth Table for the SHUTDOWN and RESET Pins
SHUTDOWN
RESET
H
H
H
Output
Normal Operation
Normal Operation (No Change)
L
H
L
L
Off (Not Latched)
Off (Latched)
L
Off (Latched, No Change)
Both pins have internal current source pull-ups and should be
left disconnected when not in use. An added feature of the
current sources is the ability to connect a capacitor and an
open-collector driver to the SHUTDOWN or RESET pins to
provide variable shutdown time.
Output Driver
The push-pull driver output has a typical on-resistance of 20 .
Maximum switching times are specified at 75 ns for a 500 pF
load. This is sufficient to directly drive 60-V, 25-A MOSFETs.
Larger devices can be driven, but switching times will be
longer, resulting in higher switching losses.
For applications information refer to AN703.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and
Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see
http://www.vishay.com/ppg?70005.
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6
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
Package Information
Vishay Siliconix
SOIC (NARROW): 14-LEAD (POWER IC ONLY)
MILLIMETERS
14
13
12
11
10
9
Dim
A
A1
B
C
D
E
e
H
L
Ø
8
E
2
3
4
5
6
7
D
A
e
B
Document Number: 72809
28-Jan-04
A1
0.25
(GAGE PLANE)
1
H
INCHES
Min
Max
Min
Max
1.35
1.75
0.053
0.069
0.10
0.20
0.004
0.008
0.38
0.51
0.015
0.020
0.18
0.23
0.007
0.009
8.55
8.75
0.336
0.344
3.8
4.00
0.149
0.157
1.27 BSC
0.050 BSC
5.80
6.20
0.228
0.244
0.50
0.93
0.020
0.037
0_
8_
0_
8_
ECN: S-40080—Rev. A, 02-Feb-04
DWG: 5914
C
ALL LEADS
L
Ø
0.101 mm
0.004″
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1
Package Information
Vishay Siliconix
PDIP: 14-LEAD (POWER IC ONLY)
14
13
12
11
10
9
8
E
E1
1
2
3
4
5
6
7
D
S
Q1
A
A1
B1
e1
L
B
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
Q1
S
15°
MAX
C
eA
MILLIMETERS
Min
Max
INCHES
Min
Max
3.81
5.08
0.150
0.200
0.38
1.27
0.015
0.050
0.38
0.51
0.015
0.020
0.89
1.65
0.035
0.065
0.20
0.30
0.008
0.012
17.27
19.30
0.680
0.760
7.62
8.26
0.300
0.325
5.59
7.11
0.220
0.280
2.29
2.79
0.090
0.110
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
1.27
2.03
0.050
0.080
1.02
2.03
0.040
0.080
ECN: S-40081—Rev. A, 02-Feb-04
DWG: 5919
Document Number: 72814
28-Jan-04
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1
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Revision: 01-Jan-2022
1
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