Product is End of Life 12/2014
Si9118, Si9119
Vishay Siliconix
Programmable Duty Cycle Controller
DESCRIPTION
FEATURES
The Si9118/Si9119 are a BiC/DMOS current-mode pulse
width modulation (PWM) controller ICs for high-frequency
dc/dc converters. Single-ended topologies (forward and
flyback) can be implemented at frequencies up to 1 MHz.
The controller operates in constant frequency mode during
the full load and automatically switches to pulse skipping
mode under light load to maintain high efficiency throughout
the full load range. The maximum duty cycle is easily
programmed with a resistor divider for optimum control.
The push-pull output driver provides high-speed switching to
external MOSPOWER devices large enough to supply 50 W
of output power. Shoot-through current for internal push-pull
stage is almost eliminated to minimize quiescent supply
current.
The push-pull output driver provides high-speed switching to
external MOSPOWER devices large enough to supply 50 W
of output power. Shoot-through current for internal push-pull
stage is almost eliminated to minimize quiescent supply
current.
The high-voltage DMOS transistor permits direct operation
from bus voltages of up to 200 V. Other features include a
1.5 % accurate voltage reference, 2.7 MHz bandwidth error
amplifier, standby mode, soft-start and undervoltage lockout
circuits.
The Si9118/Si9119 are available in both standard and lead
(Pb)-free packages.
• 10 to 200 V Input Range
• Current-Mode Control
• Internal Start-Up Circuit
• Buffer Slope Compensation Voltage
• Soft-Start
• 2.7 MHz Error Amp
• 500 mA Output Drive Current
• Light Load Frequency Fold-Back
• Low Quiescent Current
• Programmable Maximum Duty Cycle, with 80 % as
Default
FUNCTIONAL BLOCK DIAGRAM
LIMIT
5
6
Error
Amplifier
NI
4
3
VREF
10
2
11
PWM
OSC
8
ROSC
COSC
Ref
Gen
100 mV
Pulse Skip
+ EN
–
IMAX
7
600 mV
R
15
Q
DR
S
+
–
14
–VIN
+VIN
13
–
+
23µA
VCC
MAX
9
1.0 - 2.0 V
+ –
–
+
4.6 V
SS/EN
SYNC (Si9119)
12
CS
-V IN
Substrate
16
1
–
–
+
Document Number: 70815
S11-0975–Rev. E, 16-May-11
+
–
+
8.6 V
9.3 V (VREG)
Undervoltage
Lockout
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Voltage Reference VCC to VIN
18
+VIN ( Note: VCC < + VIN + 0.3 V)
200
Unit
Logic Input (SYNC)
- 0.3 to Vcc + 0.3
Linear Input (FB, ICS, ILIMIT, SS/EN)
- 0.3 to Vcc + 0.3
V
5
HV Pre-Regulator Input Current (continuous)
mA
Storage Temperature
- 65 to 150
Operating Temperature
- 40 to 85
°C
DMAX
3.2
V
Junction Temperature (TJ)
150
°C
Power Dissipation (Package)a
16-Pin SOIC (Y Suffix)b
900
mW
Thermal Impedance (θJA)
16-Pin SOIC
140
°C/W
Notes:
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/°C above 25 °C.
* Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating
may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one
Absolute Maximum rating should be applied at any one time.
RECOMMENDED OPERATING RANGE
Parameter
Limit
Unit
Voltage Reference Vcc to VIN
10 to 16.5
+VIN
10 to 200
fOSC
40 kHz to 1 MHz
ROSC
56 kΩ to 1 MΩ
COSC
47 to 200
pF
Linear Inputs
0 to Vcc - 4
V
Digital Inputs
0 to Vcc
V
V
SPECIFICATIONS
Parameter
Symbol
Limits
D Suffix - 40 to 85 °C
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Temp.a
Min.
Typ.b
Max.
OSC Disabled, TA = 25 °C
Room
3.94
4.0
4.06
Full
3.88
4.0
4.12
Unit
Reference
Output Voltage
VREF
OSC Disabled, Over Voltage and
Temperature Ranges
Short Circuit Current
Load Regulation
www.vishay.com
2
c
V
ISREF
VREF = -VIN
- 30
-5
mA
ΔVR/ΔIR
IREF = 0 to - 1mA
10
40
mV
Document Number: 70815
S11-0975–Rev. E, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
SPECIFICATIONS
Parameter
Symbol
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Limits
D Suffix - 40 to 85 °C
Temp.a
Min.
Typ.b
Max.
ROSC = 374 kΩ, COSC = 200 pF
90
100
110
ROSC = 70 kΩ, COSC = 200 pF
450
500
550
Unit
Oscillator
Initial Accuracyd
fOSC
fOSC
Voltage Stabilityc
Temperature Coefficientc
c
kHz
Δf/f
ROSC = 70 kΩ, COSC = 200 pF
Δf/f = [f(16.5 V) - f(9.5 V)] / f(9.5 V)
1
2
%
OSC TC
- 40 ≤ TA ≤ 85 °C, fOSC = 100 kHz
200
500
ppm/°C
Sync High Pulse Width (Si9119)
200
Sync Low Pulse Width (Si9119)
200
ns
Sync Rise/Fall Time (Si9119)
200
Sync Logic Low (Si9119)
VIL
Sync Logic High (Si9119)
VIH
4
Sync Rangec (Si9119)
fEXT
1.05 x fOSC
PWM/PSM Logic High
VIH
4
PWM/PSM Logic Low
VIL
0.8
V
kHz
PWM/PSM
V
0.8
DMAX
Accuracy
fOSC = 100 kHz with 1 % Resistor
± 10
VFB = 5 V, NI = VREF
< 1.0
± 200
nA
±5
± 25
mV
%
Error Amplifier (OSC Disabled)
Input BIAS Current
IFB
Input OFFSET Voltage
VOS2
Open Loop Voltage Gainc
AVOL
65
80
dB
Unity Gain Bandwidthc
BW
1.8
2.7
MHz
- 1.0
- 2.7
IOUT
Source (VFB = 3.5 V, NI = VREF)
Output Current
Sink (VFB = 4.5 V, NI = VREF)
1.0
2.4
10 V ≤ VCC ≤ 16.5 V
50
80
Power Supply Rejection
PSRR
mA
dB
Pre-Regulator/Start-up
Input Voltagec
+VIN
IIN = 10 µA
Room
Input Leakage Current
+IIN
VCC ≥ 10 V
Room
Pre-Regulator Start-Up Current
ISTART
Pulse Width ≤ 300 µs, VCC = VULVO
Room
8
15
VCC Pre-Regulator Turn-Off
Threshold Voltage
VREG
IPRE_REGULATOR = 15 µA
Room
8.7
9.3
9.8
Undervoltage Lockout
VUVLO
Room
8.0
8.6
9.3
V
VREG - VUVLO
VDELTA
Room
0.3
0.7
3.0
mA
200
V
10
µA
mA
Supply
Supply Current
Document Number: 70815
S11-0975–Rev. E, 16-May-11
ICC
CLOAD ≤ 50 pF, fOSC = 100 kHZ
1.9
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
SPECIFICATIONS
Parameter
Symbol
Test Conditions
Unless Otherwise Specified
- VIN = 0 V, VCC = 10 V
Limits
D Suffix - 40 to 85 °C
Temp.a
Min.
Typ.b
Max.
Unit
0.5
0.6
0.7
V
77
100
ns
- 12
- 23
- 30
µA
0.5
1.26
80
100
120
Room
Full
Room
Full
20
25
0.3
0.5
30
50
Room
40
75
Room
40
75
Protection
Current Limit Treshold Voltage
c
Current Limit Delay to Output
Soft-Start Current
Output Inhibit Voltage
Pulse Skipping Threshold
Voltage
VI(Limit)
VFB = 0, NI = VREF
td
VSENSE 0.85 V, See Figure 1
ISS
VSS(off)
Soft-Start Voltage to Disable Driver Output
VPS
V
mV
Mosfet Driver
Room
Full
Output High Voltage
VOH
IOUT = - 10 mA
Output Low Voltage
VOL
IOUT = 10 mA
Output Resistancec
ROUT
IOUT = 10 mA, Source or Sink
Rise Timec
Fall Time
c
tr
VCC - 0.3
VCC - 0.5
CL = 500 pF
tr
V
Ω
ns
Notes:
a. Room = 25 °C, Full = as determined by the operating temperature suffix.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. Guaranteed by design, not subject to production test.
d. CSTRAY ≤ 5 pF on COSC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TIMING WAVEFORMS
tr
10 ns
0.85
Current
Sense
50 %
0
td
Output
VCC
90 %
0
Figure 1.
www.vishay.com
4
Document Number: 70815
S11-0975–Rev. E, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless noted)
200
2 x 1000
47 pF
tr for CL = 2500 pF
Output Rise and Fall Time (ns)
f OUT (kHz)
100 pF
150 pF
200 pF
2 x 100
Note: These curves were measured
in a board with 3.5 pF of
external parasitic
capacitance.
150
tf for CL = 2500 pF
100
tr for CL = 1000 pF
tf for CL = 1000 pF
50
tr 10 % to 90 %
tf 90 % to 10 %
2 x 10
0
10
100
rOSC – Oscillator Resistance (k )
1000
9
Oscillator Frequency
16
17
12
VCC = 12 V
COSC = 47 pF
ROSC = 127 k
COSC = 47 pF
fs = 500 kHz
I CC – Supply Current (mA)
28
I CC – Supply Current (mA)
11
12
13
14
15
VCC – Supply Voltage (V)
Output Driver Rise and Fall Time
36
32
10
24
CL = 2500 pF
20
16
CL = 1000 pF
12
8
CL = 0 pF
9
CL = 1000 pF
6
3
CL = 0 pF
4
0
0
200
400
600
800
fOUT – Output Frequency (kHz)
0
1000
9
Supply Current vs. Output Frequency
10
11
12
13
14
15
VCC – Supply Voltage (V)
16
17
Supply Current vs. Supply Voltage
1.05
ROSC = 56 k
COSC = 100 pF
Switching Frequency (MHz)
1.00
0.95
0.90
0.85
8
9
10
11
12
13
14
15
VCC – Supply Voltage (V)
16
17
Switching Frequency vs. Supply Voltage
Document Number: 70815
S11-0975–Rev. E, 16-May-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
PIN CONFIGURATIONS AND ORDERING INFORMATION
+VIN
1
16
VCC
PWM/PSM
2
15
DR
VREF
3
14
-V IN
13
DMAX
12
VSC
+VIN
1
16
VCC
PWM/PSM
2
15
DR
VREF
3
14
-V IN
NI
4
13
DMAX
FB
5
SOIC
Si9119DY
12
SYNC
Top View
NI
4
FB
5
SOIC
Si9118DY
COMP
6
Top View
11
ICS
COMP
6
11
ICS
SS/EN
7
10
ILIMIT
SS/EN
7
10
ILIMIT
COSC
8
9
ROSC
COSC
8
9
ROSC
ORDERING INFORMATION
Part Number
Si9118DY-T1-E3
Temperature Range
Package
- 40 to 85 °C
SOIC-16
PIN DESCRIPTION
Pin Number
Symbol
Description
Input bus voltage ranging from 10 V to 200 V.
1
+VIN
2
PWM/PSM
3
VREF
4
NI
Non-inverting input of an error amplifier.
5
FB
Inverting input of an error amplifier.
Connected to VREF forces the converter into PWM mode. Connected to -VIN forces the converter into PSM
mode.
4 V reference voltage. Decouple with 0.1 µF ceramic capacitor.
6
COMP
Error amplifier output for external compensation network.
7
SS/EN
Programmable soft-start with external capacitor or externally controlled disable mode.
8
COSC
External capacitor to determine the switching frequency.
9
ROSC
External resistor to determine the switching frequency.
10
ILIMIT
Pulse by pulse peak current limiting pin. When the current sense voltage exceeds the current limit threshold,
the gate drive signal is terminated. ILIMIT is also used to sense the current in pulse skipping mode.
11
ICS
12
SYNC or VSC
13
DMAX
14
-VIN
Single point ground.
15
DR
Gate drive for the external MOSFET switch.
16
VCC
Supply voltage for the IC after the startup transition.
www.vishay.com
6
Current sense input to control feedback response.
Si9118: slope compensation pin. Si9119: clock synchronization pin. Logic high to low transition from external
signal synchronizes the internal clock frequency.
Sets the maximum duty cycle. Internally, the maximum duty cycle is clamped to 80 %.
Document Number: 70815
S11-0975–Rev. E, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
STANDARD APPLICATION CIRCUITS
VO
+VIN
VCC
PWM/PSM
ICS
VREF
DR
NI
-V IN
DMAX
FB
VSC
COMP
SS/EN
COSC
ILIMIT
ROSC
Si9420DY
TL431
- 48 V (- 42 to - 56 V)
Figure 2. Si9118 15 W Forward Converter Schematic
VCC
+VIN
PWM/PSM
ICS
DR
VREF
NI
-V IN
DMAX
FB
SYNC
COMP
COSC
SS/EN
ILIMIT
ROSC
Si9420DY
TL431
- 48 V (- 42 to - 56 V)
Figure 3. Si9119 Forward Converter With External Slope Compensation
Document Number: 70815
S11-0975–Rev. E, 16-May-11
www.vishay.com
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION
Start-Up
Si9118/Si9119 are designed with internal depletion
mode MOSFET capable of powering directly from the
high input bus voltage. This feature eliminates the
typical external start-up circuit saving valuable space
and cost. But, most of all, this feature improves the
converter efficiency during full load and has an even
greater impact on light load. With an input bus voltage
applied to the +VIN pin, the VCC voltage is regulated to
9.3 V. The UVLO circuit prevents the controller output
driver section from turning on, until VCC voltage
exceeds 8.7 V. In order to maximize converter
efficiency, the designer should provide an external
bootstrap winding to override the internal VCC
regulator. If external VCC voltage is greater than 9.3 V,
the internal depletion mode MOSFET regulator is
disabled and power is derived from the external VCC
supply. The VCC supply provides power to the internal
circuity as well as providing supply voltage to the gate
drive circuit.
Soft-Start/Enable
The soft-start time is externally programmable with
capacitor connected to the SS/EN pin. A constant
current source provides the current to the SS/EN pin to
generate a linear start-up time versus the capacitance
value. The SS/EN pin clamps the error amplifier output
voltage, limiting the rate of increase in duty cycle. By
controlling the rate of rise in duty cycle gradually, the
output voltage rises gradually preventing the output
voltage from overshooting. The SS/EN pin can also be
used to enable or disable the output driver section with
an external logic signal.
Synchronization
The synchronization to external clock is easily
accomplished by connecting the external clock into the
SYNC pin (Si9119 only). The logic high to low
transition synchronizes the clock. The external clock
frequency must be at least 5 % faster than the internal
clock frequency.
Reference Voltage
The reference voltage for the Si9118/Si9119 are set at
4.0 V. The reference voltage is not connected to the
non-inverting inputs of the error amplifier, therefore,
the minimum output voltage is not limited to reference
voltage. The VREF pin requires a 0.1 µF decoupling
capacitor.
Error Amplifier
The error amplifier gain-bandwidth product is critical
parameter which determines the transient response of
converter. The transient response is function of both
small and large signal responses. The small signal
www.vishay.com
8
response is determined by the feedback compensation
network while the large signal response is determined
by the inductor di/dt slew rate. Besides the inductance
value, the error amplifier gain-bandwidth determine the
converter response time. In order to minimize the
response time, Si9118/Si9119 is designed with a
2.7 MHz error amplifier gain-bandwidth product to
provide the widest converter bandwidth possible.
PWM Mode
The converter operates in PWM mode if the PWM/
PSM pin is connected to VREF pin or logic high. As the
load current and line voltage vary, the Si9118/Si9119
maintain constant switching frequency until they reach
minimum duty cycle. Once the output voltage
regulation is exceeded with minimum duty cycle, the
switching frequency will continue to decrease until
regulation is achieved. The switching frequency is
controlled by the external Rosc and Cosc as shown by
the typical oscillator frequency curve. In PWM mode,
output ripple noise is constant reducing EMI concerns
as well as simplifying the filter to minimize the system
noise.
Pulse Skipping Mode
If the PWM/PSM pin is connected to -VIN pin (logic
low), the converter can operate in either PWM or PSM
mode depending on the load current. The converter
automatically transitions from PWM to PSM or vise
versa to maintain output voltage regulation. In PSM
mode, the MOSFET switch is turned on until the peak
current sensed voltage reaches 100 mV and the output
voltage meets or exceeds its regulation voltage. The
converter is operating in pulse skipping mode because
each pulse delivers excess energy into the output
capacitor forcing the output voltage to exceed its
regulation voltage. By forcing the output voltage to
exceed the regulation voltage, succeeding pulses are
skipped until the output voltage drops below the
regulation point. Therefore, switching frequency will
continue to reduce during PSM control as the demand
for output current decreases. The pulse skipping mode
cuts down the switching losses, the dominant power
consumed during low output current, thereby
maintaining high efficiency throughout the entire load
range. With PWM/PSM pin in logic low state, the
converter transitions back into PWM mode, if the peak
current sensed voltage of 100 mV does not generate
the required output voltage. In the region between
pulse skipping mode and PWM mode, the controller
may transition between the two modes, delivering
spurts of pulses. This may cause the current waveform
to look irregular, but this will not overly affect the ripple
voltage. Even in this transitional mode, efficiency
remains high.
Document Number: 70815
S11-0975–Rev. E, 16-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si9118, Si9119
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION (CONT’D)
Programmable Duty Cycle Control
The maximum duty cycle limit is controlled by the
voltage on DMAX pin. A DMAX voltage of 3.2 V
generates
80 % duty cycle while 0.0 V generates
0 % duty cycle. The 80 % duty cycle is maximum
default condition at
1 MHz switching frequency. The
DMAX voltage can be easily generated using resistor
divider from the reference voltage.The maximum duty
cycle limitation will be different when the converter is
synchronized by an external frequency. If the internal
free running frequency is much slower than the
external SYNC signal (SYNC signal causes the
internal clock to reset before the Cosc voltage ramps
to 3.2 V) , duty cycle is determined by the one shot
discharge time of the oscillator capacitor (100 ns).
Therefore, with 1 MHz SYNC signal, maximum duty
cycle of 90 % can be achieved (100 ns is 10 % of
1 MHz). If the internal free running frequency is very
close to the external SYNC frequency (SYNC signal
causes the internal clock to reset somewhere between
3.2 V to 4 V), duty cycle is determined by the ratio of
Cosc voltage at the SYNC point and the 3.2 V. At this
condition, the maximum duty cycle can be greater than
90 %. Therefore, DMAX voltage must be modified in
order to maintain desired maximum duty cycle.
Slope Compensation
Slope compensation is necessary for duty cycles
greater than 50 % to stabilize the inner current loop
and maintain overall loop stability. In order to simplify
the slope compensation circuitry, the Si9118 provides
the buffered oscillator ramp signal, VSC to be used for
external slope compensation. VSC is only available
when DR is high. The VSC signal super-imposed with
actual current sense signal should be used by the
PWM comparator to determine the duty cycle. The
summation of this signal should be fed into ICS pin. For
optimum performance, proper slope compensation is
required. The amount of slope compensation is
determined by the resistors connected to the ICS pin.
The amplitude of the VSC signal is same as the COSC
pin voltage (≈ 4 V). For designs which use with SYNC
pin, instead of VSC pin, the converter can still operate
at duty cycles greater than 50 % by generating an
external slope compensation ramp using a
simple RC circuit from the MOSFET driver output pin
as shown on the application circuit.
Over Current Protection
Si9118/Si9119 are designed with a pulse-to-pulse
peak
current limiting protection circuit to protect itself, and
the load in case of a failure. The voltage across the
sense resistor is monitored continuously and if the
voltage reaches its trigger level, the duty cycle is
terminated. This limits the maximum current delivered
to the load. In order to improve the accuracy of over
current protection from traditional controllers, Si9118/
Si9119 are designed with separate ILIMIT and ICS pins.
Voltage on the ILIMIT pin does not sum in the traditional
slope compensation voltage, which adds error into the
detection level. ICS pin is used to sum the current
sense signal and the slope compensation for loop
stability.
Output Driver Stage
The DR pin is designed to drive a low-side N-Channel
MOSFET. The driver stage is sized to sink and source
peak currents up to 500 mA with VCC = 12 V. This
provides ample drive capability for 50 W of output
power.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see www.vishay.com/ppg?70815.
Document Number: 70815
S11-0975–Rev. E, 16-May-11
www.vishay.com
9
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOIC (NARROW):
16-LEAD (POWER IC ONLY)
JEDEC Part Number: MS-012
MILLIMETERS
16
15
14
13
12
11
10
Dim
A
A1
B
C
D
E
e
H
L
Ĭ
9
E
1
2
3
4
5
6
7
8
INCHES
Min
Max
Min
Max
1.35
1.75
0.053
0.069
0.10
0.20
0.004
0.008
0.38
0.51
0.015
0.020
0.18
0.23
0.007
0.009
9.80
10.00
0.385
0.393
3.80
4.00
0.149
0.157
1.27 BSC
0.050 BSC
5.80
6.20
0.228
0.244
0.50
0.93
0.020
0.037
0_
8_
0_
8_
ECN: S-40080—Rev. A, 02-Feb-04
DWG: 5912
H
D
C
All Leads
e
Document Number: 72807
28-Jan-04
B
A1
L
Ĭ
0.101 mm
0.004 IN
www.vishay.com
1
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2022
1
Document Number: 91000
工商网监
湘ICP备2023018690号
