SI91871DMP-26-E3

Si91871 Vishay Siliconix 300-mA Ultra Low-Noise LDO Regulator With Discharge Option FEATURES D D D D D D D D D D D D D Ultra Low Dropout—300 mV at 300-mA Load Ultra Low Noise—30 mVRMS (10-Hz to 100-kHz) Shutdown Control 130-mA Ground Current at 300-mA Load 1.5% Guaranteed Output Voltage Accuracy 400-mA Peak Output Current Capability Uses Low ESR Ceramic Capacitors Fast Start-Up (50 ms) Fast Line and Load Transient Response (v 30 ms) 1-mA Maximum Shutdown Current Output Current Limit Reverse Battery Protection Built-in Short Circuit and Thermal Protection D Output, Auto-Discharge In Shutdown Mode D Fixed 1.2, 1.8, 2.5, 2.6, 2.8, 3.0, 3.3, 5.0-V Output Voltage Options D MLP33-5 PowerPAKr Package Available APPLICATIONS D Cellular Phones, Wireless Handsets D Noise-Sensitive Electronic Systems, Laptop and Palmtop Computers D PDAs D Pagers D Digital Cameras D MP3 Player D Wireless Modem DESCRIPTION The Si91871 is a 300-mA CMOS LDO (low dropout) voltage regulator. It is the perfect choice for low voltage, low power applications. An ultra low ground current makes this part attractive for battery operated power systems. The Si91871 also offers ultra low dropout voltage to prolong battery life in portable electronics. Systems requiring a quiet voltage source, such as RF applications, will benefit from the Si91871’s ultra low output noise. An external noise bypass capacitor connected to the device’s BP pin can further reduce the noise level. The Si91871 is designed to maintain regulation while delivering 400-mA peak current, making it ideal for systems that have a high surge current upon turn-on. pull-down circuit is built into the Si91871 to clamp the output voltage when it rises beyond normal regulation. The Si91871 automatically discharges the output voltage by connecting the output to ground through a 100-W n-channel MOSFET when the device is put in shutdown mode. The Si91871 features reverse battery protection to limit reverse current flow to approximately 1-mA in the event reversed battery is applied at the input, thus preventing damage to the IC. The Si91871 is available in both the standard and lead (Pb)-free 5-pin MLP33 PowerPAK packages and is specified to operate over the industrial temperature range of −40_C to 85_. For better transient response and regulation, an active TYPICAL APPLICATION CIRCUIT Si91871 VIN VIN VOUT VOUT 2.2 mF SD 2.2 mF SD GND BP 10 nF MLP33-5 Document Number: 72012 S-51147—Rev. F, 20-Jun-05 www.vishay.com 1 Si91871 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Thermal Resistance (qJA)a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55_C/W R(qJA)a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8_C/W Absolute Maximum Ratings Input Voltage, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −6.0 to 6.5 V Maximum Junction Temperature, TJ(max) . . . . . . . . . . . . . . . . . . . . . . . 150_C VSD (See Detailed Description) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 20 mW/_C above TA = 25_C Output Current, IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN + 0.3 V Package Power Dissipation, (Pd)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 W Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to 6 V CEB (Ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.01 mF Input Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VIN Operating Ambient Temperature, TA . . . . . . . . . . . . . . . . . . . . −40_C to 85_C Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . −40_C to 125_C Notes a. Maximum ESR of COUT: 0.2 W. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 300 mA CIN, COUTa (Ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 mF SPECIFICATIONS Test Conditions Unless Specified Limits Symbol TA = 25_C, VIN = VOUT(nom) ( )+1V IOUT = 1 mA, CIN = 2 mF, COUT = 2.0 mF VSD = 1.5 V −40 to 85_C Tempa Start-Up BP Current IOUT ON/OFF = High Room Input Voltage Range VIN Parameter VOUT w 1.8 18V Output Voltage Accuracy DVIN VIN − VOUT −3.5 1 3.5 Full −0.06 0.18 Full 0 0.3 From VIN = 5.5 V to 6 V Full 0 0.4 IOUT = 1 mA Room 1 Room 45 Full 50 90 Room 300 350 IOUT = 300 mA IOUT = 300 mA IGND IOUT = 0 mA Ground Pin Currente (VOUT(nom) u 3 V) Peak Output current www.vishay.com 2 IOUT = 300 mA IO(peak) 2.0 Full IOUT = 0 mA Ground Pin (VOUT(nom) v 3 V) 1 2.5 IOUT = 300 mA Currente, g −2.0 3.0 IOUT = 50 mA Dropout Voltaged, g (VOUT(nom) 2 6 V, V VIN w OUT( ) t 2.6 2 V) Room 1 IOUT = 50 mA d g d, Dropoutt V D Voltage lt (VOUT(nom) w 2.6 V) 6 1 From VIN = VOUT(nom) + 1 V to VOUT(nom) + 2 V VOUT w 0.95 x VOUT(nom). tPW = 2 ms 415 65 % %/V mV 100 Full 120 Room 400 Full 520 570 Room 100 Full 150 180 Room 130 Full 200 330 Room 110 Full 170 mA 200 Room 150 Full Full V 80 Full Room Unit mA 2 −2.5 VOUT(nom) Line Regulation (5-V Version) 1 Full −3.0 Line Regulation (VOUT v 3 V) Line Regulation (3.0 V < VOUT v3.6 V) Maxb Full VOUT = 1.2 1 2 V, V 1.5 15V 100 Typc Room 1 mA v IOUT v 300 mA DVOUT Minb 225 275 400 mA Document Number: 72012 S-51147—Rev. F, 20-Jun-05 Si91871 Vishay Siliconix SPECIFICATIONS Parameter Limits TA = 25_C, VIN = VOUT(nom) + 1 V IOUT = 1 mA, CIN = 2 mF, COUT = 2.0 mF VSD = 1.5 V −40 to 85_C Symbol Output Noise Voltage Ripple pp Rejection j Test Conditions Unless Specified VNOM = 2.6 V, BW = 10 Hz to 100 kHz, 0 mA t IOUT t 300 mA, CNOISE = 0.01 mF eN DVOUT/DVIN IOUT = 300 mA Tempa Minb Typc Room 30 f = 1 kHz Room 60 f = 10 kHz Room 40 f = 100 kHz Room 30 Dynamic Line Regulation DVO(line) VIN : VOUT(nom) + 1 V to VOUT(nom) + 2 V tr/tf = 2 ms, IOUT = 300 mA Room 20 Dynamic Load Regulation DVO(load) IOUT : 1 mA to 300 mA, tr/tf = 2 ms Room 20 Thermal Shutdown Junction Temperature TJ(S/D) Room 150 Thermal Hysteresis THYST Room 20 Maxb Unit mV(rms) dB mV _C C Reverse current IR VIN = −6.0 V Room 1 mA Short Circuit Current ISC VOUT = 0 V Room 700 mA Shutdown Shutdown Supply Current ICC(off) SD Pin Input Voltage VSD Auto Discharge Resistance R_DIS SD Pin Input Currentf IIN(SD) SD Hysteresis VSD = 0 V Room High = Regulator ON (Rising) Full Low = Regulator OFF (Falling) Full VSD = 1.5 V, VIN = 6 V VHYST(SD) VOUT Turn-On Time tON 0.1 1.5 1 VIN 0.4 mA V Room 100 W Room 0.7 mA Full 150 mV 50 ms VSD (See Figure 1), ILOAD = 100 nA Notes a. Room = 25_C, Full = −40 to 85_C. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at VOUT w 2 V are measured at VOUT = 3.3 V, while typical values for dropout voltage at VOUT < 2 V are measured at VOUT = 1.8 V. d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V differential, provided that VIN does not not drop below 2.0 V. e. Ground current is specified for normal operation as well as “drop-out” operation. f. The device’s shutdown pin includes a typical 2-MW internal pull-down resistor connected to ground. g. VOUT(nom) is VOUT when measured with a 1-V differential to VIN. TIMING WAVEFORMS VIN VSD tr v 1 ms 0V tON VNOM 0.95 VNOM VOUT FIGURE 1. Timing Diagram for Power-Up Document Number: 72012 S-51147—Rev. F, 20-Jun-05 www.vishay.com 3 Si91871 Vishay Siliconix PIN CONFIGURATION MLP33-5 PowerPAK SD BP GND 1 2 1 2 GND 5 5 VIN 3 GND 3 VOUT 4 GND 4 Top View Bottom View PIN DESCRIPTION Pin Number Name Function 1 SD By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused 2 BP Noise bypass pin. For low noise applications, a 0.01 mF ceramic capacitor should be connected from this pin to ground. 3 VIN Input supply pin. Bypass this pin with a 1-mF ceramic or tantalum capacitor to ground 4 VOUT Output voltage. Connect COUT between this pin and ground. 5 GND Ground pin. For better thermal capability, directly connected to large ground plane ORDERING INFORMATION www.vishay.com 4 Standard Part Number Lead (Pb)-Free Part Number Marking Voltage Si91871DMP-12-T1 Si91871DMP-12-E3 7112 1.2 Si91871DMP-18-T1 Si91871DMP-18-E3 7118 1.8 Si91871DMP-25-T1 Si91871DMP-25-E3 7125 2.5 Si91871DMP-26-T1 Si91871DMP-26-E3 7126 2.6 Si91871DMP-28-T1 Si91871DMP-28-E3 7128 2.8 Si91871DMP-30-T1 Si91871DMP-30-E3 7130 3.0 Si91871DMP-33-T1 Si91871DMP-33-E3 7133 3.3 Si91871DMP-50-T1 Si91871DMP-50-E3 7150 5.0 Temp. Range Pkg. −40 40 to 85_C MLP33 5 MLP33-5 Document Number: 72012 S-51147—Rev. F, 20-Jun-05 Si91871 Vishay Siliconix TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED) Normalized Output Voltage vs. Load Current 0.30 VIN = VOUT(nom) + 1 V VIN = VOUT(nom) + 1 V 0.15 Normalized VOUT vs. Temperature 0.4 0.2 −0.0 V OUT (%) Output Voltage (%) IOUT = 0 mA 0.00 −0.15 −0.30 −0.2 −0.6 −0.60 −0.8 0 50 100 150 200 250 IOUT = 150 mA −0.4 −0.45 −0.75 IOUT = 75 mA IOUT = 300 mA −1.0 −40 300 −15 Load Current (mA) GND Current vs. Load Current 150 10 35 60 85 Ambient Temperature (_C) VOUT = 3.0 V VIN = 4.0 V No Load GND Pin Current vs. Input Voltage 300 85_C 250 125 200 100 I GND ( mA) I GND ( mA) 25_C −40_C 150 85_C 25_C 100 −40_C 75 50 50 0 0 50 100 150 200 250 300 2 3 Load Current (mA) Power Supply Rejection 0 −20 4 5 6 7 Input Voltage (V) 750 Output Short Circuit Current vs. Temperature VOUT = 2.6 V CIN = 1 mF COUT = 1 mF ILOAD = 150 mA VOUT = 3.0 V 725 I SC (mA) Gain (dB) 700 −40 675 650 −60 625 −80 10 100 1000 10000 Frequency (Hz) Document Number: 72012 S-51147—Rev. F, 20-Jun-05 100000 1000000 600 −40 −15 10 35 60 85 AmbientTemperature (_C) www.vishay.com 5 Si91871 Vishay Siliconix TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED) Dropout Voltage vs. Load Current 350 VOUT = 3.0 V 300 VOUT = 3.0 V 2.5 250 2.0 V OUT (V) V DROP (mV) VIN − VOUT Transfer Characteristic 3.0 200 150 1.5 1.0 100 0.5 50 0 0.0 0 60 120 180 240 0 300 1 2 3 ILOAD (mA) 350 Dropout Voltage vs. Temperature Dropout Voltage (mV) V DROP (mV) 250 200 IOUT = 150 mA 100 6 250 200 150 IOUT = 150 mA IOUT = 75 mA 50 IOUT = 10 mA IOUT = 0 mA −25 0 25 50 75 100 Junction Temperature (_C) www.vishay.com IOUT = 300 mA 300 100 IOUT = 75 mA 50 0 −50 6 350 IOUT = 300 mA 150 5 Dropout Voltage vs. VOUT 400 VOUT = 3.0 V 300 4 VIN (V) 125 150 0 1.0 IOUT = 10 mA 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOUT Document Number: 72012 S-51147—Rev. F, 20-Jun-05 Si91871 Vishay Siliconix TYPICAL WAVEFORMS Load Transient Response-1 Load Transient Response-2 VOUT 10 mV/div VOUT 10 mV/div ILOAD 100 mA/div ILOAD 100 mA/div 20 ms/div 20 ms/div VOUT = 3.0 V COUT = 1 mF ILOAD = 1 to 150 mA trise = 2 msec VOUT = 3.0 V COUT = 1 mF ILOAD = 150 to 1 mA tfall = 2 msec LineTransient Response-1 LineTransient Respons-2 VOUT 10 mV/div VOUT 10 mV/div VIN 2 V/div VIN 2 V/div 20 ms/div 20 ms/div VINSTEP = 4 to 5 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA trise = 5 msec Document Number: 72012 S-51147—Rev. F, 20-Jun-05 VINSTEP = 5 to 4 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA tfall = 5 msec www.vishay.com 7 Si91871 Vishay Siliconix TYPICAL WAVEFORMS Output Noise Noise Spectrum Output Spectral Noise Density 10 VOUT 200 mV/div mVń ǸHz 0.01 4 ms/div 10 Hz VIN = 4 V VOUT = 3 V IOUT = 150 mA CNOISE = 0.01 mF BW = 10 Hz to 100 kHz 1 MHz VIN = 4 V VOUT = 3 V ILOAD = 150 mA CNOISE = 0.01 mF FUNCTIONAL BLOCK DIAGRAM Si91871 VIN Reverse Polarity Protection BP Reference − + VOUT Thermal Sensor Current Limit SD Shutdown Control GND www.vishay.com 8 Document Number: 72012 S-51147—Rev. F, 20-Jun-05 Si91871 Vishay Siliconix DETAILED DESCRIPTION The Si91871 is a low-noise, low drop-out and low quiescent current linear voltage regulator, packaged in a small footprint MLP33-5 package. The Si91871 can supply loads up to 300 mA. As shown in the block diagram, the circuit consists of a bandgap reference error, amplifier, p-channel pass transistor and feedback resistor string. An external bypass capacitor connected to the BP pin reduces noise at the output. Additional blocks, not shown in the block diagram, include a precise current limiter, reverse battery and current protection and thermal sensor. Thermal Overload Protection The thermal overload protection limits the total power dissipation and protects the device from being damaged. When the junction temperature exceeds 150_C, the device turns the p-channel pass transistor off. Reverse Battery Protection The Si91871 has a battery reverse protection circuitry that disconnects the internal circuitry when VIN drops below the GND voltage. There is no current drawn in such an event. When the SD pin is hardwired to VIN, the user must connect the SD pin to VIN via a 100-kW resistor if reverse battery protection is desired. Hardwiring the SD pin directly to the VIN pin is allowed when reverse battery protection is not desired. Noise Reduction An external 10-nF bypass capacitor at BP is used to create a low pass filter for noise reduction. The start-up time is fast, since a power-on circuit pre-charges the bypass capacitor. After the power-up sequence the pre-charge circuit is switched to standby mode in order to save current. It is therefore not recommended to use larger bypass capacitor values than 50 nF. When the circuit is used without a capacitor, stable operation is guaranteed. dissipation in the pass device, the thermal resistance of the package and the circuit board, and the ambient temperature. The power dissipation is defined as PD = (VIN – VOUT) * IOUT . Junction temperature is defined as TJ = TA + ((PD * (RθJC + RθCA)). To calculate the limits of performance, these equations must be rewritten. Allowable power dissipation is calculated using the equation PD = (TJ − TA )/ (RθJC + RθCA) While allowable output current is calculated using the equation IOUT = (TJ − TA )/ (RθJC + RθCA) * (VIN – VOUT). Ratings of the Si91871 that must be observed are TJmax = 125 _C, TAmax = 85 _C, (VIN – VOUT)max = 5.3 V, RθJC = 8 _C/W. The value of RθCA is dependent on the PC board used. The value of RθCA for the board used in device characterization is approximately 46 _C/W. Figure 1 shows the performance limits graphically for the Si91871 mounted on the circuit board used for thermal characterization. 0.35 Auto-Discharge The Si91871 VOUT has an internal 100-W (typ.) discharge path to ground when the SD pin is low. Safe Operating Area The ability of the Si91871 to supply current is ultimately dependent on the junction temperature of the pass device. Junction temperature is in turn dependent on power TA = 70_C 0.25 I OUT (A) Stability The circuit is stable with only a small output capacitor equal to 6 nF/mA (= 2 mF @ 300 mA). Since the bandwidth of the error amplifier is around 1−3 MHz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150-mA load current, an ESR