Product is End of Life 3/2014
Si9913
Vishay Siliconix
Half-Bridge MOSFET Driver for Switching Power Supplies
DESCRIPTION
FEATURES
The Si9913 is a dual MOSFET high-speed driver with breakbefore-make. It is designed to operate in high frequency dcdc switchmode power supplies. The high-side driver is bootstrapped to handle the high voltage slew rate associated with
"floating" high-side gate drivers. Each driver is capable of
switching a 3000 pF load with 60 ns propagation delay and
25 ns transition time. The Si9913 comes with internal breakbefore-make feature to prevent shoot-through current in the
external MOSFETs. A synchronous enable pin is used to
enable the low-side driver. When disabled, the OUTL is logic
low.
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The Si9913 is available in both standard and lead (Pb)-free
8-pin SOIC packages for operation over the industrial operation range (- 40 °C to 85 °C).
APPLICATIONS
4.5 to 5.5 V Operation
Undervoltage Lockout
250 kHz to 1 MHz Switching Frequency
Synchronous Switch Enable
One Input PWM Signal Generates Both Drive
Bootstrapped High-Side Drive
Operates from 4.5 to 30 V Supply
TTL/CMOS Compatible Input Levels
1 A Peak Drive Current
Break-Before-Make Circuit
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Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Mobile Computing CPU Core Power Converters
Standard-Synchronous Converters
High Frequency Switching Converters
FUNCTIONAL BLOCK DIAGRAM AND TRUTH TABLE
BOOT
VDD
D1
VDC
Q1
CBOOT
OUTH
Level Shift
TRUTH TABLE
OUTPUT
Undervoltage
VS
VDD
OUTL
IN
SYN
Q2
VS
SYN
VOUTH
L
L
L
L
H
H
H
H
L
L
L
H
H
H
L
H
IN
VOUTL
L
L
L
L
L
H
L
H
H
L
H
L
H
H
L
H
L
L
L
L
L
H
L
H
+
-
Document Number: 71343
S-40133-Rev. B, 16-Feb-04
VBBM
GND
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ABSOLUTE MAXIMUM RATINGS (TA = 25 °C unless otherwise noted)
Parameter
Symbol
Limit
Unit
Low Side Driver Supply Voltage
VDD
7.0
Input Voltage on IN
VIN
- 0.3 to VDD + 0.3
VSYN
- 0.3 to VDD + 0.3
Synchronous Pin Voltage
V
VBOOT
35.0
VBOOT - VS
7.0
TJ
- 40 to 125
Tstg
- 40 to 150
Power Dissipation (Note a and b)
PD
830
mW
Thermal Impedance
θJA
125
°C/W
300
°C
Bootstrap Voltage
High Side Driver (Bootstrap) Supply Voltage
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature (soldering 10 Sec)
°C
Notes:
a. Device Mounted with all leads soldered to P.C. Board.
b. Derate 8.3 W/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Bootstrap Voltage (High-Side Drain Voltage)
Logic Supply
Bootstrap Capacitor
Ambient Temperature
Symbol
Limit
VBOOT
4.5 to 30
Unit
VDD
4.5 to 5.5
CBOOT
100 n to 1 µ
F
TA
- 40 to 85
°C
V
SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VBOOT = 4.5 to 30 V, VDD = 4.5 to 5.5 V
TA = - 40 to 85 °C
Limits
Mina
Typb
Maxa
Unit
Power Supplies
VDD Supply
VDD
IDD Supply
IDD1(en)
SYN = H, IN = H, VS = 0 V
1000
IDD Supply
IDD2(en)
SYN = H, IN = L, VS = 0 V
500
IDD Supply
IDD3(dis)
SYN = L, IN = X, VS = 0 V
500
IDD Supply
IDD4(en)
SYN = H, IN = X, VS = 25 V, VBOOT = 30 V
200
IDD Supply
IDD5(dis)
SYN = L, IN = X, VS = 25 V, VBOOT = 30 V
200
IDD(en)
FIN = 300 kHz, SYN = High, Driving Si4412DY
IDD(dis)
FIN = 300 kHz, SYN = Low, Driving Si4412DY
IBOOT
VBOOT = 30 V, VS = 25 V, VOUTH = H
IDD Supply
Boot Strap Current
4.5
5.5
µA
9
mA
5
0.9
3
VBBM
1.1
3
Input High
VIH
0.7 x VDD
VDD + 0.3
Input Low
VIL
- 0.3
0.3 x VDD
Reference Voltage
Break-Before-Make Reference Voltage
V
Logic Inputs (SYN, IN)
V
Undervoltage Lockout
VDD Undervoltage
VUVL
VDD Undervoltage Hysteresis
VHYST
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2
VDD Rising
3.7
4.3
0.4
V
Document Number: 71343
S-40133-Rev. B, 16-Feb-04
Product is End of Life 3/2014
Si9913
Vishay Siliconix
SPECIFICATIONS
Symbol
Test Conditions Unless Specified
VBOOT = 4.5 to 30 V, VDD = 4.5 to 5.5 V
TA = - 40 to 85 °C
VFD1
Forward Current = 100 mA
OUTH Source Current
IOUT(H+)
VBOOT - VS = 3.7 V, VOUTH - VS = 2 V
OUTH Sink Current
IOUT(H-)
VBOOT - VS = 3.7 V, VOUTH - VS = 1 V
OUTL Source Current
IOUT(L+)
VDD = 4.5 V, VOUTL = 2 V
OUTL Sink Current
IOUT(L-)
VDD = 4.5 V, VOUTL = 1 V
Parameter
Limits
Mina
Typb
Maxa
0.8
1
Unit
Bootstrap Diode
Diode Forward Voltage
V
Output Drive Current
- 0.4
0.4
- 0.4
A
0.6
Timing (CLOAD = 3 nF)
OUTL Off Propagation Delay
tpdl(OUTL)
OUTL On Propagation Delay
tpdh(OUTL)
OUTH Off Propagation Delay
tpdl(OUTH)
OUTH On Propagation Delay
tpdh(OUTH)
OUTL Turn On Time
30
VDD = 4.5 V
20
30
VBOOT - VS = 4.5 V
tr(OUTL)
20
OUTL = 10 to 90 %
25
OUTL Turn Off Time
tf(OUTL)
OUTL = 90 to 10 %
25
OUTH Turn On Time
tr(OUTH)
OUTH - VS = 10 to 90 %
30
OUTH Turn Off Time
tf(OUTH)
OUTH - VS = 90 to 10 %
30
ns
Notes:
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
TIMING WAVEFORMS
IN
50 %
50 %
tpdh(OUTL)
tf(OUTL)
90 %
90 %
OUTL
10 %
10 %
tr(OUTL)
tpdl(OUTH)
tpdl(OUTL)
tf(OUTH)
tr(OUTH)
tpdh(OUTH)
OUTH
90 %
10 %
90 %
10 %
VS
Document Number: 71343
S-40133-Rev. B, 16-Feb-04
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Si9913
Vishay Siliconix
PIN CONFIGURATION
SO-8
OUTH
1
8
VS
GND
2
7
BOOT
IN
3
6
VDD
SYN
4
5
OUTL
Top View
PIN DESCRIPTION
Pin Number
Name
1
OUTH
Output drive for upper MOSFET.
Function
2
GND
Ground supply
3
IN
4
SYN
Synchronous enable. When logic is high, the low-side driver is enabled.
5
OUTL
Output drive for lower MOSFET.
6
VDD
7
BOOT
8
VS
CMOS level input signal. Controls both output drives.
Input power supply
Floating bootstrap supply for the upper MOSFET
Floating GND for the upper MOSFET. VS is connected to the buck switching node and the source side of the upper
MOSFET.
ORDERING INFORMATION
Part Number
Temperature Range
Package
- 40 to 85 °C
Tape and Reel
Si9913DY
Bulk
Si9913DY-T1
Si9913DY-T1-E3
Lead (Pb)-free Tape and Reel
Eval Kit
Temperature Range
Board Type
Si9913DB
- 40 to 85 °C
Surface Mount
TYPICAL WAVEFORMS
VS
CL = Si4412DY
OUTH
OUTH
See Figure 1
See Figure 1
OUTL
OUTL
IN
IN
Si9912 tr, tf, tpd
Driver On Switch Delay
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4
CL = Si4412DY
VS
Si9912 tr, tf, tpd
Driver Off Switch Delay
Document Number: 71343
S-40133-Rev. B, 16-Feb-04
Product is End of Life 3/2014
Si9913
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C unless noted
50
30
See Figure 2
40
Rise and Fall times (ns)
See Figure 1
Current (mA)
10
tr(OUTH)
30
tf(OUTL)
tf(OUTH)
20
tr(OUTL)
10
0
1
1
10
100
0.3
1000
Frequency (kHz)
Rise and Fall Time vs. CLOAD
5
0.5 A
See Figure 3
4
Output Voltage Drop (V)
Output Voltage Drop (V)
-1
-2
1A
-3
1.5 A
2A
3
1.5 A
2
1A
1
-4
See Figure 3
3.5
4.0
4.5
5.0
5.5
0
3.0
6.0
0.5 A
3.5
4.0
4.5
5.0
Supply Voltage (V)
Supply Voltage (V)
VOUT(H+) vs. Supply
VOUT(H-) vs. Supply
5.5
6.0
2.5
0
0.5 A
See Figure 3
-1
2.0
Output Voltage Drop (V)
1A
Output Voltage Drop (V)
10
IDD Supply Current vs. Frequency
0
-5
3.0
3
1
Load Capacitance (nF)
-2
1.5 A
-3
-4
2A
2A
1.5
1.5 A
1.0
1A
0.5
0.5 A
-5
See Figure 3
-6
4.0
4.5
5.0
Supply Voltage (V)
VOUT(L+) vs. Supply
Document Number: 71343
S-40133-Rev. B, 16-Feb-04
5.5
6.0
0.0
4.0
4.5
5.0
5.5
6.0
Supply Voltage (V)
VOUT(L-) vs. Supply
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Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C unless noted
5
0
See Figure 3
See Figure 3
0.5 A
4
Output Voltage Drop (V)
Output Voltage Drop (V)
-1
-2
1A
-3
2A
1A
0.5 A
- 25
0
25
50
75
0
- 50
100
0
25
50
Temperature (°C)
VOUT(H+) vs. Temperature
VOUT(H-) vs. Temperature
75
100
75
100
2.0
0.5 A
See Figure 3
-1
1A
Output Voltage Drop (V)
Output Voltage Drop (V)
- 25
Temperature (°C)
0
-2
1.5 A
-3
1.5
2A
1.0
1.5 A
1A
0.5
0.5 A
-4
2A
-5
- 50
1.5 A
2
1
-4
-5
- 50
3
- 25
0
See Figure 3
25
50
75
100
Temperature (°C)
VOUT(L+) vs. Temperature
0.0
- 50
- 25
0
25
50
Temperature (°C)
VOUT(L-) vs. Temperature
THEORY OF OPERATION
Break-Before-Make Function
Under Voltage Lockout Function
The Si9913 has an internal break-before-make function to
ensure that both high-side and low-side MOSFETs are not
turned on at the same time. The high-side drive (OUTH) will
not turn on until the low-side gate drive voltage (measured at
the OUTL pin) is less than VBBM, thus ensuring that the lowside MOSFET is turned off. The low-side drive (OUTL) will
not turn on until the voltage at the MOSFET half-bridge output (measured at the VS pin) is less than VBBM, thus ensuring
that the high-side MOSFET is turned off.
The Si9913 has an internal under-voltage lockout feature to
prevent driving the MOSFET gates when the supply voltage
(at VDD) is less than the under-voltage lockout specification
(VUVL). This prevents the output MOSFETs from being
turned on without sufficient gate voltage to ensure they are
fully on. There is hysteresis included in this feature to prevent
lockout from cycling on and off.
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Document Number: 71343
S-40133-Rev. B, 16-Feb-04
Product is End of Life 3/2014
Si9913
Vishay Siliconix
time. This is particularly useful for discontinuous operation
under light load or pulse skipping mode, where there is a long
off time, because it prevents current flowing back from the
output to ground during the off time.
Bootstrap Supply Operation
(see Functional Block Diagram)
The power to drive the high-side MOSFET (Q2) gate comes
from the bootstrap capacitor (CBOOT). This capacitor
charges through D1 during the time when the low-side MOSFET is on (VS is at GND potential ), and then provides the
necessary charge to turn on the high-side MOSFET. CBOOT
should be sized to be greater than ten times the high-side
MOSFET gate capacitance, and large enough to supply the
bootstrap current (IBOOT) during the high-side on time, without significant voltage droop.
Layout Considerations
There are a few critical layout considerations for these parts.
Firstly, the IC must be decoupled as closely as possible to
the power pins. Secondly the IC should be placed physically
close to the high- and low-side MOSFETs it is driving. The
major consideration is that the MOSFET gates must be
charged or discharged in a few nanoseconds, and the peak
current to do this is of the order of 1 A. This current must flow
from the decoupling and bootstrap capacitors to the IC, and
from the output driver pin to the MOSFET gate, returning
from the MOSFET source to the IC. The aim of the layout is
to reduce the parasitic inductance of these current paths as
much as possible. This is accomplished by making these
traces as short as possible, and also running trace and its
Synchronous Enable
The synchronous enable pin serves to enable and disable
the drive to the low-side MOSFET gate. With SYN high, the
low-side MOSFET is driven on and off in antiphase with the
high-side MOSFET to form a synchronous rectifier. This
improves efficiency at high load currents because the flyback
current is carried by the MOSFET, thus eliminating the diode
drop. With SYN low, the low-side MOSFET is held off all the
APPLICATIONS
5
6
7
8
+ VDC
Q1
4
8
OUTH
BOOT
3
6
GND
15 µH
1 µF
C5
VDD
OUTL
5
C2
0.1 µF
RLOAD
Q2
4
Si9913
Si4412
1
2
3
SYN
C1
0.1 µF
5
6
7
8
7
IN
Enable
L1
VS
2
4
Si4412
1
2
3
1
GND
15 µF
C4 +
+5V
U1
PWM IN
0.1 µF
C3
GND
GND
Figure 1. Typical Applications Schematic Circuit Used to Obtain Typical Rising and Falling Switching Waveforms
Document Number: 71343
S-40133-Rev. B, 16-Feb-04
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Product is End of Life 3/2014
Si9913
Vishay Siliconix
+5V
+5V
U1
U1
1
8
OUTH
VS
2
GND
PWM IN
IN
4
SYN
7
2
6
3
OUTL
Si9913
4
5
CLOAD
C8
Figure 2. Capacitive Load Test Circuit Used to Measure
Rise and Fall Times vs. Capacitance
6
VDD
SYN
OUTL
Si9913
5
ISRC
C2
0.1 µF
C2
0.1 µF
GND
BOOT
IN
Input
ISRC
7
GND
VDD
VS
OUTH
BOOT
3
8
1
CLOAD
C9
GND
Figure 3. Load Test Schematic Circuit Used to Measure
Driver Output Impedance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?71343.
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Document Number: 71343
S-40133-Rev. B, 16-Feb-04
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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Revision: 02-Oct-12
1
Document Number: 91000