SiC414, SiC424
www.vishay.com
Vishay Siliconix
6 A, microBUCK® SiC414, SiC424
Integrated Buck Regulator with 5 V LDO
FEATURES
• High efficiency > 95 %
• 6 A continuous output current capability
• Integrated bootstrap switch
• Integrated 5 V / 200 mA LDO with bypass logic
• Temperature compensated current limit
• Pseudo fixed-frequency adaptive on-time control
• All ceramic solution enabled
• Programmable input UVLO threshold
DESCRIPTION
• Independent enable pin for switcher and LDO
The Vishay Siliconix SiC414 and SiC424 are an advanced
stand-alone synchronous buck regulator featuring
integrated power MOSFETs, bootstrap switch, and an
internal 5 VLDO in a space-saving PowerPAK®
MLP28-44GW package.
• Selectable ultrasonic power-save mode (SiC414)
The SiC414 and SiC424 are capable of operating with all
ceramic solutions and switching frequencies up to 1 MHz.
The programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency and
used to drive external n-channel MOSFETs or other loads.
• Power good output and over voltage protection
Additional features include cycle-by-cycle current limit,
voltage soft-start, under voltage protection, programmable
over current protection, soft shutdown, and selectable
power-save. The Vishay Siliconix SiC414 and SiC424 also
provides an enable input and a power good output.
• Selectable power-save mode (SiC424)
• Internal soft-start and soft-shutdown
• 1 % internal reference voltage
• PowerCAD Simulation software available at
www.vishay.com/power-ics/powercad-list/
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Notebook, desktop, and server computers
• Digital HDTV and digital consumer applications
• Networking and telecommunication equipment
• Printers, DSL, and STB applications
• Embedded applications
• Point of load power supplies
PRIMARY CHARACTERISTICS
3 V to 28 V
Output voltage range
0.75 V to 5.5 V
Operating frequency
200 kHz to 1 MHz
EN/PSV (Tri-State)
3.3 V
6A
PGOOD
95 %
2 V5V
3 AGND
VIN
PAD1
AGND
LX
AGND
1 FB
EN/PSV
ENL
PowerPAK MLP28-44GW
TON
28 27 26 25 24
Package
23 22
PGND 19
PAD2
VIN
S20-0483-Rev. D, 29-Jun-2020
PGND 18
PGND 17
PGND 16
VIN
9
10 11 12
LX
VIN
8
PGND
VIN
VIN
6 VLDO
7 BST
VOUT
LX 21
LX 20
PAD3
LX
4 VOUT
5 VIN
PGOOD
Peak efficiency
LDO_EN
VOUT
PGND
Continuous output current
TYPICAL APPLICATION CIRCUIT AND
PACKAGE OPTION
ILIM
Input voltage range
LX 15
13 14
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SiC414, SiC424
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28 27 26 25
2
AGND
3
VOUT
4
PGOOD
ILIM
21
PAD1
AGND
PAD3
LX
10
11
12
13
VIN
VIN
LX
PGND
VIN
7
9
6
BST
VIN
VLDO
8
5
VIN
VIN
PAD2
LX
20
LX
19
PGND
18
PGND
17
PGND
16
PGND
15
LX
14
1
24 23 22
PGND
FB
V5V
LX
EN/PSV
AGND
ENL
TON
PIN CONFIGURATION (top view)
PIN DESCRIPTION
PIN NUMBER
SYMBOL
DESCRIPTION
1
FB
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from VOUT to AGND
2
V5V
Bias input for internal analog circuits and gate drives - connect to external 3 V or 5 V supply or bias
connection to VLDO
3, 26, PAD 1
AGND
Analog ground
4
VOUT
Switcher output voltage sense pin, and also the input to the internal switch-over between VOUT and VLDO
5, 8 to 11, PAD 2
VIN
6
VLDO
5 V LDO output
7
BST
Bootstrap pin - connect a capacitor from BST to LXBST to develop the floating supply for the high side
gate drive
12
LXBST
15, 20, 21, PAD 3
LX
13, 14, 16 to 19
PGND
22
PGOOD
23
ILIM
24
LXS
Input supply voltage
LX Boost - connect to the BST capacitor
Switching (Phase) node
Power ground
Open-drain power good indicator. High impedance indicates power is good. An external pull-up resistor
is required
Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS
LX sense - connect to RILIM resistor
Enable / power save input for the switching regulator - connect to AGND to disable the switching regulator.
Float to operate in forced continuous mode (power save disabled).
For SiC414, connect to V5V to operate with ultrasonic power save mode enabled.
For SiC424, connect to V5V to operate with power save mode enabled with no minimum frequency
25
EN / PSV
27
tON
On-time programming input - set the on-time by connecting through a resistor to AGND
28
ENL
Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic to +3 V for logic
control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND
ORDERING INFORMATION
PART NUMBER
PACKAGE
SiC414CD-T1-GE3
PowerPAK MLP28-44GW
SiC424CD-T1-GE3
PowerPAK MLP28-44GW
SiC414DB
S20-0483-Rev. D, 29-Jun-2020
Reference board
Document Number: 63388
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SiC414, SiC424
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Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
2
V5V
22
PGOOD
V5V
5, 8 to 11, PAD2
25
EN/PSV
AGND
VIN
VIN
V5V
Reference
3, 26, PAD1
BST
Control and Status
7
DL
Soft Start
+
FB
-
1
On-Time
Generator
Gate Drive
Control
LX
12, 15, 20, 21,
24 PAD3
V5V
FB Comparator
TON
PGND
27
13, 14, 16 to 19
Zero Cross
Detector
VOUT
4
VLDO
6
Y
A
B
MUX
ILIM
Valley1-Limit
Bypass Comparator
23
VIN
LDO
28
ENL
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER
CONDITIONS
LIMITS
VIN
to PGND
-0.3 to 30
LX
to PGND
-0.3 to 30
LX (transient < 100 ns)
to PGND
-2 to 30
EN / PSV, PGOOD, ILIM
to GND
-0.3 to + (V5V + 0.3)
-0.3 to + (V5V + 0.3)
VOUT, VLDO, FB
to GND
V5V
to PGND
-0.3 to 6
tON
to PGND
-0.3 to + (V5V - 1.5)
to LX
-0.3 to 6
BST
to PGND
UNIT
V
-0.3 to 35
ENL
-0.3 to VIN
AGND to PGND
-0.3 to 0.3
Temperature
Maximum junction temperature
150
Storage temperature
-65 to +150
°C
Power Dissipation
Junction to ambient thermal impedance (RthJA) b
Maximum power dissipation
IC Section
43
Ambient temperature = 25 °C
3.4
Ambient temperature = 100 °C
1.3
HBM
2
°C/W
W
ESD Protection
Electronic discharge protection
kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating / conditions for extended periods may affect device reliability.
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63388
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SiC414, SiC424
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RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)
PARAMETER
VIN
MIN.
TYP.
MAX.
3
-
28
V5V to PGND
3
-
5.5
VOUT to PGND
0.75
-
5.5
UNIT
V
Temperature
Recommended ambient temperature
-40 to +85
°C
Note
• For proper operation, the device should be used within the recommended conditions
ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 12 V, V5V = 5 V, TA = +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
TJ = < 125 °C
MIN.
TYP.
MAX.
Sensed at ENL pin, rising edge
2.4
2.6
2.95
Sensed at ENL pin, falling edge
2.23
2.4
2.57
-
0.2
-
Measured at VDD pin, rising edge
2.5
2.9
3.0
Measured at VDD pin, falling edge
2.4
2.7
2.9
-
0.2
-
EN / PSV, ENL = 0 V, VIN = 28 V
-
8.5
20
Standby mode:
ENL = V5V, EN / PSV = 0 V
-
130
-
EN / PSV, ENL = 0 V, V5V = 5 V
-
3
7
UNIT
Input Supplies
VIN UVLO threshold voltage a
(not available for V5V < 4.5 V)
VIN UVLO hysteresis
V5V UVLO threshold voltage
VDD UVLO hysteresis
VIN supply current
VUVLO
VUVLO_HYS
VUVLO
VUVLO_HYS
IIN
V5V supply current
IDD
EN / PSV, ENL = 0 V, V5V = 3 V
-
2
-
SiC414, EN/PSV = V5V, no load,
(fsw = 25 kHz), VFB > 0.75 V b
-
1
-
SiC424, EN/PSV = V5V, no load,
VFB > 0.75 V b
-
0.4
-
V5V = 5 V, fsw = 250 kHz,
EN / PSV = floating, no load b
-
4
-
V5V = 5 V, fsw = 250 kHz,
EN / PSV = floating, no load b
-
2.5
-
V
μA
mA
Controller
FB comparator threshold
VFB
Frequency range b
fsw
Static VIN and load, -40 °C to +85 °C,
V5V = 3 V or 5 V
0.7425 0.7500 0.7575
V
Continuous mode
200
-
1000
Minimum fSW, (SiC414 only),
EN/PSV= V5V, no load
-
25
-
-
10
-
1350
1500
1650
-
80
-
V5V = 5 V
-
320
-
V5V = 3 V
-
390
-
tSS
-
1.7
-
ms
RO-IN
-
500
-
k
-3
0
+3
mV
Bootstrap switch resistance
kHz
Timing
On-time
tON
Minimum on-time b
Minimum off-time
b
Continuous mode operation VIN = 15 V,
VOUT = 3 V, fSW = 300 kHz, Rton = 133 k
tON, min.
tOFF, min.
ns
Soft Start
Soft start Time b
Analog Inputs/Outputs
VOUT input resistance
Current Sense
Zero-crossing detector threshold voltage
S20-0483-Rev. D, 29-Jun-2020
VSense-th
LX-PGND
Document Number: 63388
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SiC414, SiC424
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ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 12 V, V5V = 5 V, TA = +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
TJ = < 125 °C
MIN.
TYP.
MAX.
Upper limit,
VFB > internal reference 750 mV
-
+20
-
Lower limit,
VFB < internal reference 750 mV
-
-10
-
V5V = 5 V
-
4
-
V5V = 3 V
-
2
-
UNIT
Power Good
Power good threshold voltage
PG_VTH_UPPER
%
Start-up delay time
(between PWM enable and PGOOD high)
PG_Td
Fault (noise-immunity) delay time b
PG_ICC
-
5
-
μs
Power good leakage current
PG_ILK
-
-
1
μA
PG_RDS-ON
-
10
-
3
4
5
A
-
8
-
μA
mV
Power good on-resistance
ms
Fault Protection
Valley current limit
V5V = 5 V, RILIM = 5 k
ILIM source current
ILIM
ILIM comparator offset voltage
VILM-LK
With respect to AGND
-8
0
+8
Output under voltage fault
VOUV_Fault
VFB with respect to Internal 750 mV
reference, 8 consecutive clocks
-
-25
-
Smart power-save protection
threshold voltage b
PSAVE_VTH
VFB with respect to internal 750 mV
reference
-
+10
-
VFB with respect to internal 750 mV
reference
-
+20
-
-
5
-
μs
10 °C hysteresis
-
150
-
°C
1
-
-
-
-
0.4
45
-
100
1V
-
42
Over voltage protection threshold
Over voltage fault delay
b
Over temperature shutdown b
tOV-Delay
TShut
%
Logic Inputs / Outputs
Logic input high voltage
VIH
Logic input low voltage
VIL
EN / PSV
input for PSAVE operation b
ENL
% of V5V
EN / PSV
input for forced continuous operation b
EN / PSV input for disabling switcher
EN / PSV input bias current
IEN
ENL input bias current
FB input bias current
FBL_ILK
V
%
0
-
0.4
EN / PSV = V5V or AGND
-10
-
+10
VIN = 28 V
-
11
18
FB = V5V or AGND
-1
-
+1
V
μA
Linear Dropout Regulator
VLDO accuracy
VLDO_ACC
LDO current limit
LDO_ILIM
VLDO load = 10 mA
4.9
5
5.1
Start-up and foldback, VIN = 12 V
-
115
-
Operating current limit, VIN = 12 V
135
200
-
V
mA
VLDO to VOUT switch-over threshold c
VLDO-BPS
-140
-
+140
VLDO to VOUT non-switch-over threshold c
VLDO-NBPS
-450
-
+450
VOUT = 5 V
-
2
-
From VIN to VVLDO, VVLDO = 5 V,
IVLDO = 100 mA
-
1.2
-
V
VLDO to VOUT switch-over resistance
LDO drop out voltage
d
RLDO
mV
Notes
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference
b. Guaranteed by design
c. The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT
d. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63388
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ELECTRICAL CHARACTERISTICS
90
90
80
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz
80
70
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A)
Efficiency (%)
Efficiency (%)
60
50
40
30
70
60
50
20
40
10
0
30
0
IOUT (A)
3
4
IOUT (A)
Efficiency vs. IOUT
(in Continuous Conduction Mode)
Efficiency vs. IOUT
(in Power-Save-Mode)
1
2
3
4
5
6
0
7
1.05
1.05
1.04
1.04
1.03
1
2
5
6
7
1.03
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A)
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz
1.02
1.01
VOUT (V)
VOUT (V)
1.02
1
0.99
1.01
1
0.99
0.98
0.98
0.97
0.97
0.96
0.96
0.95
0.95
0
1
2
3
4
5
6
7
IOUT (A)
0
3
4
IOUT (A)
VOUT vs. IOUT
(in Continuous Conduction Mode)
VOUT vs. IOUT
(in Power-Save-Mode)
1.05
1.05
1.04
1.04
1.03
1
2
5
6
7
21
24
1.03
VOUT = 1 V, IOUT = 0 A
1.02
1.02
1.01
1.01
VOUT (V)
VOUT (V)
VOUT = 1 V, IOUT = 6 A
1
0.99
1
0.99
0.98
0.98
0.97
0.97
0.96
0.96
0.95
0.95
3
6
9
12
15
VIN (V)
18
21
24
VOUT vs. VIN at IOUT = 0 A
(in Continuous Conduction Mode, fSW = 500 kHz)
S20-0483-Rev. D, 29-Jun-2020
3
6
9
12
15
VIN (V)
18
VOUT vs. VIN at IOUT = 6 A
(in Continuous Conduction Mode, fSW = 500 kHz)
Document Number: 63388
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ELECTRICAL CHARACTERISTICS
1.05
50
1.04
45
1.03
40
VOUT = 1 V, IOUT = 0 A
VOUT Ripple (mV)
VOUT (V)
1.02
1.01
1
0.99
0.98
35
30
VOUT = 1 V, IOUT = 6 A, FSW = 500 kHz
25
20
15
0.97
10
0.96
5
0.95
0
3
6
9
12
15
VIN (V)
18
21
24
0
5
15
20
25
VIN (V)
VOUT vs. VIN
(IOUT = 0 A in Power-Save-Mode)
VOUT Ripple vs. VIN
(IOUT = 6 A in Continuous Conduction Mode)
50
50
45
45
40
40
VOUT = 1 V, IOUT = 0 A, FSW = 500 kHz
VOUT = 1 V, IOUT = 0 A, PSV Mode
35
VOUT Ripple (mV)
VOUT Ripple (mV)
10
30
25
20
35
30
25
20
15
15
10
10
5
5
0
0
0
5
10
15
20
25
0
5
10
15
20
25
VIN (V)
VIN (V)
VOUT Ripple vs. VIN
(IOUT = 0 A in Continuous Conduction Mode)
VOUT Ripple vs. VIN
(IOUT = 0 A in Power-Save-Mode)
520
550
470
525
420
500
FSW (kHz)
FSW (kHz)
370
475
450
425
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A)
320
270
220
170
400
VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A)
120
375
70
350
20
0
1
2
3
4
IOUT (A)
5
6
fSW vs. IOUT
(in Continuous Conduction Mode)
S20-0483-Rev. D, 29-Jun-2020
7
0
1
2
3
4
IOUT (A)
5
6
7
fSW vs. IOUT
(in Power-Save-Mode)
Document Number: 63388
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ELECTRICAL CHARACTERISTICS
LX Switching Node
2V/div.
2ms/div
Output Ripple Voltage
20 mV/div.
2 ms/div
VOUT Ripple in Continuous Conduction Mode (No Load)
(VIN = 12 V, VOUT = 1 V, fSW = 500 kHz)
Output Current
2 A/div.
5 µs/div.
VOUT Ripple in Power Save Mode (No Load)
(VIN = 12 V, VOUT = 1 V)
Output Current
2 A/div.
5 µs/div.
Output Voltage
50 mV/div.
5 µs/div.
AC Coupling
Output Voltage
50 mV/div.
5 µs/div.
AC Coupling
Transient Response in Continuous Conduction Mode
(0.2 A to 6 A)
(VIN = 12 V, VOUT = 1 V, fSW = 500 kHz)
Transient Response in Continuous Conduction Mode
(6 A to 0.2 A)
(VIN = 12 V, VOUT = 1 V, fSW = 500 kHz)
Output Current
2 A/div.
5 µs/div.
Output Current
2 A/div.
5 µs/div.
Output Voltage
50 mV/div.
5 µs/div.
AC Coupling
Output Voltage
50 mV/div.
5 µs/div.
AC Coupling
Transient Response in Power Save Mode
(0.2 A to 6 A)
(VIN = 12 V, VOUT = 1 V, fSW = 500 kHz at 6A)
S20-0483-Rev. D, 29-Jun-2020
Transient Response in Power Save Mode
(6 A to 0.2 A)
(VIN = 12 V, VOUT = 1 V, fSW = 500 kHz at 6 A)
Document Number: 63388
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ELECTRICAL CHARACTERISTICS
Output Voltage
500 mV/div.
5 ms/div.
Output Current
5 A/div.
5 ms/div.
LX Switching Node
10 V/div. 5 ms/div.
Power Good Signal
5 V/div. 5 ms/div.
Start-up with VIN Ramping up
(VIN = 12 V, VOUT = 1 V, fSW = 500 kHz)
Over Current Protection
(VIN = 12 V, VOUT = 1 V, fSW = 500 kHz)
APPLICATIONS INFORMATION
Device Overview
The SiC414 and SiC424 are a step down synchronous buck
DC/DC converter with integrated power FETs and
programmable LDO. The device is capable of 6 A operation
at very high efficiency in a tiny 4 mm x 4 mm - 28 pin
package. The programmable operating frequency range of
200 kHz to 1 MHz, enables the user to optimize the solution
for minimum board space and optimum efficiency.
The buck controller employs pseudo-fixed frequency
adaptive on-time control. This control scheme allows fast
transient response thereby lowering the size of the power
components used in the system.
tON
VIN
VLX
CIN
VFB
Q1
VLX
FB threshold
VOUT
L
Q2
ESR
FB
+
COUT
Input Voltage Range
The SiC414 and SiC424 requires two input supplies for
normal operation: VIN and V5V. VIN operates over the wide
range from 3 V to 28 V. V5V requires a 3.3 V or 5 V supply
input that can be an external source or the internal LDO
configured to supply 5 V.
Pseudo-Fixed Frequency Adaptive On-Time Control
The PWM control method used by the SiC414 and SiC424
is pseudo-fixed frequency, adaptive on-time, as shown in
Fig. 1. The ripple voltage generated at the output capacitor
ESR is used as a PWM ramp signal. This ripple is used to
trigger the on-time of the controller.
The adaptive on-time is determined by an internal one-shot
timer. When the one-shot is triggered by the output ripple,
the device sends a single on-time pulse to the high side
MOSFET. The pulse period is determined by VOUT and VIN;
the period is proportional to output voltage and inversely
proportional to input voltage. With this adaptive on-time
arrangement, the device automatically anticipates the
on-time needed to regulate VOUT for the present VIN
condition and at the selected frequency.
Fig. 1 - PWM Control Method, VOUT Ripple
The adaptive on-time control has significant advantages
over traditional control methods used in the controllers
today.
• Reduced component count by eliminating DCR sense or
current sense resistor as no need of a sensing inductor
current.
• Reduced saves external components used for
compensation by eliminating the no error amplifier and
other components.
• Ultra fast transient response because of fast loop,
absence of error amplifier speeds up the transient
response.
• Predictable frequency spread because of constant
on-time architecture.
• Fast transient response enables operation with minimum
output capacitance Overall, superior performance
compared to fixed frequency architectures.
Overall, superior performance compared to fixed frequency
architectures.
S20-0483-Rev. D, 29-Jun-2020
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On-Time One-Shot Generator (tON) and Operating
Frequency
The Fig. 2 shows the on-chip implementation of on-time
generation. The FB Comparator output goes high when VFB
is less than the internal 750 mV reference. This feeds into the
gate drive and turns on the high side MOSFET, and also
starts the one-shot timer. The one-shot timer uses an
internal comparator and a capacitor. One comparator input
is connected to VOUT, the other input is connected to the
capacitor. When the on-time begins, the internal capacitor
charges from zero volts through a current which is
proportional to VIN. When the capacitor voltage reaches
VOUT, the on-time is completed and the high side MOSFET
turns off.
Gate
drives
FB comparator
FB
VREF
VOUT
VIN
Rton
+
VIN
DH
Q1
VLX
DL
Q2
COUT
• The zero cross detector senses that the voltage on the LX
node is below ground. Power save is activated when a
zero crossing is detected.
tON limitations and V5V Supply Voltage
For V5V below 4.5 V, the tON accuracy may be limited by the
input voltage.
The original RtON equation is accurate if VIN satisfies the
below relation over the entire VIN range:
VIN < (V5V - 1.6 V) x 10
If VIN exceeds (V5V - 1.6 V) x 10, for all or part of the VIN
range, the RtON equation is not accurate. In all cases where
VIN > (V5V - 1.6 V) x 10, the RtON equation must be modified
as follows.
VOUT
L
ESR
One-shot
timer
• VFB falls below the 750 mV reference.
FB
+
On-time = K x Rton x (VOUT/VIN)
Fig. 2 - On-Time Generation
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN. Under
steady-state conditions, the switching frequency can be
determined from the on-time by the following equation.
RtON =
(V5V - 1.6 V) x 10
1
- 400 Ω x
VOUT
25 pF x fsw
Note that when VIN > (V5V - 1.6 V) x 10, the actual on-time
is fixed and does not vary with VIN. When operating in this
condition, the switching frequency will vary inversely with
VIN rather than approximating a fixed frequency.
VOUT Voltage Selection
The switcher output voltage is regulated by comparing VOUT
as seen through a resistor divider at the FB pin to the internal
750 mV reference voltage, see Fig. 3.
To FB pin
VOUT
fSW =
VOUT
tON x VIN
The SIC414 and SiC424 uses an external resistor to set the
ontime which indirectly sets the frequency. The on-time can
be programmed to provide operating frequency from
200 kHz to 1 MHz using a resistor between the tON pin and
ground. The resistor value is selected by the following
equation.
RtON =
V
1
- 400 Ω x IN
VOUT
25 pF x fsw
The maximum RtON value allowed is shown by the following
equation.
Rton_MAX =
VIN_MIN
15 µA
Immediately after the on-time, the DL (drive signal for the
low side FET) output drives high to turn on the low side
MOSFET. DL has a minimum high time of ~ 320 ns, after
which DL continues to stay high until one of the following
occurs:
S20-0483-Rev. D, 29-Jun-2020
R1
R2
Fig. 3 - Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
VOUT = 0.75 x (1 + R1/R2) + VRIPPLE/2
Enable and Power-Save Inputs
The EN / PSV and ENL inputs are used to enable or disable
the switching regulator and the LDO. When EN / PSV is low
(grounded), the switching regulator is off and in its lowest
power state. When off, the output of the switching regulator
soft-discharges the output into a 10 internal resistor via
the VOUT pin. When EN / PSV is allowed to float, the pin
voltage will float to 33 % of the voltage at V5V. The switching
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regulator turns on with power-save disabled and all
switching is in forced continuous mode. For V5V < 4.5 V, it
is recommended to force 33 % of the V5V voltage on the
EN / PSV pin to operate in forced continuous mode.
When EN / PSV is high (above 45 % of the voltage at V5V)
for SiC414, the switching regulator turns on with ultrasonic
power-save enabled. The SiC414 ultrasonic power-save
operation maintains a minimum switching frequency of
25 kHz, for applications with stringent audio requirements.
When EN / PSV is high (above 45 % of the voltage at V5V)
for SiC424, the switching regulator turns on with
power-save enabled. The SiC424 power-save operation is
designed to maximize efficiency at light loads with no
minimum frequency limits. This makes the SiC424 an
excellent choice for portable and battery-operated systems.
The ENL input is used to control the internal LDO. This input
provides a second function by acting as a VIN ULVO sensor
for the switching regulator. When ENL is low (grounded), the
LDO is off. When ENL is a logic high but below the VIN UVLO
threshold (2.6 V typical), then the LDO is on and the switcher
is off. When ENL is above the VIN UVLO threshold, the LDO
is enabled and the switcher is also enabled if the EN / PSV
pin is not grounded.
Ultrasonic Power-Save Operation (SiC414)
The SiC414 provides ultrasonic power-save operation at
light loads, with the minimum operating frequency fixed at
slightly under 25 kHz. This is accomplished by using an
internal timer that monitors the time between consecutive
high side gate pulses. If the time exceeds 40 μs, DL drives
high to turn the low side MOSFET on. This draws current
from VOUT through the inductor, forcing both VOUT and VFB
to fall. When VFB drops to the 750 mV threshold, the next DH
(the drive signal for the high side FET) on-time is triggered.
After the on-time is completed the high side MOSFET is
turned off and the low side MOSFET turns on. The low side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low side MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40 μs, the frequency will not fall far below
25 kHz. Fig. 5 shows ultrasonic power-save operation.
Forced Continuous Mode Operation
The SiC414 and SiC424 operates the switcher in Forced
Continuous Mode (FCM) by floating the EN / PSV pin (see
Fig. 4). In this mode of operation, the MOSFETs are turned
on alternately to each other with a short dead time between
them to avoid cross conduction. This feature results in
uniform frequency across the full load range with the
trade-off being poor efficiency at light loads due to the
high frequency switching of the MOSFETs.
For V5V < 4.5 V, it is recommended to force 33 % of the V5V
voltage on the EN / PSV pin to operate in forced continuous
mode.
After the 40 μs time - out, DL drives high if VFB has not reached the FB threshold
FB ripple
voltage (VFB)
FB threshold
(750 mV)
DC load current
Inductor
current
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
DH
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Fig. 5 - Ultrasonic Power-Save Operation
Power-Save Mode Operation (SiC424)
The SiC424 provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors the
inductor current via the voltage across the low side MOSFET
during the off-time. If the inductor current falls to zero for 8
consecutive switching cycles, the controller enters
power-save operation. It will turn off the low side MOSFET
on each subsequent cycle provided that the current crosses
zero. At this time both MOSFETs remain off until VFB drops
to the 750 mV threshold. Because the MOSFETs are off, the
load is supplied by the output capacitor. If the inductor
current does not reach zero on any switching cycle, the
controller immediately exits powersave and returns to
forced continuous mode. Fig. 6 shows power-save mode
operation at light loads.
Fig. 4 - Forced Continuous Mode Operation
S20-0483-Rev. D, 29-Jun-2020
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SmartDriveTM
Dead time varies
according to load
FB Ripple
Voltage
(VFB)
FB threshold
(750 mV)
Inductor
Current
Zero (0 A)
For each DH pulse the DH driver initially turns on the high
side MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low side diode. Once the diode is off and the
LX voltage has risen 0.5 V above PGND, the SmartDrive
circuit automatically drives the high side MOSFET on at a
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers for the power MOSFETs.
Current Limit Protection
DH On-time is triggered when
VFB reaches the FB Threshold
DH
DL
DL drives high when on-time is completed.
DL remains high until inductor current reaches zero.
Fig. 6 - Power-Save Mode Operation
Smart Power-Save Protection
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with
power-save mode enabled, this can force VOUT to slowly rise
and reach the over voltage threshold, resulting in a hard shut
down. Smart power-save prevents this condition.
When the FB voltage exceeds 10 % above nominal, the
device immediately disables power-save, and DL drives
high to turn on the low side MOSFET. This draws current
from VOUT through the inductor and causes VOUT to fall.
When VFB drops back to the 750 mV trip point, a normal tON
switching cycle begins.
This method prevents a hard OVP shutdown and also cycles
energy from VOUT back to VIN. It also minimizes operating
power by avoiding forced conduction mode operation.
Fig. 7 shows typical waveforms for the smart power-save
feature.
VOUT drifts up to due to leakage
current flowing into COUT
Smart power save
threshold (825 mV)
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
FB
threshold
DH and DL off
The device features programmable current limiting, which is
accomplished by using the RDS(ON) of the lower MOSFET for
current sensing. The current limit is set by RILIM resistor. The
RILIM resistor connects from the ILIM pin to the LXS pin
which is also the drain of the low side MOSFET. When the
low side MOSFET is on, an internal ~ 8 μA current flows from
the ILIM pin and through the RILIM resistor, creating a
voltage drop across the resistor. While the low side
MOSFET is on, the inductor current flows through it and
creates a voltage across the RDS(ON). The voltage across the
MOSFET is negative with respect to ground. If this MOSFET
voltage drop exceeds the voltage across RILIM, the voltage
at the ILIM pin will be negative and current limit will activate.
The current limit then keeps the low side MOSFET on and
will not allow another high side on-time, until the current in
the low side MOSFET reduces enough to bring the ILIM
voltage back up to zero. This method regulates the inductor
valley current at the level shown by ILIM in Fig. 8.
IPEAK
Inductor Current
On-time (TON)
ILOAD
ILIM
Time
Fig. 8 - Valley Current Limit
Setting the valley current limit to 6 A results in a 6 A peak
inductor current plus peak ripple current. In this situation,
the average (load) current through the inductor is 6 A plus
one-half the peak-to-peak ripple current.
The internal 8 μA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the RDS(ON). The RILIM value is calculated by the following
equation.
RILIM = 1250 x ILIM x [0.088 x (5 V - V5V) + 1]
High-side
drive (DH)
Single DH on-time pulse
after DL turn-off
Low-side
drive (DL)
DL turns on when smart
PSAVE threshold is reached
DL turns off FB
threshold is reached
Normal DL pulse after DH
on-time pulse
When selecting a value for RILIM do not exceed the absolute
maximum voltage value for the ILIM pin. Note that because
the low side MOSFET with low RDS(ON) is used for current
sensing, the PCB layout, solder connections, and PCB
connection to the LX node must be done carefully to obtain
good results. RILIM should be connected directly to LXS
(pin 24).
Fig. 7 - Smart Power-Save
S20-0483-Rev. D, 29-Jun-2020
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Soft-Start of PWM Regulator
LDO Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB
comparator. The voltage ramp is generated using an internal
charge pump which drives the reference from zero to
750 mV in ~ 1.8 mV increments, using an internal ~ 500 kHz
oscillator. When the ramp voltage reaches 750 mV, the ramp
is ignored and the FB comparator switches over to a fixed
750 mV threshold. During soft-start the output voltage
tracks the internal ramp, which limits the start-up inrush
current and provides a controlled soft-start profile for a wide
range of applications. Typical soft-start ramp time is 1.7 ms.
The device features an integrated LDO regulator with a fixed
output voltage of 5 V. There is also an enable pin (ENL) for
the LDO that provides independent control. The LDO
voltage can also be used to provide the bias voltage for the
switching regulator.
During soft-start the regulator turns off the low side
MOSFET on any cycle if the inductor current falls to zero.
This prevents negative inductor current, allowing the device
to start into a pre-biased output. This soft start operation is
implemented even if FCM is selected. FCM operation is
allowed only after PGOOD is high.
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage is
10 % below the nominal voltage, PGOOD is pulled low. It is
held low until the output voltage returns to the nominal
voltage. PGOOD is held low during start-up and will not be
allowed to transition high until soft-start is completed (when
VFB reaches 750 mV) and typically 4 ms has passed.
PGOOD will transition low if the VFB pin exceeds +20 % of
nominal, which is also the over voltage shutdown threshold
(900 mV). PGOOD also pulls low if the EN / PSV pin is low
when V5V is present.
A minimum capacitance of 1 μF referenced to AGND is
normally required at the output of the LDO for stability. If the
LDO is providing bias power to the device, then a minimum
0.1 μF capacitor referenced to AGND is required, along with
a minimum 1 μF capacitor referenced to PGND to filter the
gate drive pulses. Refer to the layout guide-lines section.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
2. VLDO output
3. VIN input voltage
When the ENL pin is high, the LDO will begin start-up, see
Fig. 9. During the initial phase, when the LDO output voltage
is near zero, the LDO initiates a current-limited start-up
(typically 85 mA) to charge the output capacitor. When VLDO
has reached 90 % of the final value, the LDO current limit is
increased to ~ 200 mA and the LDO output is quickly driven
to the nominal value by the internal LDO regulator.
VVLDO final
Voltage regulating with
~ 200 mA current limit
90 % of VVLDO final
Output Over Voltage Protection
Over Voltage Protection (OVP) becomes active as soon as
the device is enabled. The threshold is set at 750 mV +20 %
(900 mV). When VFB exceeds the OVP threshold, DL latches
high and the low side MOSFET is turned on. DL remains high
and the controller remains off, until the EN / PSV input is
toggled or V5V is cycled. There is a 5 μs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
Output Under Voltage Protection
When VFB falls to 75 % of its nominal voltage (falls to
562.5 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to turn off
the MOSFETs. The controller stays off until EN / PSV is
toggled or V5V is cycled.
V5V UVLO, and POR
Under Voltage Lock-Out (UVLO) circuitry inhibits switching
and tri-states the DH / DL drivers until V5V rises above
2.9 V. An internal Power-On Reset (POR) occurs when V5V
exceeds 2.9 V, which resets the fault latch and soft-start
counter to begin the soft-start cycle. The SiC414 and
SiC424 then begins a soft-start cycle. The PWM will shut off
if V5V falls below 2.7 V.
S20-0483-Rev. D, 29-Jun-2020
Constant current startup
Fig. 9 - LDO Start-Up
LDO Switch-over Function
The SiC414 and SiC424 includes a switch-over function for
the LDO. The switch-over function is designed to increase
efficiency by using the more efficient DC/DC converter to
power the LDO output, avoiding the less efficient LDO
regulator when possible. The switch-over function connects
the VLDO pin directly to the VOUT pin using an internal switch.
When the switch-over is complete the LDO is turned off,
which results in a power savings and maximizes efficiency.
If the LDO output is used to bias the SiC414 and SiC424,
then after switch-over the device is self-powered from the
switching regulator with the LDO turned off.
The switch-over logic waits for 32 switching cycles before it
starts the switch-over. There are two methods that
determine the switch-over of VLDO to VOUT.
In the first method, the LDO is already in regulation and the
DC/DC converter is later enabled. As soon as the PGOOD
output goes high, the 32 cycle counter is started. The
voltages at the VLDO and VOUT pins are then compared; if the
two voltages are within ± 300 mV (typically) of each other,
within 32 cycles, the VLDO pin connects to the VOUT pin using
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an internal switch, and the LDO is turned off.
In the second method, the DC/DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90 % of its final
value. At this time, the VLDO and VOUT pins are compared,
and if within ± 300 mV (typically) the switch-over occurs and
the LDO is turned off.
Note that it is possible to operate the switcher with the LDO
disabled, but the ENL pin must be below the logic low
threshold (0.4 V maximum). The table below summarizes the
function of the ENL and EN pins, with respect to the rising
edge of ENL.
EN
ENL
LDO
SWITCHER
Off
Switch-Over Limitations on VOUT and VLDO
Low
Low, < 0.4 V
Off
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are voltage
limitations on permissible combinations of these pins.
Consider the situation where VOUT is programmed to 4.7 V.
After start-up, the device would connect VOUT to VLDO and
disable the LDO, since the two voltages are within
the ± 300 mV switch-over window. To avoid unwanted
switch-over, the minimum difference between the voltages
for VOUT and VLDO should be ± 500 mV.
High
Low, < 0.4 V
Off
On
Low
High, < 2.6 V
On
Off
High
High, < 2.6 V
On
Off
Low
High, > 2.6 V
On
Off
High
High, > 2.6 V
On
On
Fig. 11 below shows the ENL voltage thresholds and their
effect on LDO and switcher operation.
Switch-Over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in Fig. 10.
Switchover
control
Switchover
MOSFET
VOUT
VLDO
Parastic diode
Parastic diode
V5V
Fig. 10 - Switch-Over MOSFET Parasitic Diodes
There are some important design rules that must be
followed to prevent forward bias of these diodes. The
following two conditions need to be satisfied in order for the
parasitic diodes to stay off.
• V5V VLDO
• V5V VOUT
If either VLDO or VOUT is higher than V5V, then the respective
diode will turn on and the SiC414 and SiC424 operating
current will flow through this diode. This has the potential of
damaging the device.
ENL Pin and VIN UVLO
The ENL pin also acts as the switcher under voltage lockout
for the VIN supply. The VIN UVLO voltage is programmable
via a resistor divider at the VIN, ENL, and AGND pins. ENL
is the enable / disable signal for the LDO. In order to
implement the VIN UVLO there is also a timing requirement
that needs to be satisfied. If the ENL pin transitions low
within 2 switching cycles and is < 1 V, then the LDO will turn
off, but the switcher remains on. If ENL goes below the VIN
UVLO threshold and stays above 1 V, then the switcher will
turn off but the LDO remains on. The VIN UVLO function has
a typical threshold of 2.6 V on the VIN rising edge.The falling
edge threshold is 2.4 V.
S20-0483-Rev. D, 29-Jun-2020
Fig. 11 - ENL Thresholds
ENL Logic Control of PWM Operation
When the ENL input is driven above 2.6 V, it is impossible to
determine if the LDO output is going to be used to power the
device or not. In self-powered operation where the LDO will
power the device, it is necessary during the LDO start-up to
hold the PWM switching off until the LDO has reached 90 %
of the final value. This prevents overloading the
current-limited LDO output during the LDO start-up.
However, if the switcher was previously operating (with
EN / PSV high but ENL at ground, and V5V supplied
externally), then it is undesirable to shut down the switcher.
To prevent this, when the ENL input is above 2.6 V (above
the VIN UVLO threshold), the internal logic checks the PGOOD
signal. If PGOOD is high, then the switcher is already running
and the LDO will run through the start-up cycle without
affecting the switcher. If PGOOD is low, then the LDO will not
allow any PWM switching until the LDO output has reached
90 % of its final value.
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Using the On-chip LDO to Bias the SIC414 / SIC424
The following steps must be followed when using the onchip
LDO to bias the device.
• Connect V5V to VLDO before enabling the LDO.
• Any external load on VLDO should not exceed 40 mA until
the LDO voltage has reached 90 % of final value.
RtON =
To select RtON, use the maximum value for VIN, and for tON
use the value associated with maximum VIN.
tON =
• Do not connect the EN pin directly to the V5V or any other
supply voltage if VOUT is greater than or equal to 4.5 V.
Many applications connect the EN pin to V5V and control
the on/off of the LDO and PWM simultaneously with the ENL
pin. This allows one signal to control both the bias and
power output of the SiC414 and SiC424. When VOUT > 4.5 V
this configuration can cause problems due to the
parasitic diodes in the LDO switchover circuitry. After the
VOUT > 4.5 V PWM output is up and running the switchover
diodes can hold up V5V > UVLO even if the ENL pin is
grounded, turning off the LDO. Operating in this way can
potentially damage the part.
Design Procedure
When designing a switch mode power supply, the input
voltage range, load current, switching frequency, and
inductor ripple current must be specified.
The maximum input voltage (VIN_MAX.) is the highest
specified input voltage. The minimum input voltage (VIN_MIN.)
is determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters define the design:
• Nominal output voltage (VOUT)
• Static or DC output tolerance
• Transient response
• Maximum load current (IOUT)
There are two values of load current to evaluate - continuous
load current and peak load current. Continuous load current
relates to thermal stresses which drive the selection of the
inductor and input capacitors. Peak load current determines
instantaneous
component
stresses
and
filtering
requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design:
•
•
•
•
VIN = 12 V ± 10 %
VOUT = 1.5 V ± 4 %
fSW = 250 kHz
Load = 6 A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency.
The desired switching frequency is 250 kHz which results
from using component selected for optimum size and cost.
V
1
- 400 Ω x IN
VOUT
25 pF x fsw
VOUT
VINMAX. x fSW
tON = 303 ns at 13.2 VIN, 1 VOUT, 250 kHz
Substituting for RtON results in the following solution
RtON = 130.9 k, use RtON = 130 k.
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values result in smaller size
but create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current /
voltage and for a given DC resistance are more efficient.
However, larger inductance translates directly into larger
packages and higher cost. Cost, size, output ripple, and
efficiency are all used in the selection process.
The ripple current will also set the boundary for power-save
operation. The switching will typically enter power-save
mode when the load current decreases to 1/2 of the ripple
current. For example, if ripple current is 4 A then Power-save
operation will typically start for loads less than 2 A. If ripple
current is set at 40 % of maximum load current, then
power-save will start for loads less than 20 % of maximum
current.
The inductor value is typically selected to provide a ripple
current that is between 25 % to 50 % of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
L=
(VIN - VOUT) x tON
IRIPPLE
Example
In this example, the inductor ripple current is set equal to
50 % of the maximum load current. Therefore ripple current
will be 50 % x 6 A or 3 A. To find the minimum inductance
needed, use the VIN and tON values that correspond to
VINMAX.
L=
(13.2 V - 1 V) x 318 ns
= 1.26 µH
3A
A slightly larger value of 1.5 μH is selected. This will
decrease the maximum IRIPPLE to 2.53 A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current. The ripple current
under minimum VIN conditions is also checked using the
following equations.
A resistor (RtON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63388
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SiC414, SiC424
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25 pF x RtON x VOUT
+ 10 ns = 311 ns
tON_VINMIN =
VINMIN
IRIPPLE =
(VIN - VOUT) x tON
L
(10.8 - 1 V) x 311 ns
1.5µH
IRIPPLE_VINMIN =
= 2.03 A
Peak inductor current is shown by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 10 + 1/2 x 2.53 = 7.26 A
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is for the output voltage regulation to be
± 4 % under static conditions. The internal 750 mV reference
tolerance is 1 %. Assuming a 1 % tolerance from the FB
resistor divider, this allows 2 % tolerance due to VOUT ripple.
Since this 2 % error comes from 1/2 of the ripple voltage, the
allowable ripple is 4 %, or 40 mV for a 1 V output.
The maximum ripple current of 2.53 A creates a ripple
voltage across the ESR. The maximum ESR value allowed is
shown by the following equations.
ESRMAX =
VRIPPLE
IRIPPLEMAX
=
40 mV
2.53 A
ESRMAX = 15.8 mΩ
The output capacitance is chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current
is at the peak, determines the required capacitance. If the
load release is instantaneous (load changes from maximum
to zero in < 1 μs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
1
xI
)2
2 RIPPLEMAX
(VPEAK)2 - (VOUT)2
L (IOUT +
COUT_MIN =
the falling load current. This will reduce the excess inductive
energy that must be absorbed by the output capacitor,
therefore a smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dILOAD/dt:
Assuming a peak voltage VPEAK of 1.150 (100 mV rise upon
load release), and a 6 A load release, the required
capacitance is shown by the next equation.
1
x 2.53)2
2
(1.05)2 - (1 V)2
1.5 µH (6 A +
COUT_MIN =
COUT_MIN = 772 µF
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750 mV reference, the DL
output is high and the low side MOSFET is on. During this
time, the voltage across the inductor is approximately VOUT. This causes a down-slope or falling di/dt in the
inductor. If the load dI/dt is not much faster than the - di/dt
in the inductor, then the inductor current will tend to track
S20-0483-Rev. D, 29-Jun-2020
Rate of change of load current = dILOAD/dt
IMAX = maximum load release = 6 A
COUT = ILPK x
I
I
L x LPK - MAX x dt
VOUT dlLOAD
2 (VPK - VOUT)
Example
Load
dlLOAD 1.25 A
=
1 µs
dt
This causes the output current to move from 6 A to 0 A in
4.8 μs, giving the minimum output capacitance requirement
shown in the following equation.
7.26 6 A
x 1 µs
1 V 1.25 A
2 (1.05 V - 1 V)
1.5 µH x
COUT = 7.26 x
COUT = 443 µF
Note that COUT is much smaller in this example, 443 μF
compared to 772 μF based on a worst-case load release. To
meet the two design criteria of minimum 443 μF and
maximum 15 m ESR, select two capacitors rated at 220 μF
and 15 m ESR or less.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to filter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
minimum off-time has expired. In extreme cases the noise
can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation.
This form of instability can usually be avoided by providing
the FB pin with a smooth, clean ripple signal that is at least
10 mVp-p, which may dictate the need to increase the ESR
of the output capacitors. It is also imperative to provide a
proper PCB layout as discussed in the Layout Guidelines
section.
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in Fig. 12. This capacitor should be left unpopulated
unless it can be confirmed that double-pulsing exists.
Adding the CTOP capacitor will couple more ripple into FB to
help eliminate the problem. An optional connection on the
PCB should be available for this capacitor.
Document Number: 63388
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SiC414, SiC424
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Vishay Siliconix
CTOP
VOUT
To FB pin
R1
R2
Fig. 12 - Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
One simple way to solve this problem is to add trace
resistance in the high current output path. A side effect of
adding trace resistance is a decrease in load regulation.
Fig. 13 - Virtual ESR Ramp Circuit
Dropout Performance
The output voltage adjustment range for continuous
conduction operation is limited by the fixed 250 ns (typical)
minimum off-time of the one-shot. When working with low
input voltages, the duty-factor limit must be calculated using
worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
DUTY =
ESR Requirements
tON(MIN)
tON(MIN) x tOFF(MAX)
A minimum ESR is required for two reasons. One reason
is to generate enough output ripple voltage to provide
10 mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications, the total
output ripple voltage is dominated by the output capacitors,
typically SP or POSCAP devices. For stability the ESR zero
of the output capacitor should be lower than approximately
one-third the switching frequency. The formula for minimum
ESR is shown by the following equation.
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line and
load, and the external resistor tolerance. The error
comparator off set is trimmed so that under static conditions
it trips when the feedback pin is 750 mV, 1 %.
ESRMIN =
3
2 x π x COUT x fSW
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
criteria. In these applications it is necessary to add a small
virtual ESR network composed of two capacitors and one
resistor, as shown in Fig. 12. This network creates a ramp
voltage across CL, analogous to the ramp voltage generated
across the ESR of a standard capacitor. This ramp is then
capacitive coupled into the FB pin via capacitor CC.
System DC Accuracy (VOUT Controller)
The on-time pulse from the SiC414 and SiC424 in the design
example is calculated to give a pseudo-fixed frequency of
250 kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple voltage.
Because constant on-time converters regulate to the valley
of the output ripple, 1/2 of the output ripple appears as a DC
regulation error. For example, if the output ripple is 50 mV
with VIN = 6 V, then the measured DC output will be 25 mV
above the comparator trip point. If the ripple increases to
80 mV with VIN = 25 V, then the measured DC output will be
40 mV above the comparator trip. The best way to minimize
this effect is to minimize the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capacitor.
This trace resistance should be optimized so that at full load
the output droops to near the lower regulation limit. Passive
droop minimizes the required output capacitance because
the voltage excursions due to load steps are reduced as
seen at the load.
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63388
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SiC414, SiC424
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Vishay Siliconix
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is that
frequency tends to falls slightly with increasing input voltage
inductor. An adaptive on-time converter must also
compensate for the same losses by increasing the effective
duty cycle (more time is spent drawing energy from VIN as
losses increase). The on-time is essentially constant for a
given VOUT / VIN combination, to offset the losses the
off-time will tend to reduce slightly as load increases. The
net effect is that switching frequency increases slightly with
increasing load.
The use of 1 % feedback resistors may result in up to an
additional 1 % error. If tighter DC accuracy is required,
resistors with lower tolerances should be used.
The output inductor value may change with current. This will
change the output ripple and therefore will have a minor
effect on the DC output voltage. The output ESR also affects
the output ripple and thus has a minor effect on the DC
output voltage.
Switching Frequency Variations
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fixed
propagation delays in the on-time one-shot, as well as
BILL OF MATERIALS
QTY.
REF.
DESIGNATOR
DESCRIPTION
1
U1
SiC424 COT Buck
Converter
4
C16, C18, C17,
C23
220 μF, 10 V D
220 μF
4
C15, C20, C21,
C22
10 μF, 16 V, X7R.B,
1206
VALUE
VOLTAGE FOOTPRINT
PART NUMBER
MANUFACTURER
MLPQ-28
4 x 4 mm
SiC424
Vishay
10 V
SM593D
593D227X0010E2TE3
Vishay
10 μF
16 V
SM1206
GRM31CR71C106KAC7L
Murata
1 μH
-
IHLP2525
IHLP2525EZER1R0M01
Vishay
-
SO-8
Si4812BDY
Vishay
1
L1
1 μH
1
Q1
Si4812BDY-E3
5
C1, C2, C3, C4,
C29
CAP. 22 μF, 16 V,
1210
22 μF
16 V
SM1210
GRM32ER71C226ME18L
Murata
3
C8, C9, C10
CAP. 10 μF, 25 V,
1210
10 μF
25 V
SM1210
TMK325B7106MM-T
Taiyo Yuden
1
C26
4.7 μF, 10 V, 0805
4.7 μF
10 V
SM0805
LMK212B7475KG-T
Taiyo Yuden
C12
CAP. Radial 150 μF,
35 V
150 μF
35 V
Radial
EU-FM1V151
Panasonic
1
1
R4
1 , 2512
1
200 V
SM2512
CRCW25121R00FKEG
Vishay
2
R7, R11
Res. 0
0
50 V
SM0603
CRCW0603 0000ZOEA
Vishay
1
R39
0R, 50 V, 0402
0
50 V
SM0402
CRCW04020000ZOED
Vishay
1
R3
Res. 1K, 50 V, 0402
1K
50 V
SM0402
CRCW04021K00FKED
Vishay
2
R5, R6
Res. 100K, 0603
100K
50 V
SM0603
CRCW0603 100K FKEA
Vishay
3
R8, R10, R15
Res. 10K, 50 V, 0603
10K
50 V
SM0603
CRCW060310KFKED
Vishay
1
C6
CAP. CER 1 μF, 35 V,
X7R 0805
1 μF
35 V
SM0805
GMK212B7105KG-T
Murata
1
R23
Res. 16.5 k, 1/10 W,
1%, 0603 SMD
16.5K
50 V
SM0603
CRCW060316K5FKEA
Vishay
1
R13
Res. 1K, 50 V, 0402
1K
50 V
SM0402
CRCW04021K00FKED
Vishay
1
C30
CAP. 180 pF, 0402
180 pF
50 V
SM0402
VJ0402A181JXACW1BC
Vishay
1
R30
Res. 78.7 k, 1/10 W,
1 %, 0603 SMD
78.7k
50 V
SM0603
CRCW060378K7FKEA
Vishay
4
C7, C11, C14,
C28
CAP. 0.1 μF, 50 V,
0603
0.1 μF
50 V
SM0603
VJ0603Y104KXACW1BC
Vishay
1
C5
CAP. 0.1 μF, 10 V,
0402
0.1 μF
10 V
SM0402
VJ0402Y104MXQCW1BC
Vishay
4
B1, B2, B3, B4
Solder Banana
575-6
Keystone
1
C13
CAP. 0.01 μF, 50 V,
0402
0.01 μF
50 V
SM0402
VJ0402Y103KXACW1BC
Vishay
12
P1, P2, P3, P4,
P5, P6, P7, P8,
P9, P10, P11, P12
Probe Hook
-
-
Terminal
0
Keystone
4
M1, M2, M3, M4
Nylon on Stand off
-
-
-
8834
Keystone
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63388
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PCB LAYOUT OF THE EVALUATION BOARD
Fig. 14 - Top Layer
Fig. 16 - Mid Layer1
Fig. 15 - Mid Layer2
Fig. 17 - Bottom Layer
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63388
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SiC414, SiC424
www.vishay.com
Vishay Siliconix
PRODUCT SUMMARY
Part number
Description
SiC414
SiC424
6 A, 3 V to 28 V, integrated buck regulator with 6 A, 3 V to 28 V, integrated buck regulator with
5 VLDO, ultrasonic mode
5 VLDO, powersave mode
Input voltage min. (V)
3
3
Input voltage max. (V)
28
28
Output voltage min. (V)
0.75
0.75
Output voltage max. (V)
5.5
5.5
Continuous current (A)
6
6
Switch frequency min. (kHz)
200
200
Switch frequency max. (kHz)
1000
1000
Pre-bias operation (yes / no)
Yes
Yes
Internal bias reg. (yes / no)
Yes
Yes
Not required
Not required
Compensation
Enable (yes / no)
Yes
Yes
PGOOD (yes / no)
Yes
Yes
Overcurrent protection
Protection
Light load mode
Peak efficiency (%)
Package type
Package size (W, L, H) (mm)
Programmable
Programmable
OVP, OCP, UVP/SCP, OTP, UVLO
OVP, OCP, UVP/SCP, OTP, UVLO
Ultrasonic
Powersave
95
95
PowerPAK MLP28-44GW
PowerPAK MLP28-44GW
4.0 x 4.0 x 0.75
4.0 x 4.0 x 0.75
Status code
2
2
Product type
microBUCK (step down regulator)
microBUCK (step down regulator)
Applications
Computing, consumer, networking, industrial, Computing, consumer, networking, industrial,
healthcare
healthcare
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63388.
S20-0483-Rev. D, 29-Jun-2020
Document Number: 63388
20
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
PowerPAK® MLP44-28L CASE OUTLINE
5 6
PIN 1 Dot by
Marking
2x
2x
K1
0.10 C A
D
A
D2-3
PIN#1 Identification
R0.20
D2-1
0.10 C B
1
E
2
e
28L T/SLP
(4.0 mm x 4.0 mm)
3 E2-2
(Ne-1)X e
Ref.
K2
E2-1
0.4000
b
CA B
E2-3
L
D2-2
0.10
B
Top View
Notes:
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and
Ne is the number of terminals in Y-direction.
A
4. Dimensions b applies to plated terminal and is measured
between 0.15 mm and 0.30 mm from terminal tip.
0.08 C
5. The pin #1 identifier must be existed on the top surface of the
package by using identification mark or other feature of package body. 0.000-0.0500
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
4
(Nd-1)X e
Ref.
Bottom View
C
0.2030 Ref.
Side View
MILLIMETERS
DIM.
MIN.
0.70
A (8)
A1
0.00
A2
0.175
b (4)
D
e
E
L
0.30
N (3)
Nd (3)
Ne (3)
D2-1
0.908
D2-2
0.908
D2-3
0.912
E2-1
2.43
E2-2
1.30
E2-3
0.58
K1
K2
ECN: T10-0056-Rev. A, 22-Feb-10
DWG: 5996
Document Number: 65739
Revision: 22-Feb-10
INCHES
NOM.
MAX.
MIN.
NOM.
MAX.
0.75
0.20 REF
0.225
4.00 BSC
0.45 BSC
4.00 BSC
0.40
28
7
7
1.058
1.058
1.062
2.58
1.45
0.73
0.46 BSC
0.40 BSC
0.80
0.05
0.027
0.000
0.031
0.002
0.275
0.007
0.50
0.012
1.158
1.158
1.162
2.68
1.55
0.83
0.036
0.036
0.036
0.096
0.051
0.023
0.029
0.008 REF
0.009
0.157 BSC
0.018 BSC
0.157 BSC
0.016
28
7
7
0.042
0.042
0.042
0.102
0.057
0.029
0.018 BSC
0.016 BSC
0.011
0.020
0.046
0.046
0.046
0.105
0.061
0.033
www.vishay.com
1
PAD Pattern
Vishay Siliconix
PowerPAK® MLP44-28L Land Pattern
Recommended Land Pattern
1.29
0.30
1.06
1
1.29
1.45
2
4.70
3.20
0.75
0.73
2.58
3.95
3
1.06
0.45
2.58
Recommended Land Pattern vs. Case Outline
0.06
0.75
0.06
0.400
0.30
0.06
1
2
3
Document Number: 70567
Revision: 17-May-10
www.vishay.com
1
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2022
1
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