End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
150-mA Low Noise, Low Dropout Regulator
DESCRIPTION
FEATURES
The SiP21106 BiCMOS 150 mA low noise LDO voltage
regulators are the perfect choice for low battery operated low
powered applications. An ultra low ground current and low
dropout voltage of 135 mV at 150 mA load helps to extend
battery life for portable electronics. Systems requiring a quiet
voltage source, such as RF applications, will benefit from the
SiP21106 low output noise.
The SiP21107 do not require a noise bypass capacitor and
provides an error flag pin (POK or Power OK). POK output
requires an external pull-up resistor and goes low when the
supply has not come up to voltage.
The SiP21108 output is adjusted with an external resistor
network.
The SiP21106, SiP21107, SiP21108 regulators allow stable
operation with very small ceramic output capacitors,
reducing board space and component cost. They are
designed to maintain regulation while delivering 330 mA
peak current upon turn-on. During start-up, an active
pull-down circuit improves the output transient response and
regulation. In shutdown mode, the output automatically
discharges to ground through a 100 NMOS.
The SiP21106, SiP21107, SiP21108 are available in
TSOT23-5L a super thin lead (Pb)-free TSC75-6L and
SC70-5L packages for operation over the industrial operation
range (- 40 °C to 85 °C).
• SC70-5L (2.1 mm x 2.1 mm x 0.95 mm)
• TSOT23-5L (3.05 mm x 2.85 mm x 1.0 mm)
• TSC75-6L package (1.6 mm x 1.6 mm
RoHS
COMPLIANT
x 0.55 mm), TSOT23-5L and SC70-5L
Package Options
• 1.0 % output voltage accuracy at 25 °C
• Low dropout voltage: 135 mV at 150 mA
• SiP21106 low noise: 60 µV(rms) (10 Hz to 100 kHz
bandwidth) with 10 nF over full load range
• 35 µA (typical) ground current at 1 mA load
• 1 µA maximum shutdown current at 85 °C
• Output auto discharge at shutdown mode
• Built-in short circuit (330 mA typical) and thermal
protection (160 °C typical)
• SiP21108 adjustable output voltage
• SiP21107 POK Error Flag
• - 40 °C to + 125 °C junction temperature range for
operation
• Uses low ESR ceramic capacitors
• Fixed voltage output 1.2 V to 5 V in 50 mV steps
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
•
•
•
•
•
•
Cellular phones, wireless handsets
PDAs
MP3 players
Digital cameras
Pagers
Wireless modem
• Noise-sensitive electronic systems
TYPICAL APPLICATION CIRCUIT
VIN
1
VIN
2
GND
VOUT
5
VOUT
EN
C OUT = 1 µF
C IN = 1 µF
C Bypass = 10 nF
GND
SiP21106
EN
BP
EN
3
EN
SiP21106
BP
4
VIN
C Bypass = 10 nF
TSOT23-5L/SC70-5LPackage
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
NC
VIN
VOUT
C IN = 1 µF
VOUT
COUT = 1 µF
TSC75-6L Package
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End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL APPLICATION CIRCUIT
1
VOUT
VIN
5
EN
VOUT
POK
EN
POK
COUT = 1 µF
CIN = 1 µF
2
GND
3
EN
GND
SiP21107
NC
SiP21107
POK
4
VIN
POK
VOUT
VIN
VOUT
CIN = 1 µF
C OUT =1 µF
TSOT23-5L/SC70-5LPackage
VIN
1
VIN
2
GND
3
EN
VOUT
5
TSC75L-6 Package
VOUT
EN
EN
Adj
GND
NC
C IN = 1 µF
COUT = 1 µF
SiP21108
SiP21108
EN
Adj
VIN
4
VOUT
VIN
CIN = 1 µF
VOUT
C OUT = 1 µF
TSC75-6L Package
TSOT23-5L/SC70-5L Package
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Input Voltage, VIN to GND
- 0.3 to 6.5
VEN (See Detailed Description)
- 0.3 to 6.5
Unit
V
Output Current (IOUT)
Short Circuit Protected
Output Voltage (VOUT)
- 0.3 to VIN + 0.3
Package Power Dissipation (PD)a
b
Package Thermal Resistance (JA)
Maximum Junction Temperature, TJ(max)
Storage Temperature, TSTG
Lead Temperature, TL
c
V
TSC75-6L
TSOT23-5L
SC70-5L
420
305
187
mW
180
294
°C/W
131
125
°C
- 65 to 150
260
Notes:
a. Derate 7.6 mW/°C for TSC75-6L package, 5.5 mW/°C for TSOT23-5L and 3.4 mW/°C for SC70-5L package above TA = 70 °C.
b. Device mounted with all leads soldered or welded to multilayer 1S2P PC board.
c. Soldering for 5 s.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
Input Voltage, VIN
Operating Ambient Temperature TA
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2
Limit
Unit
2.2 to 6
V
- 40 to 85
°C
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
SPECIFICATIONS
Parameter
Symbol
Input Voltage Range
Test Conditions Unless Specified
VIN = VOUT(nom) + 1.0 V = VEN
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full
VIN
IOUT = 1 mA
Output Voltage Accuracy
VOUT
SiP21106/7 (1.2 V) IOUT = 1 mA
Feedback Voltage
(SiP21108 Version only)
VAdj
Line Regulation
LNR
Load Regulation
LDR
VOUT 2.6 V,
IOUT: 1 mA to 150 mA
VOUT< 2.6 V,
IOUT: 1 mA to 150 mA
Output Noise
Voltagef
(RMS)
Output Voltage Turn-On Time
eN
ton
Auto Discharge Resistance
RDIS
VDO
EN Pin Input Current
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
2.5
- 1.5
1.5
Full
-4
Full
1.170
Full
- 0.2
0.006
0.2
Room
0.003
0.006
Room
0.005
0.009
Room
35
75
39
75
%/V
85
µA
85
350
f = 1 kHz
Room
75
56
1
µA
µV
EN to VOUT delay; IOUT = 1 mA
70
f = 10 kHz
Room
f = 100 kHz
Room
40
f = 1 kHz
Room
72
f = 10 kHz
Room
53
f = 100 kHz
Room
µs
dB
38
VOUT = 0 V
Room
EN = 0 V, VOUT = 1 V
Room
100
For VOUT < 2.2 V, EN = 0 V, VOUT = 1 V
Room
120
170
330
Room
45
Full
55
600
90
Full
106
Room
135
250
Full
160
300
Room
45
Full
55
Room
90
Full
106
Room
135
180
Full
160
220
High = Regulator On (Rising)
Full
VENL
Low = Regulator Off (Falling)
Full
Room
1.2
0.4
0.009
mA
Room
VENH
IEN
V
%/mA
Room
IOUT = 100 mA
1.212
1.230
SiP21107/8
VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz,
1 mA < IOUT < 150 mA
IOUT = 100 mA
%
4
1.2
60
IOUT = 150 mA
EN Pin Input Voltage
- 2.5
Room
IOUT = 50 mA
VDO
Full
Room
SiP21106
VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz,
1 mA < IOUT < 150 mA, CBP = 0.01 µF
IOUT = 150 mA
Dropout Voltage
(VOUT(nom) 2.6 V)
1.0
Full
IOUT = 50 mA
Dropout Voltaged
(2.2 V VOUT(nom) < 2.6 V)
- 1.0
0.02
PSRR
IO_LIM
V
Room
Full
SiP21107/8
SiP21106, CBP = 0 µF
IOUT = 10 mA
Output Current Limit
Typ.c
VEN = 0 V
SiP21106, CBP = 0.01 µF
IOUT = 10 mA
Ripple Rejection
6
Room
IOUT = 150 mA
ICC(off)
Unit
2.2
Full
IGND
Shutdown Supply Current
Max.b
Full
Room 1.188
IOUT = 1 mA
Ground Pin Currente
Temp.a Min.b
mV
V
µA
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End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
SPECIFICATIONS
Parameter
Test Conditions Unless Specified
VIN = VOUT(nom) + 1.0 V
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full
Symbol
Temp.a Min.b Typ.c Max.b
Thermal Shutdown Junction Temperature
TJ(S/D)
Room
160
Thermal Hysteresis
THYST
Room
20
Unit
°C
Error Flag Section (SiP21107 Version only)
POK(OFF) Leakage
POK(ON) Voltage
g
POK Threshold
IOFF
RPU to VOUT or VIN
Full
1
µA
VPOKL
EN = 0 V, IPOK = 0.5 mA
Full
0.4
V
VOUT rising, POK goes high
VOUT(nom) 2.2 V, IOUT = 1 mA
VPOKLH
POK Hysteresis
POK Voltage Delay Time
VOUT rising, POK goes high
VOUT(nom)< 2.2 V, IOUT = 1 mA
VHYST
VIN falling, IOUT = 1 mA, POK goes low
TP_Delay
VOUT to POK delay, IOUT = 1 mA
90
93
Full
91
Room
96
%
1.5
40
µs
Notes:
a. Room = 25 °C, Full = - 40 to 85 °C. Derate 7.6 mW/°C for TSC75 and 5.5 mW/°C for SOT23 above TA = 70 °C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Dropout voltage is defined as the input-to-output differential voltage at which the output voltage drops 2 % below its nominal
value with constant load. For outputs = 2.2 V, dropout voltage is not applicable due to 2.2 V minimum input voltage requirement.
e. Ground current is specified for normal operation as well as “drop-out” operation.
f. Output noise is proportional to output voltage. Use formula eN = 60 µV(rms)*VOUT/2.8 V.
g. POK threshold percentage is calculated by VIN/VOUT x 100 %. The POK is measured with a differential voltage across VIN and VOUT until POK
turn on (low threshold) or off (high threshold). For VOUT less than 2.2 V, POK is guaranteed functionality only.
TIMING WAVEFORMS
VIN
VEN
tr
0V
1 µs
tON
VNOM
0.95 VNOM
VOUT
Figure 1.
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
PIN CONFIGURATION
EN
BP/Adj/POK
BP/Adj/POK
GND
6
1
NC
5
2
GND
VOUT
4
3
VIN
NC
VIN
VOUT
TOP VIEW
VIN
1
GND
2
EN
3
EN
TSC75-6L Package (1.6 mm x 1.6 mm x 0.55 mm)
5
4
VOUT
VOUT
BP/Adj/POK
BP/Adj/POK
BOTTOM VIEW
5
4
1
VIN
2
GND
3
EN
BOTTOM VIEW
TOP VIEW
TSOT23-5L/SC70-5LPackage
Figure 2.
PIN DESCRIPTION
Pin Number
TSC75-6L
Pin Number
TSOT23-5L/
SC70-5L
Name
1
3
EN
2
2
GND
3
1
VIN
4
5
VOUT
5
-
NC
6
4
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
BP/Adj/POK
Function
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to
VIN if unused. Do not leave floating.
Ground pin. For better thermal capability, directly connected to large ground plane.
Input supply pin. Bypass this pin with a 1 µF ceramic or tantalum capacitor to ground.
Output voltage. Connect COUT between this pin and ground.
No Connection.
- BP (SiP21106): Noise bypass pin. For low noise applications, a 10 nF ceramic capacitor
should be connected from this pin to ground.
- Adj (SiP21108): Adjust input pin. Connect feedback resistors to program the output
voltage for trim value of 1.2005 V.
- POK (SiP21107): Power OK (error flag) pin. Open-drain output, which requires
connecting a pull-up resistor to VIN or VOUT. POK pin is actively high to indicate an output
normal operation condition on regulator and goes low to indicate under-voltage fault
condition.
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End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
ORDERING INFORMATION
Part Number
Marking
Voltage
SiP21108DVP-T1-E3
AA
Adjustable
SiP21106DVP-12-E3
BA
1.2
SiP21106DVP-18-E3
BG
1.8
SiP21106DVP-25-E3
BP
2.5
SiP21106DVP-26-E3
BR
2.6
SiP21106DVP-28-E3
BT
2.8
SiP21106DVP-285-E3
CT
2.85
SiP21106DVP-30-E3
BV
3
SiP21106DVP-33-E3
BY
3.3
SiP21106DVP-46-E3
CM
4.6
SiP21106DVP-475-E3
CU
4.75
SiP21107DVP-12-E3
DA
1.2
SiP21107DVP-18-E3
DG
1.8
SiP21107DVP-25-E3
DP
2.5
SiP21107DVP-26-E3
DR
2.6
SiP21107DVP-28-E3
DT
2.8
SiP21107DVP-30-E3
DV
3
SiP21107DVP-33-E3
DY
3.3
SiP21107DVP-46-E3
EM
4.6
SiP21107DVP-285-E3
ET
2.85
SiP21108DT-T1-E3
N9
Adjustable
SiP21106DT-12-E3
NP
1.2
SiP21106DT-18-E3
N1
1.8
SiP21106DT-25-E3
NA
2.5
SiP21106DT-26-E3
NC
2.6
SiP21106DT-28-E3
N2
2.8
SiP21106DT-285-E3
NE
2.85
SiP21106DT-30-E3
NG
3
SiP21106DT-33-E3
N3
3.3
SiP21106DT-45-E3
NM
4.5
SiP21106DT-46-E3
N4
4.6
SiP21106DT-475-E3
NJ
4.75
SiP21107DT-12-E3
NQ
1.2
SiP21107DT-18-E3
N5
1.8
SiP21107DT-25-E3
NB
2.5
SiP21107DT-26-E3
ND
2.6
SiP21107DT-28-E3
N6
2.8
SiP21107DT-285-E3
NF
2.85
SiP21107DT-30-E3
NH
3
SiP21107DT-33-E3
N7
3.3
SiP21107DT-46-E3
N8
4.6
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Temperature Range
Package
- 40 °C to 85 °C
TSC75-6L
- 40 °C to 85 °C
TSOT23-5L
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
ORDERING INFORMATION
SiP21108DR-T1-E3
N9
Adjustable
SiP21106DR-12-E3
NP
1.2
SiP21106DR-18-E3
N1
1.8
SiP21106DR-25-E3
NA
2.5
SiP21106DR-26-E3
NC
2.6
SiP21106DR-28-E3
N2
2.8
SiP21106DR-285-E3
NE
2.85
SiP21106DR-30-E3
NG
3
SiP21106DR-33-E3
N3
3.3
SiP21106DR-46-E3
N4
4.6
SiP21106DR-475-E3
NJ
4.75
SiP21107DR-12-E3
NQ
1.2
SiP21107DR-18-E3
N5
1.8
SiP21107DR-25-E3
NB
2.5
SiP21107DR-26-E3
ND
2.6
SiP21107DR-28-E3
N6
2.8
SiP21107DR-285-E3
NF
2.85
SiP21107DR-30-E3
NH
3
SiP21107DR-33-E3
N7
3.3
SiP21107DR-46-E3
N8
4.6
- 40 °C to 85 °C
SC70-5L
Note:
Other fixed output voltage options are available. Please contact your Vishay sales representative or distributor for details.
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL CHARACTERISTICS
3.0
1.00
2.5
0.50
Deviation (%)
VOUT (V)
2.0
I OUT = 0 mA
1.5
I OUT = 150 mA
1.0
I OUT = 1 mA
0.00
- 0.50
- 1.00
0.5
SiP21106: 2.8 V
SiP21106: 2.8 V
0.0
0
1
2
3
4
5
- 1.50
- 40
6
- 15
VIN (V)
10
35
60
85
Temperature (°C)
Output Voltage vs. Input Voltage
Output Voltage Accuracy vs. Temperature
180
180
SiP21106: 2.8 V
160
160
TA = + 85 °C
140
IOUT = 150 mA
140
TA = + 25 °C
V DO (mV)
V DO (mV)
120
100
80
60
120
100
IOUT = 100 mA
40
TA = - 40 °C
80
20
SiP21106: 2.8 V
0
0
25
50
75
100
125
150
60
2.0
2.5
3.0
3.5
IOUT (mA)
4.5
5.0
5.5
6.0
Dropout Voltage vs. Input Voltage
Dropout Voltage vs. Load Current
180
41
160
I OUT = 150 mA
40
I OUT = 150 mA
140
V DO (mV)
4.0
VIN (V)
39
120
38
I OUT = 100 mA
100
37
80
I OUT = 1 mA
36
60
I OUT = 50 mA
35
40
SiP21106: 2.8 V
SiP21106: 2.8 V
34
20
- 40
- 15
10
35
60
Temperature (°C)
Dropout Voltage vs. Temperature
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8
85
- 40
- 15
10
35
60
85
Temperature (°C)
Ground Current vs. Temperature
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL CHARACTERISTICS
50
50
VIN = 5.5 V
IOUT = 150 mA
40
45
I GND (µA)
I GND (µA)
VIN = 3.8 V
40
35
IOUT = 1 mA
30
20
10
30
SiP21106: 2.8 V
SiP21106: 2.8 V
0
25
0
25
50
75
100
125
0
150
1
2
3
I OUT (mA)
5
6
VIN (V)
Ground Current vs. Output Current
Ground Current vs. Input Voltage at 25 °C
80
2.820
SiP21106
C BP = 10 nF
70
SiP21106: 2.8 V
VIN = 3.8 V
I OUT = 10 mA
60
2.800
IOUT = 1 mA
50
V OUT (V)
PSRR (dB)
4
40
30
2.780
IOUT = 50 mA
2.760
IOUT = 150 mA
20
2.740
10
0
10
100
1000
10 000
100 000
1 000 000
2.720
- 40
- 15
10
35
60
Frequency (Hz)
Temperature (°C)
PSRR
Output Voltage Accuracy vs. Load Current
85
400
SiP21106: 2.8 V
350
Output Noise (µV)
300
250
200
150
100
50
0
0.001
0.0056
0.01
0.056
0.1
BP Capacitance (µF)
Output Noise vs. BP Capacitance
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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TYPICAL OPERATING WAVEFORMS
IOUT (100 mA/DIV)
IOUT (100 mA/DIV)
VOUT (50 mV/DIV)
VOUT (50 mV/DIV)
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
SiP21106: 4.6 V
VIN = 5.5 V
VOUT = 4.6 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
50 µs/DIV
Load Transient Response
50 µs/DIV
Load Transient Response
SiP21106: 2.8 V
VIN = 3.8 to 4.8 V
VOUT = 2.8 V
IOUT = 150 mA
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
SiP21106: 4.6 V
VIN = 5.0 to 5.5 V
VOUT = 4.6 V
IOUT = 150 mA
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
VIN (1 V/DIV)
AC Coupling
AC Coupling
VIN (200 mV/DIV)
VOUT (10 mV/DIV)
VOUT (10 mV/DIV)
200 µs/DIV
Line Transient Response
200 µs/DIV
Line Transient Response
SiP21106: 4.6 V
VIN = 5.0 to 5.5 V
VOUT = 4.6 V
IOUT = 1 mA
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
SiP21106: 2.8 V
VIN = 3.8 to 4.8 V
VOUT = 2.8 V
IOUT = 1 mA
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
AC Coupling
VIN (1 V/DIV)
AC Coupling
VIN (200 mV/DIV)
VOUT (10 mV/DIV)
200 µs/DIV
Line Transient Response
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VOUT (10 mV/DIV)
200 µs/DIV
Line Transient Response
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
CBP = 10 nF
IOUT (100 mA/DIV)
IOUT (50 mA/DIV)
50 ms/DIV
Output Short Thermal Cycling
50 ms/DIV
Output Short Circuit Current
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 150 mA
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 150 mA
VEN (500 mV/DIV)
VEN (1 V/DIV)
VOUT (500 mV/DIV)
VOUT (500 mV/DIV)
20 µs/DIV
Output Voltage Power-Down
VOUT (500 mV/DIV)
SiP21107: 1.8 V
VIN = 2.8 V
VOUT = 1.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
POK (1 V/DIV)
20 ms/DIV
POK pin goes low to indicate output under-voltage
fault condition
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
20 µs/DIV
Output Voltage Start-Up
VOUT (500 mV/DIV)
POK (1 V/DIV)
SiP21107: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
20 ms/DIV
POK pin goes low to indicate output under-voltage
fault condition
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SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
SiP21107: 1.8 V
VIN = 2.8 V
VOUT = 1.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
VOUT (500 mV/DIV)
VOUT (500 mV/DIV)
SiP21107: 2.8 V
VIN = 3.8 V
POK (1 V/DIV)
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 1 mA
POK (1 V/DIV)
20 µs/DIV
POK pin is actively high to indicate an output normal
operation condition on regular
20 µs/DIV
POK pin is actively high to indicate an output normal
operation condition on regular
TYPICAL WAVEFORMS
Noise Spectral Density (µV/√Hz)
1
SiP21106: 2.8 V
VIN = 4.5 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 150 mA
VOUT (100 µV/DIV)
VNOISE = 60 µVRMS
0.1
SiP21106: 2.8 V
VIN = 3.8 V
VOUT = 2.8 V
CIN = 1 µF
COUT = 1 µF
CBP = 10 nF
IOUT = 100 mA
0.01
10
2 ms/DIV
Output Noise
100
1K
10K
100K
1M
Frequency (Hz)
Output Noise Spectral Density
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
Enable
Error-Amp
* ** ***
BP/Adj/POK
Bandgap
Reference
VOUT
Current Limit and
Thermal
+
POK
-
0.94 VOUT
SiP21106: BP
SiP21107: POK
SiP21108: Adj
* SiP21106: BP
*** SiP21107: POK
** SiP21108: Adj
GND
Figure 3.
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
DETAILED DESCRIPTION
As shown in the block diagram, the circuit consists of a
bandgap reference, error amplifier, P-channel pass
transistor and an internal feedback resistor voltage divider,
which is used to monitor and control the output voltage.
A constant 1.2 V bandgap reference voltage is applied to the
non-inverting input of the error amplifier. The error amplifier
compares this reference with the feedback voltage on its
inverting input and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the
pass-transistor gate is pulled low. This increases the
PMOS's gate to source voltage and allows more current to
pass through the transistor to the output which increases the
output voltage. Conversely, if the feedback voltage is higher
than the reference voltage, the pass transistor gate is pulled
high, decreasing the gate-to-source voltage, thereby
allowing less current to pass to the output and causing it to
drop.
Internal P-Channel Pass Transistor
A 0.9 (typical) P-channel MOSFET is used as the pass
transistor for the SiP21106, SiP21107, SiP21108 part series.
The MOSFET transistor offers many advantages over the
more, formerly, common PNP pass transistor designs, which
ultimately result in longer battery lifetime. The main
disadvantage of PNP pass transistors is that they require a
certain base current to stay on, which significantly increases
under heavy load conditions. In addition, during dropout,
when the pass transistor saturates, the PNP regulators
waste considerable current. In contrast, P-channel
MOSFETS require virtually zero-base drive and do not suffer
from the stated problems. These savings in base drive
current translate to lower quiescent current which is typical
around 35 µA as shown in the Typical Characteristics.
VIN
1.2 V
Reference
+
Error-Amp
VOUT
-
R1
R2
Figure 4.
The SiP21108 has a user-adjustable output that can be set
through the resistor feedback network consisting of R1 and
R2. R2 range of 100K to 400K is recommended to be
consistent with ground current specification. R1 can then be
determined by the following equation:
R1 = R 2 x (
VOUT
Vref
- 1)
Where Vref is typically 1.2005 V. Use 1 % or better resistors
for better output voltage accuracy (see Figure 4).
Current Limit
The SiP21106, SiP21107, SiP21108 include a current limit
block which monitors the current passing through the pass
transistor through a current mirror and controls the gate
voltage of the MOSFET, limiting the output current to 330 mA
(typical). This current limit feature allows for the output to be
shorted to ground for an indefinite amount of time without
damaging the device.
Shutdown and Auto-Dischage/No-Discharge
Bringing the EN voltage low will place the part in shutdown
mode where the device output enters a high-impedance
state and the quiescent current is reduced to below 1 µA,
reducing the drain on the battery in standby mode and
increasing standby time. Connect EN pin to input for normal
operation. The output has an internal pull down to discharge
the output to ground when the EN pin is low. The internal pull
down is a 100 typical resistor, which can discharge a 1 µF
in less than 1 ms. Refer to Typical Operating Waveforms for
turn-off waveforms.
Thermal-Overload Protection
The thermal overload protection limits the total power
dissipation and protects the device from being damaged.
When the junction temperature exceeds TJ = 150 °C, the
device turns the P-channel pass transistor off allowing the
device to cool down. Once the temperature drops by about
20 °C, the thermal sensor turns the pass transistor on again
and resumes normal operation. Consequently, a continuous
thermal overload condition will result in a pulsed output. It is
generally recommended to not exceed the junction
temperature rating of 125 °C for continuous operation.
Output Voltage Selection
The SiP21106 has fixed voltage outputs that are preset to
voltages from 1.2 V to 4.6 V (see Ordering Information).
Noise Reduction in SiP21106
For the SiP21106, an external 10 nF bypass capacitor at BP
pin is used to create a low pass filter for noise reduction. The
startup time is fast, since a power-on circuit pre-charges the
bypass capacitor. After the power-up sequence the
pre-charge circuit is switched to standby mode in order to
save current. It is therefore not recommended to use larger
bypass capacitor values than 50 nF. When the circuit is used
without a capacitor, stable operation is guaranteed.
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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End of Life. Last Available Purchase Date is 31-Dec-2014
SiP21106, SiP21107, SiP21108
Vishay Siliconix
POK Status in SiP21107
The POK comparator monitors the output until the supply
comes up to specified percentage of VIN. This open drain
NMOS output requires an external pull-up resistor to either
VOUT or VIN. The internal NMOS can drive up to 0.5 mA
loads. POK pin is active high to indicate that output is within
percentage tolerance. POK goes low when output is outside
of this tolerance as when in dropout, over current and
thermal shutdown.
The GND pin of the SiP2110 acts as both the electrical
connection to GND as well as a path for channeling away
heat. Connect this pin to a GND plane to maximize heat
dissipation. Once maximum power dissipation is calculated
using the equation above, the maximum allowable output
current for any input/output potential can be calculated as
APPLICATION INFORMATION
PCB Layout
The component placement around the LDO should be done
carefully to achieve good dynamic line and load response.
The input and noise capacitor should be kept close to the
LDO. The rise in junction temperature depends on how
efficiently the heat is carried away from junction-to-ambient.
The junction-to-lead thermal impedance is a characteristic of
the package and is fixed. The thermal impedance between
lead-to-ambient can be reduced by increasing the copper
area on PCB. Increase the input, output and ground trace
area to reduce the junction-to-ambient thermal impedance.
Input/Output Capacitor Selection and Regulator Stability
It is recommended that a low ESR 1 µF capacitor be used on
the SiP21106, SiP21107, SiP21108 input. A larger input
capacitance with lower ESR would improve noise rejection
and line-transient response. A larger input bypass capacitor
may be required in applications involving long inductive
traces between the source and LDO. The circuit is stable with
only a small output capacitor equal to 6 nF/mA ( 1 µF at
150 mA) of load. Since the bandwidth of the error amplifier is
around 1 MHz - 3 MHz and the dominant pole is at the output
node, the capacitor should be capacitive in this range, i.e., for
150 mA load current, an ESR < 0.4 is necessary. Parasitic
inductance of about 10 nH can be tolerated. Applying a larger
output capacitor would increase power supply rejection and
improve load-transient response. Some ceramic dielectrics
such as the Z5U and Y5V exhibit large capacitance and ESR
variation over temperature. If such capacitors are used, a
2.2 µF or larger value may be needed to ensure stability over
the industrial temperature range. If using higher quality
ceramic capacitors, such as those with X7R and Y7R
dielectrics, a 1 µF capacitor will be sufficient at all operating
temperatures.
IOUT(max) =
P (max)
VIN - VOUT
Operating Region and Power Dissipation
An important consideration when designing power supplies
is the maximum allowable power dissipation of a part. The
maximum power dissipation in any application is dependant
on the maximum junction temperature, TJ(max) = 125 °C, the
ambient temperature, TA, and the junction-to-ambient
thermal resistance for the package, which is the summation
of J-C, the thermal resistance of the package, and C-A, the
thermal resistance through the PC board and copper traces.
Power dissipation may be expressed as:
P(max) =
TJ (max) - TA
θ J-C + θ C-A
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74442.
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14
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Package Information
www.vishay.com
Vishay Siliconix
Thin SOT-23 : 5- and 6-Lead (Power IC only)
e1
6
5
4
E1
1
2
E
3
-B-
4
Pin #1
indetifier
e
0.15 M
C B A
b
-AD
4 x θ1
0.17 ref
c
R
A2
R
L
A
Gage plane
Seating plane
θ
Seating plane
4 x θ1
A1
0.08 C
L
(L1)
-CNotes:
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
3. This part is fully compliant with JEDEC MO-193.
4. Detail of Pin #1 indentifier is optional.
MILLIMETERS
INCHES
DIM.
MIN.
NOM.
MAX.
MIN.
NOM.
A
0.91
1.00
1.10
0.036
0.039
MAX.
0.043
A1
0.00
0.05
0.10
0.000
0.002
0.004
0.039
A2
0.85
0.90
1.00
0.033
0.035
b
0.30
0.40
0.45
0.012
0.016
0.018
c
0.10
0.15
0.20
0.004
0.006
0.008
D
2.85
2.95
3.10
0.112
0.116
0.122
E
2.70
2.85
2.98
0.106
0.112
0.117
E1
1.525
1.65
1.70
0.060
0.065
0.067
0.50
0.014
e
L
0.95 BSC
0.30
0.40
L1
0.60 ref.
L2
0.25 BSC
0.0374 BSC
-
0.020
0.024 BSC
0.010 BSC
0°
4°
8°
0°
4°
8°
1
4°
10°
12°
4°
10°
12°
ECN: E13-1126-Rev. B, 01-Jul-13
DWG: 5926
Revision: 01-Jul-13
Document Number: 72821
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SC-70:
3/4/5/6-LEADS (PIC ONLY)
0.15 (0.006)
D
C
e1
A
A
D
N5
N4
N3
E/2
E1/2
E
E/1
0.15 (0.006)
C
Pin 1
N1
N2
B
e
See Detail A
C
0.10 (0.004)
M
C
A
b
B
U1
A2
A
SEATING
PLANE
0.10 (0.004)
C
A1
C
H
(b)
0.15 (0.0059)
b1
c1
GAGE PLANE
c
Base Metal
DETAIL A
SECTIION A-A
Pin
Code
N1
N2
N3
N4
N5
U
L
LEAD COUNT
NOTES:
3
4
5
6
1.
Dimensioning and tolerancing per ANSI Y14.5M-1994.
−
−
2
2
2.
2
2
3
3
Controlling dimensions: millimeters converted to inch dimensions are
not necessarily exact.
−
3
4
4
3.
3
−
−
5
Dimension “D” does not include mold flash, protrusion or gate burr.
Mold flash, protrusion or gate burr shall not exceed 0.15 mm
(0.006 inch) per side.
−
4
5
6
4.
The package top shall be smaller than the package bottom.
Dimension “D” and “E1” are determined at the outer most extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate burrs
and interlead flash, but including any mismatch between the top and
bottom of the plastic body.
Document Number: 73201
19-Nov-04
www.vishay.com
1
Package Information
Vishay Siliconix
MILLIMETERS
INCHES
Dim
Min
Nom
Max
Min
Nom
Max
A
0.80
−
1.10
0.031
−
0.043
A1
0.00
−
0.10
0.000
−
0.004
A2
0.80
0.90
1.00
0.031
0.035
0.040
b
0.15
−
0.30
0.006
−
0.012
b1
0.15
0.20
0.25
0.006
0.008
0.010
c
0.08
−
0.25
0.003
−
0.010
c1
0.08
0.13
0.20
0.003
0.005
0.008
D
1.90
2.10
2.15
0.074
0.082
0.084
E
2.00
2.10
2.20
0.078
0.082
0.086
E1
1.15
1.25
1.35
0.045
0.050
0.055
e
0.65 BSC
0.0255 BSC
e1
1.30 BSC
0.0512 BSC
L
0.26
0.36
0.46
0.010
0.014
0.018
U
0_
−
8_
0_
−
8_
U1
4_
10_
4_
10_
ECN: S-42145—Rev. A, 22-Nov-04
DWG: 5941
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2
Document Number: 73201
19-Nov-04
Package Information
Vishay Siliconix
PowerPAK ® TSC75-6L (Power IC only)
D1
Exposed pad
e
b
D
Pin4
Pin 5
Pin6
K
E
PPAK TSC75
(1.6 x 1.6 mm)
E1
Exposed pad
K
L
Pin3
Pin 2
Pin1
e1
K2
Pin 1 Dot
By Marking
K2
Top View
Bottom View
A
C
A1
Side View
MILLIMETERS
INCHES
DIM
Min
Nom
Max
Min
Nom
Max
A
0.50
0.55
0.65
0.020
0.022
0.026
A1
0
-
0.05
0
-
0.002
b
0.20
0.25
0.30
0.008
0.010
0.012
C
0.10
0.15
0.20
0.006
0.008
0.010
D
1.55
1.60
1.65
0.0061
0.063
0.065
D1
0.95
1.00
1.05
0.037
0.039
0.041
E
1.55
1.60
1.65
0.061
0.063
0.065
E1
0.55
0.60
0.65
0.022
0.024
0.026
e
0.50 BSC
e1
0.020 BSC
1.00 BSC
0.039 BSC
K
0.15
-
-
0.006
K2
0.20
-
-
0.008
L
0.20
0.25
0.30
0.008
-
-
0.010
0.012
ECN: S-61919-Rev. A, 02-Oct-06
DWG: 5955
Document Number: 74416
02-Oct-06
www.vishay.com
1
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Disclaimer
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
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