SIP41103DM-T1-E3

SiP41103 Vishay Siliconix Synchronous Rectification N-Channel MOSFET Driver for DC/DC Conversion FEATURES • 5 V Gate Drive • Undervoltage Lockout • Internal Bootstrap Diode • Adaptive Shoot-Through Protection • Synchronous MOSFET Disable • Adjustable Highside Propagation Delay • Switching Frequency Up to 1 MHz • Drive MOSFETs In 4.5 to 50 V Systems DESCRIPTION SiP41103 is a high-speed synchronous rectification MOSFET driver with adaptive shoot-through protection for use in high frequency, high-current, multiphase DC-DC synchronous rectifier buck converter. It is designed to operate at the switching frequencies up to 1 MHz. The high-side driver is bootstrapped to allow driving N-Channel MOSFET. Adaptive shootthrough protection prevents simultaneous conduction of external MOSFETs. Adding a capacitor to the delay pin can further increase the high-side driver turn-on delay by 1.2 ns/pF for further shoot-through protection. Pb-free Available RoHS* COMPLIANT APPLICATIONS • Multi-Phase DC/DC Conversion • High Current Synchronous Buck Converters • High Frequency Synchronous Buck Converters • Asynchronous-to-Synchronous Adaptations • Mobile Computer DC/DC Converters • Desktop Computer DC/DC Converters The SiP41103 is available in both standard and lead (Pb)-free 10-Pin MLP33 packages and is specified to operate over the industrial temperature range of - 40 °C to 85 °C. TYPICAL APPLICATION CIRCUIT + 5 to 50 V +5V 1 µF VDD BOOT DELAY 0.1 µF 10 pF OUTH SiP41103 PWM LX VOUT Controller ENSYNC OUTL GND GND GND *Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 72718 S-61692–Rev. E, 04-Sep-06 www.vishay.com 1 SiP41103 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND = 0 V) Limit Parameter VDD, PWM, ENSYNC, DELAY 7 LX, BOOT 55 BOOT to LX V 7 Storage Temperature - 40 to 150 Operating Junction Temperature °C 125 Power Dissipationa,b Thermal Impedance(ΘJA Unit MLP-33 )a,b 960 mW 105 °C/W Notes: a. Device mounted with all leads soldered or welded to PC board b. Derate 9.6 mW/°C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE (All voltages referenced to GND = 0 V) Parameter VDD VBOOT CBOOT Operating Temperature Range Limit 4.5 to 5.5 4.5 to 50 100 nF to 1 µF - 40 to 85 Unit V °C SPECIFICATIONSa Parameter Symbol Test Conditions Unless Specified VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = - 40 to 85 °C Limits Mina Typb Maxa Unit Power Supplies Supply Voltage VDD Quiescent Current IDDQ fPWM = 1 MHz, CLOAD = 0 ISD1 PWM = 0 V ISD2 PWM = 5 V 30 VBBM LX Falling 1 Shutdown Current 4.5 2.3 5.5 V 3.0 mA 1 60 µA Reference Voltage Break-Before-Make V PWM Input Input High VIH Input Low VIL Bias Current IB VDD 4.0 0.5 ± 0.3 ±1 V µA ENSYNC Inputs Input High VIH Input Low VIL 1.0 Bias Current IB ±1 µA VDD 2.0 V High-Side Undervoltage Lockout Threshold VUVHS Rising or Falling 2.5 3.35 3.75 V VF IF = 10 mA, TA = 25 °C 0.7 0.76 0.82 V Bootstrap Diode Forward Voltage www.vishay.com 2 Document Number: 72718 S-61692–Rev. E, 04-Sep-06 SiP41103 Vishay Siliconix SPECIFICATIONSa Parameter Symbol Test Conditions Unless Specified VDD = 5 V, VBOOT - VLX = 5 V, CLOAD = 3 nF TA = - 40 to 85 °C Limits Mina Typb Maxa Unit MOSFET Drivers High-Side Drive Currentc Low-Side Drive Current c High-Side Driver Impedance Low-Side Driver Impedance IPKH(source) 0.9 IPKH(sink) 1.1 IPKL(source) 0.8 A IPKL(sink) 1.5 RDH(source) 2.5 3.8 RDH(sink) 2.2 3.3 RDL(source) 3.4 5.1 RDL(sink) 1.4 2.1 High-Side Rise Time trH 10 % - 90 % 32 40 High-Side Fall Time tfH 90 % - 10 % 36 45 High-Side Propagation Delayc Low-Side Rise Time Low-Side Fall Time Low-Side Propagation Delayc td(off)H See Timing Waveforms 20 td(on)H See Timing Waveforms 30 trL 10 % - 90 % 45 55 30 tfL 90 % - 10 % 20 td(off)L See Timing Waveforms 30 td(on)L See Timing Waveforms 30 Ω ns LX Timer tLX 420 Threshold Rising VUVLOR 4.3 Threshold Falling VUVLOF LX Falling Timeoutc ns VDD Undervoltage Lockout 3.7 4.1 Hysteresis 0.4 Power on Reset Timec 2.5 4.5 V ms Thermal Shutdown Temperature TSD Temperature Rising 165 Hysteresis TH Temperature Falling 25 °C Notes: a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40° to 85 °C). b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 5 V unless otherwise noted. c. Guaranteed by design. Document Number: 72718 S-61692–Rev. E, 04-Sep-06 www.vishay.com 3 SiP41103 Vishay Siliconix TIMING WAVEFORMS PWM 50 % 50 % 90 % 90 % OUTH 10 % 10 % tfH trH 90 % 90 % OUTL 10 % trL td(off)H tfL 10 % td(off)L td(on)H td(on)L LX 1V PIN CONFIGURATION AND TRUTH TABLE TRUTH TABLEa MLP33 OUTH BOOT PWM DELAY GND LX ENSYNC NC VDD OUTL 10 9 8 7 6 2 3 4 5 PWM ENSYNC OUTH L L L L L H L H H X H L OUTL Note: a. After the device is enabled. Top View ORDERING INFORMATION Standard Part Number Lead (Pb)-Free Part Number Temperature Range Marking SiP41103DM-T1 SiP41103DM-T1-E3 - 40 to 85 °C 41A3 Eval Kit Temperature Range SiP41103DB - 40 to 85 °C PIN DESCRIPTION Pin Number 1 Name OUTH High-side MOSFET gate drive 2 BOOT Bootstrap supply for high-side driver. A capacitor connects between BOOT and LX 3 PWM Input signal for the MOSFET drivers 4 DELAY 5 6 GND OUTL 7 VDD 8 9 NC ENSYNC 10 LX www.vishay.com 4 Function Connection for the highside dealy adjustment capacitors Ground Synchronous or low-side MOSFET gate drive + 5 V supply No Connect Enables OUTL, the driver for the synchronous MOSFET Connection for source of high-side MOSFET, drain of the low-side MOSFET and the inductor Document Number: 72718 S-61692–Rev. E, 04-Sep-06 SiP41103 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VDD BOOT OUTH UVLO OTP LX DELAY − + DELAY VBBM PWM ENSYNC VDD OUTL GND Figure 1. DETAILED OPERATION PWM The PWM pin controls the switching of the external MOSFETs. The driver logic operates in a noninverting configuration. The PWM input stage should be driven by a signal with fast transition times, like those provided by a PWM controller or logic gate, (< 200 ns). The PWM input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a switching output when the input switching threshold voltage is reached. Enable The device is enabled by edge sensing of transitions on PWM, high or low. A minimum PWM frequency of 2 kHz is required to keep the device enabled. When continuous PWM transitions are present, and after power-on reset time has elapsed, OUTH and OUTL will become active. Low-Side Driver The supplies for the low-side driver are VDD and GND. During shutdown, OUTL is held low. High-Side Driver The high-side driver is isolated from the substrate to create a floating high-side driver so that an N-Channel MOSFET can be used for the high-side switch. The supplies for the high-side driver are BOOT and LX. The voltage is supplied by a floating bootstrap capaci- Document Number: 72718 S-61692–Rev. E, 04-Sep-06 tor, which is continually recharged by the switching action of the output. During shutdown OUTH is held low. Bootstrap Circuit The internal bootstrap diode and a bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode replaces the external Schottky diode and bootstrap only a capacitor is necessary to complete the circuit. The bootstrap capacitor is sized according to. CBOOT = (QGate/ΔVBOOT- LX) x 10 where QGATE is the gate charge needed to turn on the high-side MOSFET and ΔVBOOT-LX is the amount of droop allowed in the bootstrap supply voltage when the high-side MOSFET is driven high. The bootstrap capacitor value is typically 0.1 µF to 1 µF. The bootstrap capacitor voltage rating must be greater than VDD + 5 V to withstand transient spikes and ringing. Shoot-Through Protection The external MOSFETs are prevented from conducting at the same time during transitions. Break-beforemake circuits monitor the voltages on the LX pin and the OUTL pin and control the switching as follows: When the signal on PWM goes low, OUTH will go low after an internal propagation delay. After the voltage www.vishay.com 5 SiP41103 Vishay Siliconix on LX falls below 1 V by the inductor action, the lowside driver is enabled and OUTL goes high after some delay. When the signal on PWM goes high, OUTL will go low after an internal propagation delay. After the voltage on OUTL drops below 1 V the high-side driver is enabled OUTH will go high after an internal propagation delay. If LX does not drop below 1 V within 400 ns after OUTH goes low, OUTL is forced high until the next PWM transition. Delay The addition of a capacitor between DELAY and GND will increase the propagation delay time for OUTH going high. Delay capacitance may be added to prevent shoot-through current in the low-side MOSFET due to the finite time between OUTL going low and the continuing conduction of the low-side MOSFET. Choose a MOSFET with lower gate resistance to reduce this effect. If necessary, choose a capacitor value that prevents MOSFET conduction under worstcase temperature and manufacturing conditions. Propagation delay is increased according to the ratio of 1.2 ns/pF. Synchronous MOSFET Enable Under light load conditions, efficiency can be increased by disabling the synchronous MOSFET, thus avoiding the gate charge losses of the synchronous MOSFET. When ENSYNC is low, OUTL is forced low. When high, the low-side driver operates normally. ENSYNC should be driven by a 5-V signal. Shutdown The driver enters shutdown mode when a period of inactivity on PWM elapses. Shutdown current is less than 1 µA. VDD Bypass Capacitor MOSFET drivers draw large peak currents from the supplies when they switch. A local bypass capacitor is required to supply this current and reduce power supply noise. Connect a 1 µF ceramic capacitor as close as practical between the VDD and GND pins. Undervoltage Lockout Undervoltage lockout prevents control of the circuit until the supply voltages reach valid operating levels. The UVLO circuit forces OUTL and OUTH to low when VDD is below its specified voltage. A separate UVLO forces OUTH low when the voltage between BOOT and LX is below the specified voltage. Thermal Protection If the temperature rises above 165 °C, the thermal protection disables the drivers. The drivers are re-enabled after the temperature has decreased below 140 °C. TYPICAL CHARACTERISTICS 50 140.0 120.0 40 30 1 MHz td(on)H(ns) IDD (mA) 100.0 500 kHz 20 200 kHz 80.0 60.0 40.0 10 20.0 0 0.0 0 1 2 3 CLOAD (nF) IDD vs. CLOAD vs. Frequency www.vishay.com 6 4 5 0 10 20 30 40 50 60 70 80 90 100 110 CDelay (pF) High Side Turn On Delay vs. CDELAY Document Number: 72718 S-61692–Rev. E, 04-Sep-06 SiP41103 Vishay Siliconix TYPICAL WAVEFORMS PWM IN 2 V/div PWM IN 2 V/div VLX 2 V/div 50 ns/div VLX 2 V/div 50 ns/div PWM IN 5 V/div PWM IN 5 V/div HS Gate 5 V/div HS Gate 5 V/div LS Gate 5 V/div LS Gate 5 V/div 50 ns/div 50 ns/div Figure 4. PWM Signal vs. HS Gate and LS Gate (Rising) Figure 5. PWM Signal vs. HS Gate and LS Gate (Falling) ENSYNC 5 V/div HS Gate 5 V/div LS Gate 5 V/div 50 s/div Figure. 6 ENSYNC Delay Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72718 Document Number: 72718 S-61692–Rev. E, 04-Sep-06 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1