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SN74CBT16211C - 24-BIT FET BUS SWITCH 5-V BUS SWITCH WITH 2-V UNDERSHOOT PROTECTION - Texas Instruments

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SN74CBT16211C
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TI[TexasInstruments]
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http://www.ti.com/
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SN74CBT16211C - 24-BIT FET BUS SWITCH 5-V BUS SWITCH WITH 2-V UNDERSHOOT PROTECTION - Texas Instrume...
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SN74CBT16211C 24 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 D Member of the Texas Instruments D D D D D D D D D D D D D Widebus Family Undershoot Protection for Off-Isolation on A and B Ports Up To −2 V Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating DGG, DGV, OR DL PACKAGE (TOP VIEW) NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 1A11 1A12 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 1B11 1B12 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 NC − No internal connection description/ordering information ORDERING INFORMATION TA PACKAGE† Tube SSOP − DL −40°C to 85°C TSSOP − DGG Tape and reel Tube Tape and reel ORDERABLE PART NUMBER SN74CBT16211CDL SN74CBT16211CDLR SN74CBT16211CDGG SN74CBT16211CDGGR CBT16211C CBT16211C TOP-SIDE MARKING TVSOP − DGV Tape and reel SN74CBT16211CDGVR CY211C † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 SN74CBT16211C 24 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION description/ordering information (continued) The SN74CBT16211C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16211C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBT16211C is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and the high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each 12-bit bus switch) INPUT OE L H INPUT/OUTPUT A B Z FUNCTION A port = B port Disconnect logic diagram (positive logic) 2 1A1 SW 54 1B1 14 1A12 SW 42 1B12 56 1OE 15 2A1 SW 41 2B1 28 2A12 SW 29 2B12 55 2OE 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT16211C 24 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† † EN is the internal enable signal applied to the switch. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) MIN VCC VIH VIL VI/O Supply voltage High-level control input voltage Low-level control input voltage Data input/output voltage 4 2 0 0 MAX 5.5 5.5 0.8 5.5 UNIT V V V V TA Operating free-air temperature −40 85 °C NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 SN74CBT16211C 24 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VIKU IIN IOZ‡ Ioff ICC ∆ICC§ Cin Cio(OFF) Cio(ON) Control inputs Control inputs Control inputs Data inputs Control inputs VCC = 4.5 V, VCC = 5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VIN = 3 V or 0 VI/O = 3 V or 0, VI/O = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ron¶ VCC = 4.5 V 4.5 TEST CONDITIONS IIN = −18 mA 0 mA > II ≥ −50 mA, VIN = VCC or GND, VIN = VCC or GND VO = 0 to 5.5 V, VI = 0, VO = 0 to 5.5 V, II/O = 0, VIN = VCC or GND, One input at 3.4 V, Switch OFF, Switch ON, VI = 2.4 V, VI = 0 MIN TYP† MAX −1.8 Switch OFF −2 ±1 Switch OFF, VIN = VCC or GND VI = 0 Switch ON or OFF Other inputs at VCC or GND 4.5 VIN = VCC or GND VIN = VCC or GND IO = −15 mA IO = 64 mA IO = 30 mA 5.5 14.5 8 3 3 12 6 6 Ω ±10 10 3 2.5 UNIT V V µA µA µA µA mA pF pF pF VI = 2.4 V, IO = −15 mA 5 10 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tpd# ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B VCC = 4 V MIN MAX 0.24 6.5 1.5 VCC = 5 V ± 0.5 V MIN MAX 0.15 6 ns ns UNIT tdis A or B 6.5 1.5 6 ns OE # The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT16211C 24 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 undershoot characteristics (see Figures 1 and 2) PARAMETER TEST CONDITIONS VIN = VCC or GND MIN 2 TYP† VOH−0.3 MAX UNIT V VOUTU VCC = 5.5 V, Switch OFF, † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. VCC Input Generator 50 Ω Ax VS 11 V 100 kΩ DUT Bx 100 kΩ 10 pF Output (VOUTU) Input (Open Socket) 90 % 2 ns 10 % 20 ns VOH VOH − 0.3 2 ns 10 % −2 V 90 % 5.5 V Figure 1. Device Test Setup Figure 2. Transient Input Voltage (VI) and Output Voltage (VOUTU) Waveforms (Switch OFF) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 SN74CBT16211C 24 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω VG1 50 Ω DUT 7V Input Generator 50 Ω VG2 VI 50 Ω VO CL (see Note A) RL RL S1 Open GND TEST CIRCUIT TEST tpd(s) tPLZ/tPZL tPHZ/tPZH VCC 5 V ± 0.5 V 4V 5 V ± 0.5 V 4V 5 V ± 0.5 V 4V S1 Open Open 7V 7V Open Open RL 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω VI VCC or GND VCC or GND GND GND VCC VCC Output Control (VIN) tPZL CL 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF V∆ 0.3 V 0.3 V 0.3 V 0.3 V 3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V VOL + V∆ tPHZ VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL Output Control (VIN) tPLH Output 3V 1.5 V 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) Output Waveform 1 S1 at 7 V (see Note B) tPZH Output Waveform 2 S1 at Open (see Note B) 1.5 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device 74CBT16211CDGGRE4 74CBT16211CDGVRE4 74CBT16211CDGVRG4 SN74CBT16211CDGG SN74CBT16211CDGGR SN74CBT16211CDGVR SN74CBT16211CDL SN74CBT16211CDLG4 SN74CBT16211CDLR SN74CBT16211CDLRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE PREVIEW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type TSSOP TVSOP TVSOP TSSOP TSSOP TVSOP SSOP SSOP SSOP SSOP Package Drawing DGG DGV DGV DGG DGG DGV DL DL DL DL Pins Package Eco Plan (2) Qty 56 56 56 56 56 56 56 56 56 56 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 35 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 20 20 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2007 Device Package Pins Site Reel Diameter (mm) 330 330 330 Reel Width (mm) 24 24 32 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 12 12 16 W Pin1 (mm) Quadrant 24 24 32 Q1 Q1 Q1 SN74CBT16211CDGGR SN74CBT16211CDGVR SN74CBT16211CDLR DGG DGV DL 56 56 56 MLA MLA MLA 8.6 6.8 11.35 15.8 10.1 18.67 1.8 1.6 3.1 TAPE AND REEL BOX INFORMATION Device SN74CBT16211CDGGR SN74CBT16211CDGVR SN74CBT16211CDLR Package DGG DGV DL Pins 56 56 56 Site MLA MLA MLA Length (mm) 333.2 333.2 336.6 Width (mm) 333.2 333.2 342.9 Height (mm) 31.75 31.75 41.3 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN 0,23 0,13 13 PLASTIC SMALL-OUTLINE 0,40 24 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 A 12 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,08 PINS ** DIM A MAX A MIN 14 3,70 3,50 16 3,70 3,50 20 5,10 4,90 24 5,10 4,90 38 7,90 7,70 48 9,80 9,60 56 11,40 11,20 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) 48 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 25 0.005 (0,13) M 48 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 A 24 0°– 8° 0.040 (1,02) 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10) PINS ** DIM A MAX 28 0.380 (9,65) 0.370 (9,40) 48 0.630 (16,00) 0.620 (15,75) 56 0.730 (18,54) 0.720 (18,29) 4040048 / E 12/01 A MIN NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) 48 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,50 48 0,27 0,17 25 0,08 M 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 0,25 0°– 8° A 0,75 0,50 1 24 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 48 56 64 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 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Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers RFID Low Power Wireless amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lpw Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated

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