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TRF2443 - Integrated IF Transceiver for Broadband Wireless Applications - Texas Instruments

型  号:
TRF2443
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1627.00KB 共72页
厂  商:
TI[TexasInstruments]
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http://www.ti.com/
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TRF2443 - Integrated IF Transceiver for Broadband Wireless Applications - Texas Instruments
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TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Integrated IF Transceiver for Broadband Wireless Applications 1 FEATURES Integrated TX Chain (165–175 MHz / 330–350 MHz) – Baseband Amplifiers – Quadrature Modulator – Digitally Controlled VGA – TX Output IP3: 29.5 dBm – TX Output Noise: –166 dBc/Hz Integrated RX Chain (140–165 MHz / 280–330 MHz) – IF Amplifiers – Analog and Digital VGA – Quadrature Demodulator – Baseband Filters – ADC Buffers – IF SAW Filter Bypass – RX Noise Figure: 4.3 dB – RX Input IP3: 9.5 dBm Integrated TX and RX Synthesizers Integrated Cross-Polarization Interference Cancellation (XPIC) Support Auxiliary RX Chain • DESCRIPTION The TRF2443 is a highly integrated full-duplex intermediate frequency (IF) transceiver designed for broadband point-to-point wireless communications applications. The receiver chain integrates a quadrature (IQ) demodulator and provides more than 90 dB of gain range, obtained via a combination of analog- and digital-controlled VGAs. The integrated programmable baseband low-pass filter gives the TRF2443 the flexibility to receive signals with different bandwidths, while also helping to remove interferer signals before they reach the ADC. Additionally, the TRF2443 gives the flexibility to add an external IF filter to further remove unwanted signals. The TRF2443 transmitter chain integrates a quadrature (IQ) modulator driving a highly linear IF DVGA that provides 35 dB of gain range controlled via a serial programming interface (SPI). The TRF2443 includes the two synthesizers for the receiver and transmitter chains, removing the need for external LO generation circuitry and simplifying the implementation of a frequency-division duplexing (FDD) transceiver design. The TRF2443 also provides cross-polarization interference cancellation (XPIC) support via an integrated XPIC output amplifier and receiver chain. The TRF2443 is an ideal building block for implementing the IF transceiver function in the indoor unit (IDU), which is connected via a coaxial cable interface to the outdoor unit (ODU), of a point-to-point microwave backhaul split-architecture system. IF SAW XPIC AGC • • • • • • • • APPLICATIONS Wireless Microwave Backhaul Point-to-Point Microwave Broadband Wireless Applications WiMAX IF Transceiver RXAGC IF_OUT IF_IN XPIC OUT XPIC_IN XPIC_BBI 0/90 AGC CNTL from RXPLL IFAMP RX_IN XPIC_BBQ RXBBI 0/90 RX VGA RXBBQ TEMPOUT VCCs Temperature Sensor RXPLL S P I 3 CLKSPI DATASPI LESPI From SPI 7 TXI_IN TX VGA TX_OUT GNDs TXPLL Level Detect 0/90 TXQ_IN TX_PWD 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TRF2443 DEVICE DESCRIPTION IF SAW RXAGC IF_OUT IF_IN XPIC OUT XPIC_IN XPIC AGC XPIC_BBI 0/90 AGC CNTL from RXPLL IFAMP RX_IN XPIC_BBQ RXBBI 0/90 RX VGA RXBBQ TEMPOUT VCCs Temperature Sensor RXPLL S P I 3 CLKSPI DATASPI LESPI From SPI 7 TXI_IN TX VGA TX_OUT GNDs TXPLL Level Detect 0/90 TXQ_IN TX_PWD Figure 1. TRF2443 Functional Block Diagram RECEIVER DESCRIPTION IF SAW RX_AGC IF_OUT AGC CNTL LNA RX_IN IFVGA1 From SPI from RXPLL From SPI IFVGA2 IFVGA3 0/90 RX _BBQ IF_IN BB AMP/FLT RX VGA RX_BBI Figure 2. Receiver Chain Block Diagram The TRF2443 features a highly linear low-noise receiver chain with over 60 dB of analog-controlled gain range and more than 40 dB of gain range programmable via the serial programming interface (SPI) in 1-dB steps. Moreover, the TRF2443 gives the flexibility to add an external IF filter to further remove unwanted signals. Such an external filter can be bypassed using an internal path that can be enabled via SPI. The first block of the 2 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 receiver chain is a low-noise, highly linear IF amplifier (LNA). Its input is differential and internally matched to 50 Ω. The TRF2443 LNA attenuation is programmable from 0 dB to –19 dB, corresponding to an LNA gain of 17 dB to –2 dB (1-dB steps). The LNA is followed by three analog-controlled VGAs that provide more than 60 dB of gain range. The IFVGA1 output and IFVGA2 input can be connected externally (pins IFOUT and IFIN) through an external IF filter. An internal switch gives the flexibility to bypass the external filter. The VGAs provide a gain slope of 51 dB/V. The IFVGA3 drives the demodulator, which downconverts the IF input signal directly to baseband in-phase and quadrature. The demodulator block includes the local oscillator in-phase and quadrature generation circuitry followed by the LO buffer. The TRF2443 baseband section integrates a programmable-gain amplifier (PGA) and programmable low-pass filter. The baseband PGA minimum gain is 9 dB, and the maximum gain is 33 dB. The TRF2443 baseband low-pass filter cutoff frequency can be programmed from 2 MHz to 11 MHz by setting the cutoff-frequency control bits appropriately. The baseband output buffers (ADC drivers) are designed to drive directly an analog-to-digital converter (ADC), either dc- or ac-coupled. The output common mode of the ADC drivers is set externally via the RXBBCM pin (pin 40). When the TRF2443 is dc-connected to the ADC, the same dc common mode can be used for both the ADC and the TRF2443 baseband output. TRANSMITTER DESCRIPTION VCC From SPI TX_OUT 6 To feedback switch From TX PLL TXI_IN 0/90 TXAMP VCC TX_PWD ATT Level Detect TXQ_IN Figure 3. Transmitter Chain Block Diagram The transmitter chain integrates an IQ modulator followed by a variable attenuator and the final transmitter amplification stage. The last two blocks provide over 35 dB of gain range. A power-alarm circuit monitors the level at the modulator output, and its digital output goes low if the signal level falls below the user-specified threshold level relative to the expected level. The first block of the transmitter chain is the IQ modulator, which upconverts the incoming in-phase and quadrature signals to the TX IF frequency. The TRF2443 can be either acor dc-coupled to the digital-to-analog converter (DAC). The IQ modulator drives a variable attenuator. This block provides 5.5 dB of total attenuation range in 0.5-dB steps. The output amplifier integrates five attenuation steps of 6 dB each for total of 30 dB. The output amplifier in combination with the variable attenuator provides over 35.5 dB of monotonic output power control (0.5-dB steps). SYNTHESIZERS DESCRIPTION TRF2443 integrates two complete integer synthesizers for the receiver and transmitter chain. The RXVCO operates at 16 times the typical RX input frequency, and the TXVCO operates at 8 times the typical TX output frequency. Each synthesizer is composed of: • High-frequency VCO (around 2720 MHz for the TX VCO and 2240 MHz for the RX VCO) • N-divider (driven by the high-frequency VCO) done by an 8/9 prescaler followed by an A-B counter that drives the phase-frequency detector • Phase-frequency detector (PFD) (driven by the N-divider) that compares the VCO divided by N to the reference clock divided by R signals • Charge pump (driven by the PFD) which creates up and down current pulses, based on the incoming signals from the PFD. Its output is filtered and transformed to voltage by the external loop filter and applied to the VCO input control voltage. • An external reference clock must be applied to the REFIN (pin 16). The incoming signal is buffered and goes through a programmable divider (R-divider). Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 3 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com The VCO output is then routed through a programmable divider by 8 or 16 to create the TX and RX LO signals. The TRF2443 features a lock-detect output pin (LOCKDET, pin 5). This is a digital output that is high when both RX and TX synthesizers are locked, and it is low if one or both synthesizers are unlocked (or lose lock). XPIC DESCRIPTION The TRF2443 provides cross-polarization interference cancellation (XPIC) support via an integrated XPIC output amplifier and receiver chain. The XPIC output amplifier transmits the signal taken at the receiver demodulator input. The XPIC receiver section downconverts the input signal to baseband I and Q. It includes an IF VGA followed by a demodulator and a baseband amplifier. PINOUT DIAGRAM PFP Package (Top View) RDBKSPI VCCSPI DATASPI GNDTX TXOUTN TXOUTP VCCTX IFOUTP IFOUTN GNDRX GNDRX TXPWD MIXINDN MIXINDP PWRDET LOCKDET TXLOTEST VCCVCOTX GNDVCOTX VTUNETX CPOUTX GNDPLLTX VCCPLLTX VCCDIGTX GNDDIGTX VCCREF REFIN GNDREFIN GND TXBBQN TXBBQP 1 2 3 4 5 6 7 8 9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 TRF2443 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GNDRX CLKSPI LESPI RXAGC GNDTX VCCRX GND RXINN RXINP GNDIFIN GNDIFIN IFINN IFINP VCCIFIN XPICOUTP XPICOUTN RXLOTEST VCCVCORX GNDVCORX VTUNERX CPOUTRX GNDPLLRX VCCPLLRX VCCDIGRX GDNDIGRX RXBBIP RXBBIN RXBBQP RXBBQN 10 11 12 13 14 15 16 17 18 19 20 TXBBIP GND XPICBBQN XPICBBQP XPICBBCM TEMPOUT TXBBIN XPICBBIN GNDXPIC XPICAGC XPICINP GND XPICBBIP XPICINN GND VCCXPIC VCCXPIC2 RXBBCM GNDRX2 LDCAP P0027-04 4 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 PIN FUNCTIONS PIN NAME CLKSPI CPOUTRX CPOUTX DATASPI GND NO. 73 49 10 74 18, 31, 32, 36, 66 45 14 59, 60 48 11 17 61, 70, 71 39 79, 80 51 8 23 58 57 62 63 38 72 5 2 3 4 64 16 65 40 43 44 41 42 69 68 53 37 21 22 19 20 I/O I O O I – SPI clock RX PLL charge-pump output TX PLL charge-pump output SPI data Ground DESCRIPTION GNDDIGRX GNDDIGTX GNDIFIN GNDPLLRX GNDPLLTX GNDREFIN GNDRX GNDRX2 GNDTX GNDVCORX GNDVCOTX GNDXPIC IFINN IFINP IFOUTN IFOUTP LDCAP LESPI LOCKDET MIXINDN MIXINDP PWRDET RDBKSPI REFIN RXAGC RXBBCM RXBBIN RXBBIP RXBBQN RXBBQP RXINN RXINP RXLOTEST TEMPOUT TXBBIN TXBBIP TXBBQN TXBBQP – – – – – – – – – – – – I I O O I/O I O O O O O I I I O O O O I I O O I I I I RX PLL digital ground TX PLL digital ground RX chain ground RX PLL ground TX PLL ground Reference clock ground RX chain ground RX chain ground TX chain ground RX VCO ground TX VCO ground XPIC ground IFVGA2 input: negative terminal IFVGA2 input: positive terminal IFVGA1 output: negative terminal IFVGA1 output: positive terminal PLL lock detector decoupling capacitor pin SPI latch enable PLL lock detect output (digital HIGH = locked, LOW = unlocked) TX mixer output collector: negative terminal TX mixer output collector: positive terminal Power alarm output (digital HIGH = output power above threshold; LOW = output power below threshold) SPI data readback PLL reference clock input RX AGC control input RX chain common-mode input RX baseband output I: negative terminal RX baseband output I: positive terminal RX baseband output Q: negative terminal RX baseband output Q: positive terminal RX input: negative terminal RX input: positive terminal RX LO test pin Temperature sensor output TX baseband I input: negative input TX baseband I input: positive input TX baseband Q input: negative input TX baseband Q input: positive input Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 5 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com PIN FUNCTIONS (continued) PIN NAME TXLOTEST TXOUTN TXOUTP TXPWD VCCDIGRX VCCDIGTX VCCIFIN VCCPLLTX VCCPLLRX VCCREF VCCRX VCCSPI VCCTX VCCVCORX VCCVCOTX VCCXPIC VCCXPIC2 VTUNERX VTUNETX XPICAGC XPICBBCM XPICBBIN XPICBBIP XPICBBQN XPICBBQP XPICINN XPICINP XPICOUTN XPICOUTP NO. 6 78 77 1 46 13 56 12 47 15 67 75 76 52 7 29 33 50 9 30 24 27 28 25 26 34 35 54 55 I/O O O O I – – – – – – – – – – – – – I I I I O O O O I I O O TX LO test pin TX IF output: negative terminal TX IF output: positive terminal TX power down RX PLL digital power supply TX PLL digital power supply RX chain power supply TX PLL power supply RX PLL power supply Reference clock power supply RX chain power supply SPI power supply TX power supply RX VCO power supply TX VCO power supply XPIC power supply XPIC power supply RX VCO input control voltage VCO tune voltage input XPIC AGC control input XPIC common-mode input XPIC baseband I output: negative terminal XPIC baseband I output: positive terminal XPIC baseband Q output: negative terminal XPIC baseband Q output: positive terminal XPIC input XPIC input XPIC output XPIC output DESCRIPTION 6 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) VALUE Input voltage range ESD rating, HBM ESD rating, CDM TJ Tstg (1) (2) Junction temperature range Storage temperature range (2) UNIT V V V °C °C –0.3 to 5 2000 500 –40 to 150 –65 to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL CHARACTERISTICS Over recommended operating free-air temperature (unless otherwise noted) PARAMETER θJA Thermal derating, junction-to-ambient High-K board, still air MIN TYP 8.5 MAX UNIT °C/W RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted) MIN VCC_3V V_RXAGC V_XPICAGC TJ TA 3.3-V power-supply voltage Analog AGC voltage (pin 65) Analog AGC voltage (pin 30) Operating junction temperature Operating ambient temperature 3 0 0 0 –40 65 TYP 3.3 MAX 3.6 2 1 125 85 UNIT V V V °C °C DC CHARACTERISTICS VCC = 3.3 V; TJ = 65°C PARAMETER ICC Total supply current TEST CONDITIONS TX on; RX on (SAW off); XPIC off TX on; RX on (SAW on); XPIC off TX on; RX on (SAW on); XPIC on MIN TYP 947 965 1085 mA MAX UNIT DIGITAL INTERFACE CHARACTERISTICS VCC = 3.3 V; TJ = 65°C PARAMETER VIH VIL VOH VOL High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage TEST CONDITIONS MIN 2 0 0.8 VCC 0.2 VCC TYP MAX VCC 0.8 UNIT V V V V Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 7 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER CHARACTERISTICS VCC_3V = 3.3 V ±5%, TJ = 65°C , IF SAW filter insertion loss = 10 dB (1) (unless otherwise noted) PARAMETER fIF Input IF frequency LNA_ATT = 0; RXAGC = 2 V (3) Gmax (2) Maximum voltage gain LNA_ATT = 0; RXAGC = 2 V (4) LNA_ATT = 17; RXAGC = 2 V (3) LNA_ATT = 17; RXAGC = 2 V (4) LNA_ATT = 0; RXAGC = 0 V (3) Gmin (2) Minimum voltage gain LNA_ATT = 0; RXAGC = 0 V (4) LNA_ATT = 17; RXAGC = 0 V LNA_ATT = 17 (5) LNA attenuation setting through SPI RXAGC from 0 V to 2 V (6) (3) TEST CONDITIONS MIN TYP 140 MAX UNIT MHz From RX_IN to RX_BBI/RX_ BBQ 76 69 59 52 12 12 25 27 8 10 16.9 54 17.9 1.05 62 1.5 51 LNA_ATT = 0 (8) (9) LNA_ATT = 17 (10) (11) LNA_ATT = 0 (12) (13) LNA_ATT = 17 (14) (15) 86 68 dB dB LNA_ATT = 17; RXAGC = 0 V (4) LNA attenuation step ΔGstep ΔGrange Digital gain step Analog gain range Gain flatness Gain control slope NF IP3 Γin Gmax ΔGdig ΔGstep ΔGanalog NF IP3 Γin (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) Noise figure (7) Input IP3 Input return loss Maximum voltage gain Digital gain range Digital gain step Analog gain range Noise figure Input IP3 Input return loss LNA_ATT = 0, RXAGC = 2 V LNA_ATT = 17, RXAGC = 2 V LNA_ATT = 0, RXAGC = 2 V Z0 = 50 Ω, differential Programmed by SPI 18.9 dB dB dB dB dB/V From 110 MHz to 170 MHz 4.5 18.5 -9.5 3 6.5 –25 33 20 1.05 34 3.5 19.5 –13 6 23 dB dBm Z0 = 50 Ω, differential –12 dB dB dB dB dB dB dBm FROM RX_IN TO IF_OUT –12 dB 10 dB includes SAW filter insertion loss plus matching/board loss Gain measured from transformer input to RXBBI/Q output. External transformer insertion loss = 0.5 dB SAW filter path enabled; baseband amplifier gain setting set to 9 SAW filter path disabled; baseband amplifier gain setting set to 0 Attenuation measured from LNA_ATT = 0 state. Monotonicity of RX gain versus VAGC is specified up to the maximum voltage gain spec and not the maximum VAGC voltage. Automated test equipment 1-sigma measurement uncertainty of 0.15 dB. SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 55 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 3; total gain = 66 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 38 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 3; total gain = 49 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 9; total gain = 33 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 35 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path enabled; baseband amplifier gain setting set to 9; total gain = 16 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) SAW filter path disabled; baseband amplifier gain setting set to 0; total gain = 18 dB (gain measured from transformer input to RXBBI/Q output; external transformer insertion loss = 0.5 dB) 8 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER CHARACTERISTICS (continued) VCC_3V = 3.3 V ±5%, TJ = 65°C , IF SAW filter insertion loss = 10 dB (unless otherwise noted) PARAMETER FROM IF_IN TO RX_BBI (OR RX_BBQ) Gmax ΔGdig ΔGstep ΔGanalog NF Maximum voltage gain Digital gain range Digital gain step Analog gain range Noise figure Image rejection Output common mode Baseband output load BASEBAND LOW-PASS FILTER fC_ON ATT30M 3-dB cutoff frequency Filter rejection at 30 MHz Filter on, programmed via SPI Filter bypassed 3-dB point with fC = 2.3 MHz (16) TEST CONDITIONS RXAGC = 2 V, RXBB_GAIN = 9 Programmed by SPI MIN TYP 58 24 1 28 MAX UNIT dB dB dB dB dB dB V pF kΩ RXAGC = 2 V, RXBB_GAIN = 9 RXAGC = 0 V, RXBB_GAIN = 9 See RX Image Rejection section Parallel capacitor Parallel resistor 2 12.5 28 -40 1.5 15 1 11 1 2.2 25 (16) MHz dB MHz kHz dB MHz dB 3-dB corner-frequency step (17) Rejection at 4.5 MHz with fC = 2.3 MHz Filter rejection 36 Rejection at 8.75 MHz with fC = 2.3 MHz (16) Rejection at 17.5 MHz with fC = 2.3 MHz 3-dB point with fC = 8.5 MHz (16) Rejection at 18 MHz with fC = 8.5 MHz (16) Rejection at 35 MHz with fC = 8.5 MHz (16) Rejection at 70 MHz with fC = 8.5 MHz (16) After room-temperature cutoff-frequency calibration (17) Baseband filter 3-dB corner frequency control step via SPI around fC = 2.3 MHz (16) (16) 76 80 8.3 30 65 80 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 9 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TRANSMITTER CHARACTERISTICS VCC_3V = 3.3 V ± 5%, TJ = 65°C (unless otherwise noted) PARAMETER fIout Pmax Pmin Grange Gstep Nout TX output frequency Maximum output power Minimum output power Gain range 1-dB gain step Output noise floor TX ATT set to 0 (1) TX ATT set to 35 Programmed by SPI Two consecutive 1-dB steps TX ATT set to 4 (2) TX ATT set to 31 (2) Two tones of –2.5 dBm each at TX output (3) Two tones of –29.5 dBm each at TX output (3) Calibrated; TX ATT set to 4 (4) Uncalibrated (5) See See (1) (1) TEST CONDITIONS MIN TYP 340 MAX UNIT MHz dBm FROM TXBBI/Q INPUTS TO TX RFOUT 2.5 –28.5 31 0.8 –139 –166 27.5 0.5 –55 –50 –55 –50 10 30 1.4 Parallel resistor Parallel capacitor Z0 = 50 Ω (9) See (specified by design) (10) dBm dB dB dBm/Hz 1.2 –135 –162 29.5 dBm OIP3 Output IP3 CS SBS HD2 HD3 τoff VCM ZBBin Γout Carrier leakage Side-band suppression Second harmonic level Third harmonic level TX turnoff time (6) –35 –35 dBm dB dBc dBc TX_PWD: low → high; TX_PWD = high 100 µs dB V kΩ pF TX off attenuation (7) Baseband input common-mode voltage (8) TX differential input impedance Output return loss Detector threshold Response time (1) (2) (3) (12) 10 0.1 –12 See See (11) (11) dB dB µs POWER ALARM DETECTOR (See the Power Alarm Detector section) See (11) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI (or TXBBQ) input level of –23 dBVrms No signal applied to TRF2443. This parameter is assured by characterization and is not production tested. Two tones of –26 dBVrms each at TXBBI and TXBBQ inputs at 5 MHz and 8 MHz; measured at transformer output (0.7-dB insertion loss). (4) Using internal common and dc offset control (5) TXIQ_PHASE set to 8; SPI-3, register 1, B (6) See the TX Output Power Ramp-Down section. (7) Attenuation of output level from TX on. (8) Common mode input is set internally. It is possible to disable internal bias through SPI and apply external common mode. (9) Single-ended, measured at transformer output (10) Delta output power level at TX fixed gain that forces detector output low (power alarm). (11) Detector threshold and response time are fully programmable by the user. (See the Power Alarm Detector section.) (12) If output power is lower than threshold for more than user-specified value, power-alarm detector output goes low. 10 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RF SYNTHESIZER CHARACTERISTICS VCC_3V = 3.3 V ±5%, TJ = 65°C (unless otherwise noted) PARAMETER TXVCO ftxvco ftxlo TXVCO frequency range TXLO frequency range See (1) TEST CONDITIONS MIN 2640 330 165 TYP MAX 2800 350 175 UNIT MHz MHz Divide-by-8 mode Divide-by-16 mode fout = 340 MHz; offset = 10 kHz fout = 340 MHz; offset = 100 kHz fout = 340 MHz; offset = 1 MHz fout = 340 MHz; offset = 20 MHz –92.5 –117.5 –140 –150 45 20 MHz/V MHz dBc/Hz TXLO free-running phase noise KvTX TXPLL fPFD TXVCO gain PFD frequency fout = 340 MHz; offset = 20 kHz TXLO closed-loop phase noise fout = 340 MHz; offset = 100 kHz fout = 340 MHz; offset = 1 MHz fout = 340 MHz; offset = 20 MHz Integrated TXLO noise Reference spur Lock time Integrated from 1 kHz to 12 MHz; fout = 340 MHz Measured at TXLOTEST (2720 MHz) From unlocked state to locked state (includes digital-calibration time) (3) fout = 165 MHz; offset = 20 kHz TXLO closed-loop phase noise fout = 165 MHz; offset = 100 kHz fout = 165 MHz; offset = 1 MHz fout = 165 MHz; offset = 20 MHz TJ = 65°C See (1) (2) –117 –116 –140 –150 –56.5 –70 300 –121 –120 –141 –147 2.8 2240 280 140 –97.5 –122.5 –146 –150 45 20 MHz/V MHz dB dBc/Hz 2640 330 165 V MHz MHz dBc/Hz dB dBc µs dBc/Hz Vccmin RXVCO frxvco frxlo PLL-lock minimum power supply RXVCO frequency range RXLO frequency range Divide-by-8 mode Divide-by-16 mode fout = 140 MHz; offset = 10 kHz fout = 140 MHz; offset = 100 kHz fout = 140 MHz; offset = 1 MHz fout = 140 MHz; offset = 20 MHz RXLO free-running phase noise KvRX RXPLL fPFD RXVCO gain PFD frequency Integrated RXLO noise Integrated from 1 kHz to 12 MHz; fout = 140 MHz fout = 140 MHz; offset = 20 kHz RXLO closed-loop phase noise fout = 140 MHz; offset = 100 kHz fout = 140 MHz; offset = 1 MHz fout = 140 MHz; offset = 20 MHz Reference spur Lock time Measured at RXLOTEST (2240 MHz) From unlock state to lock state (includes digital-calibration time) (3) (2) –62 –60 –122 –121 –146 –150 –65 300 Integrated from 1 kHz to 12 MHz; fout = 160 MHz (2) dBc/Hz dBc µs (1) (2) (3) Frequency range proven locked with PFD frequency = 20 MHz Optimized for lowest integrated noise; see the Reference-Clock Characteristics table for recommended reference clock performance. Charge-pump current = 1 mA, PFD frequency = 20 MHz, loop filter optimized (see Application Schematic section) Submit Documentation Feedback Product Folder Link(s): TRF2443 11 Copyright © 2009, Texas Instruments Incorporated TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com REFERENCE-CLOCK CHARACTERISTICS VCC = 3.3 V PARAMETER fref Reference frequency Phase noise Reference-clock input level 1 kHz Floor REFIN pin, ac-coupled on board (internally dc-coupled) 0.8 TEST CONDITIONS MIN TYP 20 –135 –160 2 3 MAX UNIT MHz dBc/Hz VPP XPIC CHARACTERISTICS VCC_3V = 3.3 V ± 5%, TJ = 65°C (unless otherwise noted) PARAMETER From RX_IN to XPIC_OUT fin Pout NF OIP3 Γout GMAX GMIN GDRange NF IP3 Input frequency Output power Output power flatness Noise figure Output IP3 Output return loss Maximum gain (4) Minimum gain (4) Gain control slope Digital gain range Gain flatness Noise figure Input IP3 Image rejection Γin Input return loss Output common mode Baseband output load (1) (2) (3) (4) Parallel capacitor Parallel resistor Programmed via SPI Measured over 110 MHz to 170 MHz XPICBB_GAIN set to 2; total gain = 21 dB XPICBB_GAIN set to 2; total gain = 21 dB XPICBB_GAIN set to 2; total gain = 10 dB See RX Image Rejection section Z0 = 75 Ω, single-ended 1.5 15 1 –4 6 Pin = –32 dBm, LNA ATT set to 0 (1) From 110 MHz to 170 MHz LNA ATT set to 0, total gain = 20 dB Two tones of –16 dBm each at 136 MHz and 144 MHz (1) (2) (3) Z0 = 75 Ω, single-ended XPIC_AGC = 0.7 V and XPICBB_GAIN set to 2 XPIC_AGC = 0 V and XPICBB_GAIN set to 2 21 27 5 46 11 1 22 0 9.5 –40 –12 25 10 11.5 –14 140 –12 1 15 13 –12 22 –10 MHz dBm dB dB dBm dB dB dB dB/V dB dB dB dBm dB dB V pF kΩ TEST CONDITIONS MIN TYP MAX UNIT FROM XPIC_IN TO XPIC_BBI/Q RXAGC voltage to have RXBBI (or RXBBQ) output level = –17 dBVrms LNA ATT set to 0; total power gain = 20 dB Measured at XPIC_OUT balun output (75-Ω characteristic impedance) Measured from differential output (XPICBBIP/N or XPICBBQP/N) to XPICINN input balun 12 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G001 RX GAIN vs RX AGC VOLTAGE 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G002 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V RX AGC Voltage (mV) RX AGC Voltage (mV) Figure 4. RX INPUT IP3 vs RX GAIN 10 0 −10 RX Input IP3 (dBm) −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 G003 Figure 5. RX INPUT IP3 vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 10 0 −10 RX Input IP3 (dBm) −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 G004 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 6. RX NOISE FIGURE vs RX GAIN 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G005 Figure 7. RX NOISE FIGURE vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G006 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 8. Copyright © 2009, Texas Instruments Incorporated Figure 9. Submit Documentation Feedback Product Folder Link(s): TRF2443 13 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 3, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G007 RX GAIN vs RX AGC VOLTAGE 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G008 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V RX AGC Voltage (mV) RX AGC Voltage (mV) Figure 10. RX INPUT IP3 vs RX GAIN 10 0 −10 RX Input IP3 (dBm) −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 G009 Figure 11. RX INPUT IP3 vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C RX Input IP3 (dBm) 10 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 G010 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 12. RX NOISE FIGURE vs RX GAIN 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G011 Figure 13. RX NOISE FIGURE vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G012 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 14. 14 Submit Documentation Feedback Product Folder Link(s): TRF2443 Figure 15. Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 6, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE 100 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G013 RX GAIN vs RX AGC VOLTAGE 100 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G014 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V RX AGC Voltage (mV) RX AGC Voltage (mV) Figure 16. RX INPUT IP3 vs RX GAIN 10 0 −10 RX Input IP3 (dBm) −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 G015 Figure 17. RX INPUT IP3 vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C RX Input IP3 (dBm) 10 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 G016 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 18. RX NOISE FIGURE vs RX GAIN 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G017 Figure 19. RX NOISE FIGURE vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G018 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 20. Copyright © 2009, Texas Instruments Incorporated Figure 21. Submit Documentation Feedback Product Folder Link(s): TRF2443 15 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX GAIN vs RX AGC VOLTAGE 100 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G019 RX GAIN vs RX AGC VOLTAGE 100 90 80 70 RX Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G020 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V RX AGC Voltage (mV) RX AGC Voltage (mV) Figure 22. RX INPUT IP3 vs RX GAIN 10 0 −10 RX Input IP3 (dBm) −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 100 G021 Figure 23. RX INPUT IP3 vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 10 0 −10 RX Input IP3 (dBm) −20 −30 −40 −50 −60 −70 −80 −90 0 10 20 30 40 50 60 70 80 90 100 G022 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 24. RX NOISE FIGURE vs RX GAIN 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 G023 Figure 25. RX NOISE FIGURE vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 50 45 40 RX Noise Figure (dB) 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 G024 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 26. 16 Submit Documentation Feedback Product Folder Link(s): TRF2443 Figure 27. Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX LNA ATTENUATION vs LNA ATTENUATION SETTING 0 −2 RX LNA Attenuation (dB) −4 −6 −8 −10 −12 −14 −16 −18 −20 0 2 4 6 8 10 12 14 16 18 20 G037 RX LNA ATTENUATION vs LNA ATTENUATION SETTING 0 −2 RX LNA Attenuation (dB) −4 −6 −8 −10 −12 −14 −16 −18 −20 0 2 4 6 8 10 12 14 16 18 20 G038 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V LNA Attenuation Setting (SPI-3, REG2) LNA Attenuation Setting (SPI-3, REG2) Figure 28. RX LNA CUMULATIVE ATTENUATION ERROR vs LNA ATTENUATION SETTING RX LNA Cumulative Attenuation Error (dB) 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LNA Attenuation Setting (SPI-3, REG2) G086 Figure 29. RX LNA CUMULATIVE ATTENUATION ERROR vs LNA ATTENUATION SETTING RX LNA Cumulative Attenuation Error (dB) 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LNA Attenuation Setting (SPI-3, REG2) G087 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V Figure 30. RX BASEBAND GAIN vs RXBB GAIN SETTING 32 30 RX Baseband Gain (dB) 28 26 24 22 20 18 16 14 12 10 8 0 2 4 6 8 10 12 14 16 18 20 22 24 G039 Figure 31. RX BASEBAND GAIN vs RXBB GAIN SETTING 32 30 RX Baseband Gain (dB) 28 26 24 22 20 18 16 14 12 10 8 0 2 4 6 8 10 12 14 16 18 20 22 24 G040 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V RXBB Gain Setting (SPI-3, REG2) RXBB Gain Setting (SPI-3, REG2) Figure 32. Figure 33. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 17 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS (continued) fin= 140 MHz (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX BASEBAND CUMULATIVE GAIN ERROR vs RXBB GAIN SETTING RX Baseband Cumulative Gain Error (dB) TJ = 0°C TJ = 65°C TJ = 125°C RX Baseband Cumulative Gain Error (dB) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 0 2 4 6 8 10 12 14 16 18 20 22 24 G088 RX BASEBAND CUMULATIVE GAIN ERROR vs RXBB GAIN SETTING 3.0 2.5 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 0 2 4 6 8 10 12 14 16 18 20 22 24 G089 VCC = 3.1V VCC = 3.3V VCC = 3.5V RXBB Gain Setting (SPI-3, REG2) RXBB Gain Setting (SPI-3, REG2) Figure 34. Figure 35. 18 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER TYPICAL CHARACTERISTICS fin= 280 MHz, SAW_EN = 0, LNA_ATT = 0, baseband gain setting = 0, 3-dB pad enabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RXBBI GAIN vs RX AGC VOLTAGE 90 80 70 RXBBI Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G074 RXBBI GAIN vs RX AGC VOLTAGE 90 80 70 RXBBI Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G075 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V RX AGC Voltage (mV) RX AGC Voltage (mV) Figure 36. RXBBI INPUT IP3 vs RX GAIN 20 10 RXBBI Input IP3 (dBm) 0 −10 −20 −30 −40 −50 −60 −70 −80 0 10 20 30 40 50 60 70 80 90 G076 Figure 37. RXBBI INPUT IP3 vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 20 10 RXBBI Input IP3 (dBm) 0 −10 −20 −30 −40 −50 −60 −70 −80 0 10 20 30 40 50 60 70 80 90 G077 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 38. RXBBI NOISE FIGURE vs RX GAIN 50 45 RXBBI Noise Figure (dB) 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G078 Figure 39. RXBBI NOISE FIGURE vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 50 45 RXBBI Noise Figure (dB) 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G079 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 40. Copyright © 2009, Texas Instruments Incorporated Figure 41. Submit Documentation Feedback Product Folder Link(s): TRF2443 19 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER TYPICAL CHARACTERISTICS fin= 280 MHz, SAW_EN = 1, LNA_ATT = 0, baseband gain setting = 9, 3-dB pad disabled (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RXBBI GAIN vs RX AGC VOLTAGE 90 80 70 RXBBI Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G080 RXBBI GAIN vs RX AGC VOLTAGE 90 80 70 RXBBI Gain (dB) 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 1800 G081 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V RX AGC Voltage (mV) RX AGC Voltage (mV) Figure 42. RXBBI INPUT IP3 vs RX GAIN 20 10 RXBBI Input IP3 (dBm) 0 −10 −20 −30 −40 −50 −60 −70 −80 0 10 20 30 40 50 60 70 80 90 G082 Figure 43. RXBBI INPUT IP3 vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 20 10 RXBBI Input IP3 (dBm) 0 −10 −20 −30 −40 −50 −60 −70 −80 0 10 20 30 40 50 60 70 80 90 G083 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 44. RXBBI NOISE FIGURE vs RX GAIN 50 45 RXBBI Noise Figure (dB) 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G084 Figure 45. RXBBI NOISE FIGURE vs RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 50 45 RXBBI Noise Figure (dB) 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 G085 VCC = 3.1V VCC = 3.3V VCC = 3.5V RX Gain (dB) RX Gain (dB) Figure 46. 20 Submit Documentation Feedback Product Folder Link(s): TRF2443 Figure 47. Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) 0 −20 −40 −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 Frequency (MHz) 1 10 G055 RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −20 −40 −60 −80 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 Frequency (MHz) 1 10 G056 BW = 1.8MHz BW = 1.8MHz Figure 48. RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) 0 −20 −40 −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 Frequency (MHz) 1 10 G057 Figure 49. RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −20 −40 −60 −80 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 Frequency (MHz) 1 10 G058 BW = 2.3MHz BW = 2.3MHz Figure 50. RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) 0 −20 −40 −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 Frequency (MHz) 1 10 G059 Figure 51. RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −20 −40 −60 −80 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 Frequency (MHz) 1 10 G060 BW = 3.5MHz BW = 3.5MHz Figure 52. Figure 53. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 21 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (continued) (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) 0 −20 −40 −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 Frequency (MHz) 1 10 G061 RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −20 −40 −60 −80 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 Frequency (MHz) 1 10 G062 BW = 4.5MHz BW = 4.5MHz Figure 54. RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) 0 −20 −40 −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 Frequency (MHz) 1 10 G063 Figure 55. RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −20 −40 −60 −80 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 Frequency (MHz) 1 10 G064 BW = 8.5MHz BW = 8.5MHz Figure 56. RX LOW-PASS FILTER REJECTION vs FREQUENCY RX Low-Pass Filter Rejection (dB) RX Low-Pass Filter Rejection (dB) 0 −20 −40 −60 −80 −100 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 Frequency (MHz) 1 10 G065 Figure 57. RX LOW-PASS FILTER REJECTION vs FREQUENCY 0 −20 −40 −60 −80 −100 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 Frequency (MHz) 1 10 G066 BW = 9MHz BW = 9MHz Figure 58. Figure 59. 22 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECEIVER LOW-PASS FILTER TYPICAL CHARACTERISTICS (continued) (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) RX LOW-PASS FILTER REJECTION vs FREQUENCY 0.5 RX Low-Pass Filter Rejection (dB) 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 0.01 TJ = 0°C TJ = 65°C TJ = 125°C 0.1 Frequency (MHz) 1 10 G092 RX LOW-PASS FILTER REJECTION vs FREQUENCY 0.5 RX Low-Pass Filter Rejection (dB) 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 0.01 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 Frequency (MHz) 1 10 G093 BW = 3.5MHz BW = 3.5MHz Figure 60. Figure 61. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 23 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TRANSMITTER TYPICAL CHARACTERISTICS Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX OUTPUT POWER vs TX ATTENUATION SETTING 10 5 TX Output Power (dBm) 0 −5 −10 −15 −20 −25 −30 −35 0 fOUT = 340MHz 5 10 15 20 25 30 35 G041 TX OUTPUT POWER vs TX ATTENUATION SETTING 10 5 TX Output Power (dBm) 0 −5 −10 −15 −20 −25 −30 −35 0 fOUT = 340MHz 5 10 15 20 25 30 35 G042 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 62. TX GAIN vs TX ATTENUATION SETTING 25 20 15 TX Gain (dB) 10 5 0 −5 −10 −15 −20 0 fOUT = 340MHz 5 10 15 20 25 30 35 G043 Figure 63. TX GAIN vs TX ATTENUATION SETTING 25 20 15 TX Gain (dB) 10 5 0 −5 −10 −15 −20 0 fOUT = 340MHz 5 10 15 20 25 30 35 G044 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 64. TX 0.5-dB GAIN STEP vs TX ATTENUATION SETTING 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 TJ = 0°C TJ = 65°C TJ = 125°C 5 10 15 20 Figure 65. TX 0.5-dB GAIN STEP vs TX ATTENUATION SETTING 0.8 0.7 0.6 0.5 0.4 0.3 0.2 35 G047 TX 0.5-dB Gain Step (dB) TX 0.5-dB Gain Step (dB) fOUT = 340MHz 25 30 VCC = 3.1V VCC = 3.3V VCC = 3.5V 0 5 10 15 20 fOUT = 340MHz 25 30 35 G048 TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 66. 24 Submit Documentation Feedback Product Folder Link(s): TRF2443 Figure 67. Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TRANSMITTER TYPICAL CHARACTERISTICS (continued) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX 1-dB GAIN STEP vs TX ATTENUATION SETTING 1.5 1.4 TX 1-dB Gain Step (dB) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 5 10 15 20 25 30 35 G049 TX 1-dB GAIN STEP vs TX ATTENUATION SETTING 1.5 1.4 TX 1-dB Gain Step (dB) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 5 10 15 20 25 30 35 G050 TJ = 0°C TJ = 65°C TJ = 125°C fOUT = 340MHz VCC = 3.1V VCC = 3.3V VCC = 3.5V fOUT = 340MHz TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 68. TX CUMULATIVE GAIN ERROR vs TX ATTENUATION SETTING 0.5 TX Cumulative Gain Error (dB) 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 5 10 15 20 25 30 35 G090 Figure 69. TX CUMULATIVE GAIN ERROR vs TX ATTENUATION SETTING 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 5 10 15 20 25 30 35 G091 TX Cumulative Gain Error (dB) TJ = 0°C TJ = 65°C TJ = 125°C fOUT = 340MHz VCC = 3.1V VCC = 3.3V VCC = 3.5V fOUT = 340MHz TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 70. UNCALIBRATED TX SIDEBAND SUPPRESSION vs TX ATTENUATION SETTING TJ = 0°C TJ = 65°C TJ = 125°C Figure 71. UNCALIBRATED TX SIDEBAND SUPPRESSION vs TX ATTENUATION SETTING Uncalibrated TX Sideband Suppression (dB) 60 55 50 45 40 35 30 0 5 10 15 20 25 30 35 G052 Uncalibrated TX Sideband Suppression (dB) 60 55 50 45 40 35 30 0 fOUT = 340MHz VCC = 3.1V VCC = 3.3V VCC = 3.5V fOUT = 340MHz 5 10 15 20 25 30 35 G051 TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 72. Copyright © 2009, Texas Instruments Incorporated Figure 73. Submit Documentation Feedback Product Folder Link(s): TRF2443 25 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TRANSMITTER TYPICAL CHARACTERISTICS (continued) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX CARRIER LEAKAGE vs TX ATTENUATION SETTING −40 −50 −60 −70 −80 −90 −100 0 fOUT = 340MHz 5 10 15 20 25 30 35 G094 TX CARRIER LEAKAGE vs TX ATTENUATION SETTING −40 −50 −60 −70 −80 −90 −100 0 fOUT = 340MHz 5 10 15 20 25 30 35 G095 TX Carrier Leakage (dBm) TX Attenuation Setting (SPI-3, REG1) TX Carrier Leakage (dBm) TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V TX Attenuation Setting (SPI-3, REG1) Figure 74. TX OUTPUT IP3 vs TX ATTENUATION SETTING 35 30 TX Output IP3 (dBm) 25 20 15 10 5 0 0 fOUT = 340MHz 5 10 15 20 25 30 35 G053 Figure 75. TX OUTPUT IP3 vs TX ATTENUATION SETTING 35 30 TX Output IP3 (dBm) 25 20 15 10 5 0 0 fOUT = 340MHz 5 10 15 20 25 30 35 G054 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 76. TX IM3 vs TX ATTENUATION SETTING 80 75 70 TX IM3 (dBc) TX IM3 (dBc) 65 60 55 50 45 40 0 TJ = 0°C TJ = 65°C TJ = 125°C 5 10 15 20 80 75 70 65 60 55 50 45 fOUT = 340MHz 25 30 35 G072 Figure 77. TX IM3 vs TX ATTENUATION SETTING 40 0 VCC = 3.1V VCC = 3.3V VCC = 3.5V 5 10 15 20 fOUT = 340MHz 25 30 35 G073 TX Attenuation Setting (SPI-3, REG1) TX Attenuation Setting (SPI-3, REG1) Figure 78. 26 Submit Documentation Feedback Product Folder Link(s): TRF2443 Figure 79. Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TRANSMITTER TYPICAL CHARACTERISTICS (continued) Measured after the transformer (0.7-dB insertion loss) and with a TXBBI/TXBBQ input level of –23 dBVrms (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX PROGRAMMABLE POWER-SHUTDOWN vs TIME 10 0 TX Output Power (dBm) −10 −20 −30 −40 −50 −60 −70 SPI-3 REG3= −80 0 10 20 30 40 50 60 70 80 90 100 G067 TX PROGRAMMABLE POWER-SHUTDOWN vs TIME 10 0 TX Output Power (dBm) −10 −20 −30 −40 −50 −60 −70 SPI-3 REG3= −80 0 10 20 30 40 50 60 70 80 90 100 G068 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V Time (µs) Time (µs) Figure 80. TX OUTPUT NOISE vs TX ATTENUATION SETTING −120 −125 TX Output Noise (dBm/Hz) −130 −135 −140 −145 −150 −155 −160 −165 −170 0 5 10 15 20 25 30 G069 Figure 81. VCC = 3.1V VCC = 3.3V VCC = 3.5V Note: No Input Signal TX Attenuation Setting (SPI-3, REG1) Figure 82. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 27 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com PLL TYPICAL CHARACTERISTICS Measured at TXLOTEST pin (6) and RXLOTEST pin (53). Charge-pump current = 1 mA, PFD frequency = 20 MHz, loop filter optimized (see Application Schematic section). (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) TX VCO PHASE NOISE −90 −100 Phase Noise (dBc/Hz) −110 −120 −130 −140 −150 −160 0.01 BW = 2720MHz TJ = 0°C TJ = 65°C TJ = 125°C −90 −100 Phase Noise (dBc/Hz) −110 −120 −130 −140 −150 −160 0.01 BW = 2720MHz VCC = 3.1V VCC = 3.3V VCC = 3.5V TX VCO PHASE NOISE 0.1 1 Frequency Offset (MHz) 10 100 G096 0.1 1 Frequency Offset (MHz) 10 100 G097 Figure 83. RX VCO PHASE NOISE −90 −100 Phase Noise (dBc/Hz) −110 −120 −130 −140 −150 −160 0.01 BW = 2240MHz TJ = 0°C TJ = 65°C TJ = 125°C −90 −100 Phase Noise (dBc/Hz) −110 −120 −130 −140 −150 −160 0.01 BW = 2240MHz Figure 84. RX VCO PHASE NOISE VCC = 3.1V VCC = 3.3V VCC = 3.5V 0.1 1 Frequency Offset (MHz) 10 100 G098 0.1 1 Frequency Offset (MHz) 10 100 G099 Figure 85. Figure 86. 28 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 XPIC RECEIVER TYPICAL CHARACTERISTICS fin= 140 MHz, XPIC baseband gain setting = 2 (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) XPIC RX GAIN vs XPIC AGC VOLTAGE 30 25 XPIC RX Gain (dB) 20 15 10 5 0 0 100 200 300 400 500 600 700 G025 XPIC RX GAIN vs XPIC AGC VOLTAGE 30 25 XPIC RX Gain (dB) 20 15 10 5 0 0 100 200 300 400 500 600 700 G026 TJ = 0°C TJ = 65°C TJ = 125°C VCC = 3.1V VCC = 3.3V VCC = 3.5V XPIC AGC Voltage (mV) XPIC AGC Voltage (mV) Figure 87. XPIC RX INPUT IP3 vs XPIC RX GAIN 14 12 XPIC RX Input IP3 (dBm) 10 8 6 4 2 0 −2 −4 0 5 10 15 20 25 30 G027 Figure 88. XPIC RX INPUT IP3 vs XPIC RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 14 12 XPIC RX Input IP3 (dBm) 10 8 6 4 2 0 −2 −4 0 5 10 15 20 25 30 G028 VCC = 3.1V VCC = 3.3V VCC = 3.5V XPIC RX Gain (dB) XPIC RX Gain (dB) Figure 89. XPIC RX NOISE FIGURE vs XPIC RX GAIN 50 45 XPIC RX Noise Figure (dB) 40 35 30 25 20 15 10 0 5 10 15 20 25 30 G029 Figure 90. XPIC RX NOISE FIGURE vs XPIC RX GAIN TJ = 0°C TJ = 65°C TJ = 125°C 50 45 XPIC RX Noise Figure (dB) 40 35 30 25 20 15 10 0 5 10 15 20 25 30 G030 VCC = 3.1V VCC = 3.3V VCC = 3.5V XPIC RX Gain (dB) XPIC RX Gain (dB) Figure 91. Figure 92. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 29 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com INSERTION LOSSES TYPICAL CHARACTERISTICS Measured after transformers (see Application Schematic section). (TJ = 65°C, VCC = 3.3 V, unless otherwise noted) INPUT RETURN LOSS XPICIN −10 OUTPUT RETURN LOSS XPICOUT −10 Output Return Loss XPICOUT (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V Input Return Loss XPICIN (dB) −15 VCC = 3.1V VCC = 3.3V VCC = 3.5V −15 −20 −20 −25 −25 −30 −30 −35 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) G031 −35 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) G032 Figure 93. INPUT RETURN LOSS IFIN −10 Figure 94. OUTPUT RETURN LOSS IFOUT −10 Output Return Loss IFOUT (dB) VCC = 3.1V VCC = 3.3V VCC = 3.5V Input Return Loss IFIN (dB) −15 VCC = 3.1V VCC = 3.3V VCC = 3.5V −15 −20 −20 −25 −25 −30 −30 −35 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) G033 −35 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) G034 Figure 95. INPUT RETURN LOSS RXIN vs LNA_ATT −10 Output Return Loss TXOUT (dB) LNA_ATTN = 0 LAN_ATTN = 3 LNA_ATTN = 6 LAN_ATTN = 9 Figure 96. OUTPUT RETURN LOSS TXOUT 0 −5 −10 −15 −20 −25 −30 −35 300 VCC = 3.1V VCC = 3.3V VCC = 3.5V Input Return Loss RXIN (dB) −15 −20 −25 −30 −35 −40 90 100 110 120 130 140 150 160 170 180 190 Frequency (MHz) G035 LNA_ATTN = 12 LAN_ATTN = 15 LNA_ATTN = 18 310 320 330 340 350 360 370 380 G036 Frequency (MHz) Figure 97. Figure 98. 30 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 SPI REGISTERS The TRF2443 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift register. There are a total of three signals that must be applied: the clock (CLKSPI), the serial data (DATASPI) and the latch enable (LESPI). The TRF2443 has an additional pin (RDBKSPI) for readback functionality. This pin is a digital pin and can be used to read back values of different internal registers. The DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of the CLOCK. The latch enable is asynchronous to the CLOCK, and at its rising edge the data in the shift register is loaded onto the selected internal register. The 5 LSBs of the data field are the address bits to select the available internal registers (see Figure 99). The SPI can operate reliably at clock speeds up to 20 MHz (clock period = td V1 = HIGH PWRDET = HIGH V1 = LOW V1 = HIGH PRE-ALARM MODE PWRDET = HIGH TIME COUNTER STARTS TIME COUNTER < td V1 = LOW COUNTER ? V1 ? Figure 107. TX Power-Alarm Flow Chart Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 61 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com TX OUTPUT POWER RAMP-DOWN To avoid unwanted spurious emissions during power down of the transmitter, the power-down circuitry is designed to ramp down the output power gradually. The ramp-down time constant is programmable. PS_TC (SPI-3, register 3, B) allows selection of four different time constants. PS_TC 00 01 10 11 POWER DOWN 28 µs 42 µs 57 µs 75 µs The values shown in the preceding table are the typical times required for the output level to be attenuated by 30 dB. LOOPBACK The TRF2443 integrates a loopback switch between the TX and the RX chains. The switch connects the TX modulator output to the RX IFVGA3 input. This path can be used for three different functions: • Loopback path for the transmitted signal • RX baseband low-pass-filter corner-frequency calibration • TX modulator LO leakage calibration The loopback mode is enabled by setting EN_LB (SPI-3, register 1, B) to 1. When the switch is activated, the TX amplifier, RX LNA, RX IFVGA1, and RX IFVGA2 are all turned off automatically. The loopback path can be programmed with two different insertion losses: • 20-dB insertion loss for the loopback path of the transmitted signal • Minimum insertion loss for calibration mode The attenuation mode is selected via EN_LB_ATT (SPI-3, register 1, B). EN_LB_ATT = 1 → 20-dB attenuation EN_LB_ATT = 0 → minimum insertion loss TX Signal Loopback The TRF2443 internal feedback path can be used to loop back the TX signal (1), which enables the RX chain to be used to monitor the transmitted signal. This mode is controlled via the serial programming interface (SPI) according the following possible steps: 1. Enable loopback switch with 20-dB attenuation a. EN_LB_ATT = 1 (SPI-3, register 1, B) b. EN_LB = 1 (SPI-3, register 1, B) 2. Program TXLO to 165 MHz (TXLO to 2640 MHz and TX divider to 16) a. TXRDIV = (SPI-1, register 1, B) [R = 1] b. TX_NINT = (SPI-1, register 2, B) [N = 66] c. TXDIV_SEL = 0 (SPI-1, register 2, B) [LO divider set to 16] 3. Program RXLO to 165 MHz (RXLO to 2640 MHz and RX divider to 16) a. RXRDIV = (SPI-2, register 1, B) [R = 1] b. RX_NINT = (SPI-2, register 2, B) [N = 132] c. RXDIV_SEL = 0 (SPI-2, register 2, B) [LO divider set to 16] 4. Set receiver baseband gain to 10 dB a. RXBB_GAIN = (SPI-3, register 2, B) 5. Program the receiver baseband-filter cutoff frequency to the appropriate value (depending on the TX signal bandwidth). (1) 62 For a TX loopback frequency of 165 MHz, the PLLs are locked to a 20-MHz PFD frequency. Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Baseband-Filter Cutoff-Frequency Calibration The TRF2443 internal feedback path can be used to set up an automatic calibration of the RX baseband-filter cutoff frequency. The procedure to calibrate the corner frequency to 3 MHz is described as follows. 1. Enable loopback switch with minimum insertion loss. a. EN_LB_ATT = 0 (SPI-3, register 1, B) b. EN_LB = 1 (SPI-3, register 1, B) 2. Program RXLO to 165 MHz (RXLO to 2640 MHz and RX divider to 16). a. RXRDIV = (SPI-2, register 1, B) [R = 1] b. RX_NINT = (SPI-2, register 2, B) [N = 132] c. RXDIV_SEL = 0 (SPI-2, register 2, B) [LO divider set to 16] 3. Set TXVCO divider to 16. a. TXDIV_SEL = 0 (SPI-1, register 2, B) [LO divider set to 16] 4. Set the TXPLL PFD frequency to 4 MHz (R divider = 5). a. TXRDIV = (SPI-1, register 1, B) [R = 5] 5. Apply a dc offset at the TRF2443 TX baseband inputs (to increase the TXLO leakage at the modulator output). 6. Set the RX baseband amplifier gain to 22 dB. a. RXBB_GAIN = (SPI-3, register 2, B) 7. Set the RX baseband cutoff-frequency bit controls RXBB_FREQ = 011 1000 (typical value for fC = 3 MHz) 8. Program the TXLO frequency to 166 MHz (TXVCO = 2656 MHz). a. TX_NINT = (SPI-1, register 2, B) [N = 332] 9. Measure the RX baseband output-power level (at I or Q output): Pout1. 10. Program the TXLO frequency to 168 MHz (TXVCO = 2688 MHz). a. TX_NINT = (SPI-1, register 2, B) [N = 336] 11. Measure the RX baseband output power level (Pout2) and calculate attenuation: Att = Pout1 – Pout2. 12. If Att < 3 dB, then increase RXBB_FREQ and go back to 11); else if Att > 3 dB, then reduce RXBB_FREQ and go back to 11). This is repeated until two sequential iterations result in the calculated attenuation being above and below 3 dB. When this is observed, save the RXBB_FREQ value which results in an attenuation value closer to 3 dB. The TRF2443 baseband low-pass filter cutoff frequency can be programmed to any of 128 cutoff frequencies. The cutoff frequency control consists of 7 bits, RXBB_FREQ, which are located in SPI-3, register 2, B. RXBB_FREQ = corresponds to the minimum corner frequency. Figure 108 shows the 3-dB bandwidth of the filter versus all possible SPI codes for a typical unit. Figure 109 shows the inverse of the 3-dB bandwidth versus all possible SPI codes for a typical unit. 16 14 12 10 8 RXBB I 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 LPF BW Adj (dec) G070 0.7 0.6 RXBB Filter 1/BW 0.5 0.4 0.3 0.2 0.1 0.0 0 10 20 30 40 50 60 70 80 90 100 110 120 LPF BW Adj (dec) G071 RXBB Q RXBB Filter BW RXBB I RXBB Q Figure 108. BW vs SPI Code (RXBB_FREQ Figure 109. 1/BW vs SPI Code (RXBB_FREQ Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF2443 63 TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com Because the corner frequency is dependent on the on-chip capacitance, it is possible to observe variations from unit to unit in the SPI code that yields a fixed corner frequency. Variations in capacitance from unit to unit result in a unique 1/BW curve for each unit. If the same DUT is to be used at multiple corner frequencies, the user should calibrate the DUT as described above to determine, at a minimum, 2 points on the 1/BW curve. From these calibrated points, any other corner frequency can be extrapolated using linear regression. TX LO Leakage Calibration The TRF2443 internal feedback path can be used to set up an automatic calibration of the TX LO leakage according the following potential procedure: 1. Enable loopback switch with minimum insertion loss. a. EN_LB_ATT = 0 (SPI-3, register 1, B) b. EN_LB = 1 (SPI-3, register 1, B) 2. Set RXLO = 330 MHz (RXVCO to 2640 MHz and RX divider to 8) a. RXRDIV = (SPI-2, register 1, B) [R = 1] b. RX_NINT = (SPI-2, register 2, B) [N = 132] c. RXDIV_SEL = 1 (SPI-2, register 2, B) [LO divider set to 8] 3. Set RX baseband in filter bypass mode and gain = 22 dB a. RXBB_GAIN = (SPI-3, register 2, B) [gain = 22 dB] b. RXBB_FLT_BYP = 1 (SPI-3, register 2, B) [bypass filter] 4. Program TX LO in normal mode (TXLO = 340 MHz). a. TXRDIV = (SPI-1, register 1, B) [R = 1] b. TX_NINT = (SPI-1, register 2, B) [N = 68] c. TXDIV_SEL = 1 (SPI-1, register 2, B) [LO divider set to 8] 5. Measure power level at RXBB output at 10 MHz = P1. 6. Change TX input dc offset until minimum P1 is achieved. The TRF2443 TX baseband inputs can be ac- or dc-coupled to the external digital-to-analog converter (DAC). In case of direct coupling, the DAC must provide the appropriate dc offset of step 6 to null the LO leakage. If an ac-coupled approach is selected, then the internal bias must be enabled by setting EN_TXCM = 1 (SPI-3, register 3, B). In this case, the integrated dc DAC controls the baseband dc offset. The internal DAC is programmed via the SPI. TXBBI (SPI-3, register 3, B) and TXBBQ (SPI-3, register 3, B) control the internal DAC settings. TXBBI = TXBBQ = corresponds to midrange, that is, no offset applied. RX IMAGE REJECTION The TRF2443 has been designed to provide optimal image rejection. Using symmetry in the design of the I and Q paths of the receiver ensures that mismatch between the I and Q paths is minimized. Image rejection is a function of the amplitude (A) mismatch and the phase error (Φ) from 90 degrees of the I and Q RX baseband signals. Image rejection is calculated in the following manner: é A 2 - 2Acosf + 1ù Rejection(dB) = 10log ê 2 ú ê A + 2Acosf + 1ú ë û DC-OFFSET CALIBRATION The TRF2443 provides an automatic calibration procedure for adjusting the dc offset in the receiver and XPIC baseband I/Q paths. The internal calibration requires a clock in order to function. This clock is derived internally from the reference clock with a frequency divider, whose divider ratio is programmable. DCOFF_CLK (SPI-3, register 5, B) and XDCOFF_CLK (SPI-3, register 5, B) set the division ratio for the dc-offset correction-loop clock for the receiver and XPIC chains, respectively. The output full-scale range of the internal dc-offset-correction DAC is programmable using bits DCOFF_BIAS (SPI-3, register 5, B) for the receiver chain and XPICDCOFF_BIAS (SPI-3, register 5, B) for the XPIC chain. The range is shown in Table 11. 64 Submit Documentation Feedback Product Folder Link(s): TRF2443 Copyright © 2009, Texas Instruments Incorporated TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Table 11. DC Offset Correction DAC Programmable Range DCOFF_BIAS _B1 XPICDCOFF_BIAS _B1 0 0 1 1 DCOFF_BIAS _B0 XPICDCOFF_BIAS _B0 0 1 0 1 FULL SCALE 10 mV 20 mV 30 mV 40 mV The I- and Q-channel output maximum dc-offset correction range can be calculated by multiplying the values in Table 11 by the baseband PGA gain. The LSB of the digital correction is dependent on the programmed maximum correction range. The dc offset correction DAC output is affected by a change in the PGA gain, but if the initial calibration yields optimum results, then the adjustment of the PGA gain during normal operation does not significantly impair the dc offset balance. The dc offset correction DACs are programmed from the internal registers when the RXBB_CALSELECT bit (SPI-3, register 7, B) is set to 1 (default value at power on). At start-up, the internal registers are loaded at half-scale, corresponding to a decimal value of 128. The autocalibration for the receiver chain is initiated by setting the EN_BB_AUTOCAL bit (SPI-3, register 5, B) to 1. When the calibration is over, this bit is automatically reset to 0. Similarly for the XPIC, by programming EN_XPIC_AUTOCAL (SPI-3, register 5, B) to 1, the baseband dc-offset calibration starts. During calibration, the RX local oscillator must be on. At each clock cycle during an autocalibration sequence, the internal circuitry senses the output dc offset and calculates the new dc current for the DAC. After the 13th clock cycle, the calibration is complete and the EN_BB_AUTOCAL (or EN_XPIC_AUTOCAL) bit is reset to 0. The dc-offset DAC state is stored in the internal registers and maintained as long as the power supply is kept on or until a new calibration is started. The required clock speed for the optimum calibration is determined by the internal detector behavior (integration bandwidth, gain, sensitivity). The speed of the clock can be slowed down by selecting a clock divider ratio DCOFF_CLK (SPI-3, register 5, B) and/or XDCOFF_CLK (SPI-3, register 5, B). The detector has more averaging time the slower the clock; hence, it can be desirable to slow down the clock speed for a given condition to achieve optimum results. The internal registers controlling the internal dc current DAC for the receiver chain are accessible through the SPI (SPI-3, register 7, B), providing a user-programmable method for implementing the dc-offset calibration. To employ this option, the RXBB_CALSELECT (SPI-3, register 7, B) bit must be set to 0. During this calibration, an external instrument monitors the output dc offset between the I/Q differential outputs and programs the internal registers RXBBI_DCOFF (SPI-3, register 7, B

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