XC61H

XC61H Series Voltage Detector with Delay Circuit Built-In ETR0212-002 ■GENERAL DESCRIPTION The XC61H series is a highly accurate, low power consumption CMOS voltage detector with a delay circuit. Detect voltage is accurate with minimal temperature drift. Output configurations are available in both CMOS and N-channel open drain. Since the full delay circuit is built-in, an external delay-time capacitor is not necessary so that high density mounting is possible. ■APPLICATIONS ●Microprocessor reset circuitry ●System battery life and charge voltage monitors ●Memory battery back-up circuits ●Power-on reset circuits ●Power failure detection ●Delay circuitry ■FEATURES Detect Voltage Accuracy : ± 2% (*) Low Power Consumption : 1.0μA(TYP.)[ VIN=2.0V ] : 1.6V ~ 6.0V (0.1V increments) Detect Voltage Range Operating Voltage Range : 0.7V ~ 10.0V Detect Voltage Temperature Characteristics :±100ppm/℃(TYP.) Built-In Release Delay time : ①1ms (MIN.) ②50ms (MIN.) ③80ms (MIN.) Output Configuration : N-ch open drain or CMOS Package : SOT-23 * No parts are available with an accuracy of ± 1% ■TYPICAL APPLICATION CIRCUITS ■TYPICAL PERFORMANCE CHARACTERISTICS μP V IN R pull ●Release Delay Time (tDR) vs. Ambient Temperature ＸＣ６１ＨＣ３０１２ Release Delay Time: tDR(ms) RESETB 2 VIN 3 VSS 1 RESETB INPUT V SS XC61HN series Not necessary with CMOS output products Ambient Temperature: Ta (℃) 1/13 XC61H Series ■PIN CONFIGURATION （TOP VIEW） ■PIN ASSIGNMENT PIN NUMBER SOT-23 1 2 3 PIN NAME VSS FUNCTION Ground Output Supply Voltage Input RESETB VIN 2/13 XC61H Series ■PRODUCT CLASSIFICATION ●Ordering Information XC61H ①②③④⑤⑥⑦-⑧ DESIGNATOR ① ②③ ④ ⑤ ⑥⑦-⑧ (*1) (*2) (*1) DESCRIPTION Output Configuration Detect Voltage (VDF) Release Delay Time Detect Accuracy Packages Taping Type (*2) SYMBOL C N 16 ~ 60 1 4 5 2 MR-G CMOS output DESCRIPTION N-ch open drain output e.g. 2.5V → ②2 , ③5 50ms ~ 200ms 80ms ~ 400ms 1ms ~ 50ms ± 2.0% SOT-23 (Halogen & Antimony free) The ”-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant. The device orientation is fixed in its embossed tape pocket. For reverse orientation, please contact your local Torex sales office or representative. (Standard orientation: ⑥R-⑧, Reverse orientation: ⑥L-⑧) ■BLOCK DIAGRAMS (1)CMOS output (2)N-ch open drain output 3/13 XC61H Series ■ABSOLUTE MAXIMUM RATINGS PARAMETER Input Voltage Output Current CMOS Output Voltage N-ch open drain Power Dissipation SOT-23 Operating Temperature Range Storage Temperature Range SYMBOL VIN IOUT RESTB Pd Topr Tstg RATINGS 12.0 50 VSS-0.3 ~VIN+0.3 VSS -0.3 ~ 12 250 -30∼+80 -40∼+125 Ta=25℃ UNITS V mA V mW ℃ ℃ ■ELECTRICAL CHARACTERISTICS PARAMETER Detect Voltage Hysteresis Width SYMBOL VDF VHYS VIN = 1.5V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VDF=1.6V∼6.0V VIN = 1.0V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VIN = 8.0V ILEAK Nch Open Drain Detect Voltage Temperature Characteristics Release Delay Time (VDR → RESEB inversion) ΔVDF ΔTopr･VDF tDR VIN changes from 0.6V to 10V VIN=10.0V, VOUT=10.0V 50 80 1 0.01 ±100 0.1 200 400 50 ppm/℃ ms CONDITIONS MIN. VDF(T) x 0.98 VDF x 0.02 0.7 1.0 3.0 5.0 6.0 7.0 TYP. VDF(T) VDF x 0.05 0.9 1.0 1.3 1.6 2.0 2.2 7.7 10.1 11.5 13.0 -10.0 0.01 MAX. VDF(T) x 1.02 VDF x 0.08 2.6 3.0 3.4 3.8 4.2 10.0 -2.0 μA UNITS V V Ta = 25℃ CIRCUIT ① ① Supply Current (*1) ISS μA ② Operating Voltage VIN V ① Output Current IOUT N-ch, VDS = 0.5V mA ③ P-ch, VDS=2.1V (CMOS Output) Leakage Current CMOS Output ④ ③ - ⑤ VDF (T) is nominal detect voltage value Release Voltage: VDR = VDF + VHYS (*1) The supply current during power-start until output being stable (during release operation) is 2μA greater with comparison to the period after the completion of release operation because of the shoot-through current in delay current. 4/13 XC61H Series ■OPERATIONAL EXPLANATION ●CMOS output An input voltage VIN starts higher than the release voltage VDR. Then, VIN voltage will gradually fall. When VIN voltage is higher than detect voltage VDF, output voltage RESETB is equal to the VIN voltage. *Note that high impedance exists at RESETB with the N-channel open drain configuration. If the RESETB pin is pulled up, RESETB will be equal to the pull up voltage. ② When VIN falls below VDF, RESETB will be equal to ground voltage VSS level (detect state). * Note that this also applies to N-channel open drain configurations. ③ When VIN falls to a level below that of the minimum operating voltage VMIN, output will become unstable. *When the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage. ④ When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), RESETB will be equal to VSS until VIN reaches the VDR level. ⑤ Although VIN will rise to a level higher than VDR, RESETB maintains ground voltage level via the delay circuit. ⑥ After taking a release delay time, VIN voltage will be output at the RESETB pin. *High impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up. ① Notes: 1. The difference between VDR and VDF represents the hysteresis width. 2. Release delay time (tDR) represents the time it takes until when VIN voltage appears at RESETB pin once the input voltage has exceeded the VDR level. ●Timing Chart Output Voltage (RESETB) Release Delay Time (tDR) 5/13 XC61H Series ■NOTES ON USE 1. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded. 2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irregular oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be added. (refer to Figure 1 below) 3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch output configurations, oscillation may occur as a result of shoot-through current at the time of voltage release even if load current (IOUT) does not exist. (refer to Figure 1 below) 4. By connecting a resistor between the VIN pin and the input, detect and release voltages will rise as a result of the IC's supply current flowing through the VIN pin. 5. If a resistor (RIN) must be used, then please use with as small a level of input impedance as possible in order to control the occurrences of oscillation as described above. Further, please ensure that RIN is less than 10kΩ and that CIN is more than 0.1μF (Figure 1). In such cases, detect and release voltages will rise due to voltage drops at RIN brought about by the IC's supply current. 6. Depending on circuit's operation, release delay time of this IC can be widely changed due to upper limits or lower limits of operational ambient temperature. ●Irregular Oscillations (1) Irregular oscillation as a result of output current with the CMOS output configuration: When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow through RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Irregular oscillation may occur with this "release - detect - release" repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Irregular oscillation as a result of shoot-through current: Since the XC61H series are CMOS ICS, shoot-through current will flow when the IC's internal circuit switching operates (during release and detect operations). Consequently, irregular oscillation is liable to occur during release voltage operations as a result of output current which is influenced by this shoot-through current (Figure 3). Since hysteresis exists during detect operations, irregular oscillation is unlikely to occur. XC61HN Series XC61HC Series Fi図 1．入力抵抗を入れた時の回路例 gure 1 Use of input resistor RIN 6/13 XC61H Series ■NOTES ON USE ●Irregular Oscillations (Continued) ＸＣ６１HＣシリーズ XC61HC Series ＲＩＮ ＲＩＮ×ＩOUT Voltage drop 電圧降下 ＩOUT VIN RESETB VSS ＲL 図 2．出力電流による発振 Figure 2 Irregular Oscillation by output current XＸＣ６１HＣシリーズ C61HC Series XC61HN Series ＸＣ６１HNシリーズ Ｒ ＩＮ ＲＩＮ×Ｉ SS * Voltage drop 電圧降下 VIN RESETB VSS Ｉ SS * (Includes shoot-through current) （貫通電流を含む） F図 3．貫通電流による発振 by shoot-through current igure 3 Irregular Oscillation 7/13 XC61H Series ■TEST CIRCUITS 測定回路１ ●Circuit ① 測定回路２ ●Circuit ② A VIN VIN V VSS RESETB *R 220kΩ V IN VIN RESETB V VSS 測定回路３ ③ ●Circuit 測定回路４ ④ ●Circuit VIN VIN RESETB VIN A V DS V IN RESETB VDS A VSS VSS 測定回路５ ●Circuit ⑤ VIN RESETB *R 220kΩ measurement of waveform VSS *R is not necessary with CMOS output products. 8/13 XC61H Series ■TYPICAL PERFORMANCE CHARACTERISTICS XC61HN1612 XC61HN2512 XC61HN3512 VDF,VDR (V) XC61HN1612 XC61HN2512 XC61HN3512 (3) Detect Voltage, Release Voltage vs. Input Voltage Detect, Release Voltage: VDF,VOUTV) 出力電圧 V DR ( (V) Detect, Release Voltage: VDF,VDR (V) XC61HN1612 R-pull:100kΩ Ta=-30℃ 25℃ 80℃ XC61HN2512 R-pull:100kΩ Ta=-30℃ 25℃ 80℃ Detect, Release Voltage: VDF,VDR (V) 出力電圧 VOUT (V) 検出電圧,解除電圧 XC61HN3512 R-pull:100kΩ Ta=-30℃ 25℃ 80℃ XC61HN1612 XC61HN1612 XC61HN2512 9/13 XC61H Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) XC61HN2512 XC61HN3512 XC61HN3512 XC61HN1612 XC61HN2512 XC61HN3512 XC61HC2712 XC61HC4412 （7）Ambient Temperature vs. Release Delay Time (tDR) XC61HC3012 Release Delay Time: tDR (ms) Release Delay Time: tDR (ms) XC61HC3042 Release Delay Time: tDR (ms) XC61HC3052 10/13 XC61H Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) （8）Input Voltage vs. Release Delay Time (tDR) XC61HC2712 Release Delay Time: tDR (ms) 11/13 XC61H Series ■PACKAGING INFORMATION ●SOT-23 ■MARKING RULE ●SOT-23 ①Represents integer of detect voltage and output configuration CMOS output (XC61HC series) MARK CONFIGURATION B C D E F H CMOS CMOS CMOS CMOS CMOS CMOS VOLTAGE (V) 1. X 2. X 3. X 4. X 5. X 6. X N-channel open drain (XC61HN series) MARK CONFIGURATION VOLTAGE (V) L M N P R S N-ch N-ch N-ch N-ch N-ch N-ch ③Represents delay time VOLTAGE (V) X.5 X.6 X.7 X.8 X.9 VOLTAGE (V) 5 6 7 DELAY TIME 50ms∼200ms 80ms∼400ms 1ms∼50ms 1. X 2. X 3. X 4. X 5. X 6. X ②Represents decimal number of detect voltage MARK 0 1 2 3 4 VOLTAGE (V) X.0 X.1 X.2 X.3 X.4 MARK 5 6 7 8 9 ④Represents assembly lot number (Based on internal standards) 12/13 XC61H Series 1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. The products in this datasheet are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. Please use the products listed in this datasheet within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. We assume no responsibility for damage or loss due to abnormal use. 7. All rights reserved. No part of this datasheet may be copied or reproduced without the prior permission of TOREX SEMICONDUCTOR LTD. 13/13