XD6131A341MR-Q

XD6130/XD6131Series ETR02039-006 Watchdog Timeout Period Externally Adjustable Voltage Detector ☆AEC-Q100 Grade1 ■ GENERAL DESCRIPTION The XD6130/XD6131 series are voltage detectors with a watchdog function. The watchdog timeout time and release delay time can be set as desired using a single external capacitor. These voltage detectors are used for microprocessor monitoring, and when the power voltage reaches the detect voltage or an L→H pulse is not input to the watchdog pin within the watchdog timeout time, an L level signal is output from the RESETB pin. The XD6130 series has a manual reset function. When the manual reset pin is set to Low level at any desired timing, an L level signal is output from the RESETB pin. The XD6131 series has a watchdog ON/OFF function. By setting the EN pin to L level, the watchdog function can be turned OFF while the voltage detector that monitors the power voltage continues to operate. The MRB pin and EN pin are pulled up internally to VIN, and thus these pins can be left open when not used. ■FEATURES ■APPLICATIONS Operating Ambient Temperature : -40℃ ~ 125℃ Operating Voltage Range : 1.5V ~ 6.0V Detect Voltage (Standard) : 1.6V,2.2V,2.3V,2.4V,2.9V,3.0V, 3.1V,4.4V,4.5V,4.6V,±1.0% Detect Voltage Range(Option) : 1.6V ~ 5.0V (±1.0%) Hysteresis Width : VDFL×5% Temperature Characteristics : ±50ppm/℃ Output Configuration : N-channel open drain output Low Power Consumption : 8.1μA Detect 9.8μA Release 2.5μA Release (EN=L) Function : Manual Reset (XD6130) : Watchdog function OFF (XD6131) WD Timeout Time : 100ms (Cd=0.1μF) Release Delay Time : 100ms (Cd=0.1μF) (at power on) 10ms (Cd=0.1μF) (After Watchdog Timeout) Package : SOT-26 Environmentally Friendly : EU RoHS compliant, Pb free ●Microprocessor reset and malfunction monitoring circuitry ●Memory battery backup circuits ●Power-on reset circuits ●Power failure detection ■TYPICAL APPLICATION CIRCUIT ■TYPICAL PERFORMANCE XD6130 Series CHARACTERISTICS XC6130シリーズ VIN VIN RESETB MRB WD Function ON WD Function OFF VSS XD6131 Series XC6131シリーズ VIN VIN Supply Current:ISS(μA) 12 I/O RESET SW 10 8 6 4 2 Rpull RESETB EN/ENB Cd 14 RESETB INPUT WD Cd Cd=0.01μF, WD=RESETB=OPEN, Ta=25℃ EN=VSS(WD Function OFF) EN=VIN (WD Function ON) XC6131A301MR-G XD6131A301MR-Q Rpull RESETB INPUT 0 0 1 2 3 4 5 6 Input Voltage:VIN(V) VSS WD I/O The above values do not include the current that flows to the EN pull-up resistance. 1/29 XD6130/XD6131 Series ■BLOCK DIAGRAM ●XD6130 Series Type A VIN RH RX + RMRB RY RESET LOGIC Voltage Reference RESETB VSS MRB Cd LOGIC + - L→H　PULSE DETECT　LOGIC Voltage Reference RWD WD Cd ● XD6131 Series Type A VIN RH RX RY RESET LOGIC + REN Voltage Reference VSS EN Cd LOGIC + L→H　PULSE DETECT　LOGIC Voltage Reference Cd RWD WD * Diodes inside the circuit are an ESD protection diode and a parasitic diode. 2/29 RESETB XD6130/XD6131 Series ■BLOCK DIAGRAM ● XD6131 Series Type B VIN RH RX RY RESET LOGIC + REN RESETB Voltage Reference VSS EN Cd LOGIC + L→H　PULSE DETECT　LOGIC Voltage Reference Cd RWD WD * Diodes inside the circuit are an ESD protection diode and a parasitic diode. 3/29 XD6130/XD6131 Series ■PRODUCT CLASSIFICATION ●Ordering Information XD6130①②③④⑤⑥-⑦ DESIGNATOR ① ②③ ④ ⑤⑥-⑦ (*1) ITEM SYMBOL TYPE Detect Voltage Detect Accuracy Package (Order Unit) A 16 ~ 50 1 MR-Q DESCRIPTION MRB pin With pull-up resistor e.g. 1.6V → ②=1, ③=6 ±1.0% SOT-26 (3000pcs/Reel)(*2) (*1) The “-Q” suffix denotes “AEC-Q100” and “Halogen and Antimony free” as well as being fully EU RoHS compliant. (*2) The SOT-26 reels are shipped in a moisture-proof packing. XD6131①②③④⑤⑥-⑦ DESIGNATOR ITEM ① TYPE ②③ ④ ⑤⑥-⑦ (*1) Detect Voltage Detect Accuracy Package (Order Unit) SYMBOL A B 16 ~ 50 1 MR-Q DESCRIPTION EN pin With pull up resistor ENB pin With pull down resistor e.g. 1.6V → ②=1, ③=6 ±1.0% SOT-26 (3000pcs/Reel)(*2) (*1) The “-Q” suffix denotes “AEC-Q100” and “Halogen and Antimony free” as well as being fully EU RoHS compliant. (*2) The SOT-26 reels are shipped in a moisture-proof packing. ●Detect Voltage (Standard) Part No. XD6130A161MR-Q XD6130A221MR-Q XD6130A231MR-Q XD6130A241MR-Q XD6130A291MR-Q XD6130A301MR-Q XD6130A311MR-Q XD6130A441MR-Q XD6130A451MR-Q XD6130A461MR-Q TYPE Detect Voltage MRB pin With pull-up resistor 1.6V 2.2V 2.3V 2.4V 2.9V 3.0V 3.1V 4.4V 4.5V 4.6V Part No. XD6131A161MR-Q XD6131A221MR-Q XD6131A231MR-Q XD6131A241MR-Q XD6131A291MR-Q XD6131A301MR-Q XD6131A311MR-Q XD6131A441MR-Q XD6131A451MR-Q XD6131A461MR-Q XD6131B161MR-Q XD6131B221MR-Q XD6131B231MR-Q XD6131B241MR-Q XD6131B291MR-Q XD6131B301MR-Q XD6131B311MR-Q XD6131B441MR-Q XD6131B451MR-Q XD6131B461MR-Q TYPE EN pin With pull-up resistor ENB pin With pull-down resistor For another type of detect voltage, please contact your local Torex sales office or representative. Output voltages can be set internally from 1.6V to 5.0V. 4/29 Detect Voltage 1.6V 2.2V 2.3V 2.4V 2.9V 3.0V 3.1V 4.4V 4.5V 4.6V 1.6V 2.2V 2.3V 2.4V 2.9V 3.0V 3.1V 4.4V 4.5V 4.6V XD6130/XD6131 Series ■PIN CONFIGURATION Cd Cd VSS RESETB 6 5 6 4 VSS RESETB 5 4 1 2 3 1 2 3 WD MRB VIN WD EN /ENB VIN SOT-26 (TOP VIEW) SOT-26 (TOP VIEW) XD6130 series XD6131 series ■PIN ASSIGNMENT XD6130 Series PIN NUMBER PIN NAME FUNCTIONS 1 WD Watchdog Input 2 MRB Manual Reset Input 3 VIN Power Input 4 RESETB Reset Output 5 VSS Ground 6 Cd Adjustable Pin for Release Delay Time/Watchdog Timeout PIN NAME FUNCTIONS WD Watchdog Input EN Watchdog ON/OFF Control (XD6131A) ENB Watchdog ON/OFF Control (XD6131B) 3 VIN Power Input 4 RESETB Reset Output 5 VSS Ground 6 Cd Adjustable Pin for Release Delay Time/Watchdog Timeout SOT-26 XD6131 Series PIN NUMBER SOT-26 1 2 5/29 XD6130/XD6131 Series ■FUNCTION CHART 1) XD6130 Series VIN *2 VMRB *3 VWD *6 VRESETB *7 H H H L OPEN L⇔H H L L L L⇔H H L *1 H L L 2) XD6131A Series VIN *2 VEN *4 VWD *6 VRESETB *7 H H H L OPEN L⇔ H H L L L L⇔ H H H *1 H L L 3) XD6131B Series VIN *2 VENB *5 VWD *6 VRESETB *7 H H L L OPEN L⇔ H H L H L L⇔ H H H *1 H L L *1: Includes all WD logic (VWD=H, L, OPEN, H→L, L→H) *2: VIN=H indicates higher than the release voltage. VIN=L indicates lower than the detect voltage. *3: VMRB=H indicates MRB High Level Voltage. VMRB=L indicates MRB Low Level Voltage. Since MRB pin of XD6130 Series is pulled up internally, the open condition of MRB pin is acceptable when MR function is not required. *4: VEN=H indicates EN High Level Voltage. VEN=L indicates EN Low Level Voltage. The EN pin of the XD6131A Series is pulled up internally, enabling the WD function to be used with EN open. *5: VENB=H indicates ENB High Level Voltage. VENB=L indicates ENB Low Level Voltage. The ENB pin of the XD6131B Series is pulled down internally, enabling the WD function to be used with ENB open. *6: VWD=H indicates WD High Level Voltage. VWD=L indicates WD Low Level Voltage. *7: VRESETB=H indicates the release state. VRESETB=L indicates the detect state. 6/29 XD6130/XD6131 Series ■ ABSOLUTE MAXIMUM RATINGS XD6130 Series PARAMETER SYMBOL RATINGS UNITS Input Voltage VIN -0.3 ~ 7.0 V WD Input Voltage VWD -0.3 ~ 7.0 V MRB Input Voltage VMRB -0.3 ~ 7.0 V Cd Pin Voltage VCd -0.3 ~ VIN+0.3 or 7.0(*1) V Output Voltage VRESETB -0.3 ~ 7.0 V Cd Pin Current ICd 10 mA Output Current IOUT 30 mA Power Dissipation (Ta=25℃) SOT-26 Pd 250 600 (40mm x 40mm Standard Board) (*2) mW Operating Ambient Temperature Topr -40 ~ 125 ℃ Storage Temperature Tstg -55 ~ 125 ℃ All voltages are described based on the VSS pin. (*1) The maximum value should be VIN+0.3V or 7.0V in the lowest. (*2) The power dissipation figure shown is PCB mounted and is for reference only. Please refer to PACKAGING INFORMATION for the mounting condition. XD6131 Series PARAMETER SYMBOL RATINGS UNITS Input Voltage VIN -0.3 ~ 7.0 V WD Input Voltage VWD -0.3 ~ 7.0 V EN/ENB Input Voltage VEN/VENB -0.3 ~ 7.0 Cd Pin Voltage VCd Output Voltage VRESETB -0.3 ~ 7.0 V Cd Pin Current ICd 10 mA Output Current IOUT 30 mA Power Dissipation (Ta=25℃) SOT-26 Pd -0.3 ~ VIN+0.3 or V 7.0(*1) 250 600 (40mm x 40mm Standard Board) (*2) V mW Operating Ambient Temperature Topr -40 ~ 125 ℃ Storage Temperature Tstg -55 ~ 125 ℃ All voltages are described based on the VSS pin. (*1) The maximum value should be VIN+0.3V or 7.0V in the lowest. (*2) The power dissipation figure shown is PCB mounted and is for reference only. Please refer to PACKAGING INFORMATION for the mounting condition. 7/29 XD6130/XD6131 Series ■ELECTRICAL CHARACTERISTICS XD6130 Series PARAMETER SYMBOL Operating Voltage VIN Detect Voltage VDFL Temperature ΔVDFL/ Characteristics (ΔTopr・VDFL) Hysteresis Width Supply Current Ta=25℃ CONDITIONS -40℃≦Topr≦125℃ IRBOUT MAX. MIN. TYP. MAX. 1.5 - 6.0 1.5 - 6.0 - VDF(T) ±50 VDF(T) VDF(T) ×1.01 ×0.975 - - VDF(T) ±50 VDF(T) ×1.025 - VDFL VDFL VDFL VDFL VDFL VDFL ×0.04 ×0.05 ×0.06 ×0.03 ×0.05 ×0.07 VIN=VDF(T) ×0.9 - 8.1 12.1 - 8.1 14.0 VIN=VDF(T) ×1.1 - 9.8 12.6 - 9.8 13.6 2.6 3.5 - 1.4 3.5 - VIN=1.5V Output Current TYP. ×0.99 VHYS Iss MIN. VDF(T) VDF(T)(*1)=1.6~5.0V -40℃≦Ta≦125℃(*9) N-ch. VIN=2.0V (*2) 4.9 6.0 - 3.0 6.0 - VRESETB=0.3V VIN=3.0V(*3) 9.2 10.3 - 5.8 10.3 - VIN=4.0V(*4) 12.3 13.8 - 7.7 13.8 - - 0.01 0.1 - 0.01 1 V ppm /℃ μA ② mA ③ μA ④ Cd Pin Sink Current Icd VIN=1.5V, VCd=0.7V 530 770 - 295 770 - tDR1 VIN=1.5V→VDF(T)×1.1, Cd=0.01μF 8.5 10.0 11.5 7 10.0 12 tDR2 VIN=VDF(T)×1.1, Cd=0.01μF 0.85 1.0 1.15 0.7 1.0 1.2 8.5 10.0 11.5 7 10.0 12 - 10.0 50 - 10.0 100 μs 100 - - 100 - - ns Release Delay Time2(*6) Watchdog Timeout Period(*7) Detect Delay Time(*8) Watchdog Pulse Width Watchdog High Level Voltage Watchdog Low Level Voltage Watchdog Pull-down Resistance MRB High Level Voltage MRB Low Level Voltage MRB Pull-up Resistance MRB Pulse Width tWD tDF VIN=VDF(T)×1.1V, Cd=0.01μF,WD=VSS VIN=VDF(T)×1.1→1.5V, Cd=0.01μF ① V ILeak Time1(*5) CIRCUIT V Leak Current Release Delay VIN=6.0V,VRESETB=6.0 UNITS ms ⑤ VIN=6.0V, Cd=0.01μF tWDIN Apply pulse from 6.0V to 0V to the WD pin. ⑥ VWDH VIN=VDF(T)×1.1→6.0V VIN×0.7 - 6 VIN×0.7 - 6 V VWDL VIN=VDF(T)×1.1→6.0V 0 - VIN×0.3 0 - VIN×0.3 V RWD VWD=6.0V, RWD=VWD/IWD 280 550 1100 220 550 1350 kΩ 1.3 - VIN 1.3 - VIN V 0 - 0.45 0 - 0.45 V 300 800 1200 230 800 1420 kΩ ⑨ 1.0 - - 1.0 - - μs ⑩ VMRH VIN=VDF(T)×1.1~6.0V VMRL RMR VIN=6.0V, VMRB=0V, RMR=VIN/IMRB ⑦ ⑧ VIN=6.0V, tMRIN Apply pulse from 6.0V to 0V to the MRB pin. NOTE: *The WD pin and MRB pin are open unless otherwise specified in the measurement conditions. (*1) VDF(T): Nominal detect voltage (*2) For VDF(T)＞2.0V products only. (*3) For VDF(T)＞3.0V products only. (*4) For VDF(T)＞4.0V products only. (*5) Until time when RESETB pin shows release status after VIN reached the release voltage. Release voltage (VDR) = Detect voltage (VDFL) + Hysteresis width (VHYS) (*6) The time to change the status of RESETB pin from the detect-status after the watchdog-timeout happens with the condition of WD=VSS. (*7) The time to change the status of RESETB pin from the release-status to the detect-status with the condition of WD=VSS. (*8) When VIN is changed during watchdog timeout time, until time when RESETB pin shows detect status after VIN reached the detect voltage. (*9) The ambient temperature range (-40℃≦Ta≦125℃) is design Value. 8/29 XD6130/XD6131 Series ■ELECTRICAL CHARACTERISTICS (Continued) XD6131A Series PARAMETER SYMBOL Operating Voltage VIN Detect Voltage VDFL Temperature ΔVDFL/ Characteristics (ΔTopr・VDFL) Hysteresis Width CONDITIONS VDF(T)(*1)=1.6~5.0V -40℃≦Topr≦125℃ VHYS VIN=VDF(T) ×0.9 Supply Current Output Current Leakage Current Cd Pin Sink Current Release Delay Time1(*6) Release Delay Time2(*7) Watchdog Timeout Period(*8) Detect Delay Time(*9) Watchdog Pulse Width Iss IRBOUT ILeak VIN=VDF(T)×1.1 EN=L(*2) EN=H Ta=25℃ MIN. TYP. 1.5 - VDF(T) ×0.99 - VDF(T) ±50 -40℃≦Ta≦125℃(*10) MAX. MIN. TYP. - 6.0 1.5 VDF(T) VDF(T) ×1.01 ×0.975 - - VDF(T) ±50 MAX. 6.0 VDF(T) ×1.025 - VDFL VDFL VDFL VDFL VDFL VDFL ×0.04 ×0.05 ×0.06 ×0.03 ×0.05 ×0.07 - 8.1 12.1 - 8.1 14.0 - 2.5 3.5 - 2.5 5.0 13.6 - 9.8 12.6 - 9.8 VIN=1.5V 2.6 3.5 - 1.4 3.5 - N-ch. VIN=2.0V(*2) 4.9 6.0 - 3.0 6.0 - VRESETB=0.3V VIN=3.0V(*3) 9.2 10.3 - 5.8 10.3 - VIN=4.0V(*4) 12.3 13.8 - 7.7 13.8 - - 0.01 0.1 - 0.01 VIN=6.0V, VRESETB=6.0V UNITS V V ppm /℃ μA ② mA ③ μA ④ VIN=1.5V, VCd=0.7V 530 770 - 295 770 - tDR1 VIN=1.5V→VDF(T)×1.1, Cd=0.01μF 8.5 10.0 11.5 7 10.0 12 tDR2 VIN=VDF(T)×1.1, Cd=0.01μF 0.85 1.0 1.15 0.7 1.0 1.2 8.5 10.0 11.5 7 10.0 12 - 10.0 50 - 10.0 100 μs 100 - - 100 - - ns tDF VIN=VDF(T)×1.1, Cd=0.01μF, WD=VSS VIN=VDF(T)×1.1→1.5V, Cd=0.01μF ms ⑤ VIN=6.0V, Cd=0.01μF tWDIN Apply pulse from 6.0V to 0V to the WD pin. Watchdog High Level ① V Icd tWD CIRCUIT ⑥ VWDH VDF(T)×1.1≦VIN≦6.0V VIN×0.7 - 6 VIN×0.7 - 6 V VWDL VDF(T)×1.1≦VIN≦6.0V 0 - VIN×0.3 0 - VIN×0.3 V RWD VWD=6.0V, RWD=VWD/IWD 280 550 1100 220 550 1350 kΩ ⑦ 1.3 - VIN 1.3 - VIN V ⑧ 0 - 0.45 0 - 0.45 V Voltage Watchdog Low Level Voltage Watchdog Pull-down Resistance EN High Level Voltage EN Low Level Voltage EN Pull-up Resistance VENH VIN=VDF(T)×1.1~6.0V VENL REN VIN=6.0V,VEN=0V, REN=VIN/IEN ⑨ 300 800 1200 230 800 1420 kΩ NOTE: * The WD pin and EN pin are open unless otherwise specified in the measurement conditions. (*1) VDF(T): Nominal detect voltage (*2) Excludes the current that flows to EN pull-up resistance when EN = L. (*3) For VDF(T)＞2.0V products only. (*4) For VDF(T)＞3.0V products only. (*5) For VDF(T)＞4.0V products only. (*6) Until time when RESETB pin shows release status after VIN reached the release voltage. Release voltage (VDR) = Detect voltage (VDFL) + Hysteresis width (VHYS) (*7) The time to change the status of RESETB pin from the detect-status after the watchdog-timeout happens with the condition of WD=VSS. (*8) The time to change the status of RESETB pin from the release-status to the detect-status with the condition of WD=VSS. (*9) When VIN is changed during watchdog timeout time, until time when RESETB pin shows detect status after VIN reached the detect voltage. (*10) The ambient temperature range (-40℃≦Ta≦125℃) is design Value. 9/29 XD6130/XD6131 Series ■ELECTRICAL CHARACTERISTICS (Continued) XD6131B Series PARAMETER SYMBOL Operating Voltage VIN Detect Voltage VDFL Temperature ΔVDFL/ Characteristics (ΔTopr・VDFL) Hysteresis Width VHYS Ta=25℃ CONDITIONS Iss -40℃≦Topr≦125℃ IRBOUT Period(*8) Detect Delay Time(*9) Watchdog Pulse Width Watchdog High Level Voltage Watchdog Low Level Voltage 6.0 1.5 - 6.0 VDF(T) ±50 VDF(T) VDF(T) ×1.01 ×0.975 - - VDF(T) ±50 VDF(T) ×1.025 - VDFL VDFL VDFL VDFL VDFL ×0.05 ×0.06 ×0.03 ×0.05 ×0.07 - 8.1 12.1 - 8.1 14.0 ENB=H - 2.5 3.5 - 2.5 5.0 ENB=L - 9.8 12.6 - 9.8 13.6 N-ch. VIN=2.0V (*2) VRESETB=0.3V VIN=3.0V (*3) 2.6 3.5 - 1.4 3.5 - 4.9 6.0 - 3.0 6.0 - 9.2 10.3 - 5.8 10.3 - V ppm /℃ μA ② mA ③ μA ④ - 7.7 13.8 - 0.01 VIN=1.5V, VCd=0.7V 530 770 - 295 770 - tDR1 VIN=1.5V→VDF(T)×1.1, Cd=0.01μF 8.5 10.0 11.5 7 10.0 12 tDR2 VIN=VDF(T)×1.1, Cd=0.01μF 0.85 1.0 1.15 0.7 1.0 1.2 8.5 10.0 11.5 7 10.0 12 - 10.0 50 - 10.0 100 μs 100 - - 100 - - ns tWD tDF VIN=VDF(T)×1.1, Cd=0.01μF, WD=VSS VIN=VDF(T)×1.1→1.5V, Cd=0.01μF ① V 0.1 VIN=6.0V, VRESETB=6.0V CIRCUIT V 13.8 Icd Watchdog Timeout - 0.01 Cd Pin Sink Current Time2(*7) 1.5 UNITS - ILeak Release Delay MAX. 12.3 Leakage Current Time1(*6) TYP. VDFL VIN=4.0V(*4) Release Delay MIN. ×0.04 VIN=1.5V Output Current MAX. - (*2) VIN=VDF(T)×1.1 TYP. ×0.99 VIN=VDF(T) ×0.9 Supply Current MIN. VDF(T) VDF(T)(*1)=1.6~5.0V -40℃≦Ta≦125℃(*10) ms ⑤ VIN=6.0V, Cd=0.01μF tWDIN Apply pulse from 6.0V to 0V to the WD pin. ⑥ VWDH VDF(T)×1.1≦VIN≦6.0V VIN×0.7 - 6 VIN×0.7 - 6 V VWDL VDF(T)×1.1≦VIN≦6.0V 0 - VIN×0.3 0 - VIN×0.3 V RWD VWD=6.0V, RWD=VWD/IWD 280 550 1100 220 550 1350 kΩ ⑦ 1.3 - VIN 1.3 - VIN V ⑧ 0 - 0.45 0 - 0.45 V 300 800 1200 230 800 1420 kΩ Watchdog Pull-down Resistance ENB High Level Voltage VENBH ENB Low Level Voltage VENBL ENB Pull-down RENB VIN=VDF(T)×1.1~6.0V VENB=6.0V, RENB=VENB/IENB Resistance NOTE: *The WD pin and ENB pin are open unless otherwise specified in the measurement conditions. (*1) VDF(T): Nominal detect voltage (*2) Excludes the current that flows to the EN pull-down resistance when ENB = H. (*3) For VDF(T)＞2.0V products only. (*4) For VDF(T)＞3.0V products only. (*5) For VDF(T)＞4.0V products only. (*6) Until time when RESETB pin shows release status after VIN reached the release voltage. Release voltage (VDR) = Detect voltage (VDFL) + Hysteresis width (VHYS) (*7) The time to change the status of RESETB pin from the detect-status after the watchdog-timeout happens with the condition of WD=VSS. (*8) The time to change the status of RESETB pin from the release-status to the detect-status with the condition of WD=VSS. (*9) When VIN is changed during watchdog timeout time, until time when RESETB pin shows detect status after VIN reached the detect voltage. (*10) The ambient temperature range (-40℃≦Ta≦125℃) is design Value. 10/29 ⑨ XD6130/XD6131 Series ■ TEST CIRCUITS CIRCUIT① VIN 100ｋΩ MRB/EN/ENB V RESETB Cd WD V VSS CIRCUIT② A VIN MRB/EN/ENB RESETB Cd WD VSS CIRCUIT③ VIN MRB/EN/ENB V IRESETB A RESETB Cd WD VSS CIRCUIT④ VIN Iｃｄ A MRB/EN/ENB RESETB Cd WD ILeak A VSS CIRCUIT⑤ VIN MRB/EN/ENB RESETB Cd WD VSS 100ｋΩ Waveform Measure Point 11/29 XD6130/XD6131 Series ■ TEST CIRCUITS (Continued) CIRCUIT⑥ tWDIN　Min. VIN WD MRB/EN/ENB RESETB Cd WD VIN×0.3 Waveform Measure Point VSS VIN×0.7 (VDF（T)×1.1≦VIN≦6.0V) RESETB tWD CIRCUIT⑦ VIN MRB/EN/ENB IWD Cd A WD RESETB VSS CIRCUIT⑦ VIN MRB/EN/ENB IWD Cd A WD RESETB VSS CIRCUIT⑧ VIN 100ｋΩ MRB/EN/ENB V WD CIRCUIT⑨ IMRB　 IEN IENB RESETB Cd V VSS VIN A MRB/EN/ENB RESETB Cd WD VSS CIRCUIT⑩ tMRIN Min. MRB VIN RESETB Cd WD 12/29 MRB VSS Waveform Measure Point RESETB （VDFL) tDR2 XD6130/XD6131 Series ■OPERATIONAL EXPLANATION In the XD6130/XD6131 Series, the voltage divided by RH, RX, and RY connected to the VIN pin is compared to the internal reference voltage by the comparator, and the resulting output signal drives the watchdog logic and output driver. The VIN pin voltage is gradually lowered, and when the VIN pin voltage reaches the detect voltage, H→L level signal is output to the reset output pin (VDFL type). VIN RH RX + RMRB RY RESET LOGIC Voltage Reference RESETB VSS MRB Cd LOGIC + - L→H　PULSE DETECT　LOGIC Voltage Reference RWD WD Cd XD6130 Series If the VIN pin voltage is below the detect voltage, the reset output pin outputs H→L level signal. After the VIN pin voltage reaches the release voltage, the reset output pin holds L level during release delay time1 (tDR1). If a start signal is not input to the WD pin within the watchdog timeout time, the reset output pin holds L level during release delay time 2 (tDR2) and then outputs H level signal. If the internal comparator outputs L level signal, the PMOS transistor connected in parallel to RH turns ON and the hysteresis circuit activates. The hysteresis voltage width is obtained from the difference between the detect voltage and the release voltage. The hysteresis width is VDFL×0.05 (TYP.). A watchdog timer is used to detect abnormal operation and runaway in a microprocessor. If “L→H” signal is not input from the microprocessor within the watchdog timeout time, the reset output pin holds the detect state during release delay time 2 (tDR2), and then L→H level signal is output to the reset output pin. In addition, the watchdog pin is pulled down internally to VSS, and when the watchdog pin is OPEN, a reset signal is output after the watchdog timeout time. The watchdog timeout time (tWD) can be set using the equation below. tWD＝Cd×106 Example: When Cd is 0.1μF, tWD=0.1×10-6×106 = 100ms (TYP.) 13/29 XD6130/XD6131 Series ■OPERATIONAL EXPLANATION (Continued) When power is added on the VIN, the time from the point that VIN reaches the release voltage until the reset output pin reaches the release voltage is release delay time 1 (tDR1). Release delay time 1 (tDR1) can be set using the equation below. tDR1=Cd×106 Example: When Cd is 0.1μF, tDR1= 0.1×10-6×106=100ms (TYP.) Release delay time 2 (tDR2) is the duration of the detect state until the watchdog timer restarts when “L → H” signal is not input to the WD pin within the watchdog timeout time. Release delay time 2 (tDR2) can be set using the equation below. tDR2=Cd×105 Example: When Cd is 0.1μF, tDR2=0.1×10-6×105=10ms (TYP.) The detect delay time (tDF) is the time until the VIN pin voltage drops to the detect voltage and the reset output pin enters the detect state. *XD6130 Series The MRB pin voltage can be input to force the signal of the reset output pin to the detect state. When the MRB pin voltage input reaches an H→L level signal, an H→L level signal is output to the reset output pin. After the MRB pin voltage reaches L→H level, the reset output pin holds the detect state during release delay time 1(tDR1). *XD6131A Series If the watchdog function will not be used, the EN pin can be set to L level to forcibly stop only the watchdog function and keep the voltage detector operating. When using the watchdog function, use the EN pin at H level. If the input voltage and EN pin voltage reach L→H level, the reset output pin holds the detect state during release delay time 1 (tDR1). (Refer to Timing Chart 2, ①) If the input voltage is higher than the release voltage and the EN pin voltage reaches L→H level, the watchdog function recovers. (Refer to Timing Chart 2, ②) *XD6131B Series When the watchdog function is not used, the ENB pin can be set to H level to keep the voltage detector operating and forcibly stop only the watchdog function. To use the watchdog function, use the ENB pin at L level. When the input voltage and ENB pin voltage reach H→L level, the reset output pin holds the detect state during release delay time 1 (tDR1). (Refer to Timing Chart 3, ①) When the input voltage is higher than the release voltage and the ENB pin voltage reaches H→L level, the watchdog function recovers. (Refer to Timing Chart 3, ②) 14/29 XD6130/XD6131 Series ■OPERATIONAL EXPLANATION (Continued) XD6130 Series VIN VDR Level VDF Level VIN Pin Wave Form Hysterisis Range Min.Operating Voltage GND Pulse Width : “tMRIN Min” or more MRB Pin Wave Form MRB GND Ignore Ignore Pulse Width : “tWDIN Min” or more Ignore Ignore Ignore WD tWD tWD WD Pin Wave Form tWD GND Cd Pin Wave Form Cd HIGH Level Cd Low Level GND RESETB Pin Wave Form VDR Level VDF Level Min.Operating Voltage GND Unstable tDR1 tDR2 tDR2 tDR2 tDR1 15/29 XD6130/XD6131 Series ■OPERATIONAL EXPLANATION (Continued) XD6131A Series VIN VDR Level VDF Level VIN Pin Wave Form Hysterisis Range Min.Operating Voltage GND EN Pin Wave Form EN GND Ignore Ignore Pulse Width : “tWDIN Min” or more Ignore Ignore Ignore WD tWD tWD tWD WD Pin Wave Form GND Cd Pin Wave Form Cd HIGH Level Cd Low Level GND RESETB Pin Wave Form VDR Level VDF Level Min.Operating Voltage GND Unstable tDR1 ① 16/29 tDR2 tDR2 tDR2 ② XD6130/XD6131 Series ■OPERATIONAL EXPLANATION(Continued) XD6131B Series VIN VDR Level VDF Level VIN Pin Wave Form Hysterisis Range Min.Operating Voltage GND ENB ENB Pin Wave Form GND Ignore Ignore Pulse Width : “tWDIN Min” or more Ignore Ignore WD tWD Ignore WD Pin Wave Form tWD tWD GND Cd Pin Wave Form Cd HIGH Level Cd Low Level GND RESETB Pin Wave Form VDR Level VDF Level Min.Operating Voltage GND Unstable tDR1 ① tDR2 tDR2 tDR2 ② 17/29 XD6130/XD6131 Series ■NOTES ON USE 1. Use this IC within the absolute maximum ratings. Risk of deterioration or damage if the absolute maximum ratings are exceeded during temporary or transient voltage drops or voltage jumps. 2. If a resistance is added between the power and the VIN pin, the flowthrough current when the IC operates will cause the VIN pin voltage to drop and the IC may malfunction. 3. When raising the input voltage from the minimum operating voltage or less, if changed suddenly, the release delay time may become short. 4. Sufficiently reinforce the VIN and GND lines, as power noise may cause malfunctioning of the watchdog function and voltage detector. It is recommended that a capacitor be added between VIN and GND. 5. Enter “H” level, or “L” level should be fed to MRB and EN/ENB pin. 6. To ensure stable operation of the watchdog function, be sure to add a capacitor at the Cd pin. The release delay time and watchdog timeout time are affected by the accuracy and temperature characteristics of the Cd pin capacitor. 7. If the Cd pin capacitor is unable to discharge to the ground level during recovery after a power interruption, the release delay may become noticeably shorter. Exercise caution. 8. The output voltage at detection is determined by the pull-up resistance connected to RESETB pin. Select the resistance based on the following considerations: At detection: VRESETB=(Vpull-Up)/(1+Rpull/RON) Vpull-Up: Voltage after pull-up RON (*1): ON resistance of N-ch driver (calculated from VRESETB/IRBOUT1 in electrical characteristics)(*3) Example calculation: When VIN=2.0V (*2), RON=0.3/4.9×10-3≒61.2Ω(MAX.). If you wish to make the VRESETB voltage at detection 0.1V or lower with Vpull-Up=3.0V, Rpull=(Vpull-Up /VRESETB-1)×RON=(3/0.1-1)×61.2≒1.8kΩ, and thus to make the output voltage at detection 0.1V or less under the above conditions, the pull-up resistance must be 1.8kΩ or higher. The smaller VIN is, the larger RON becomes. When selecting VIN, calculate using the lowest value of the input voltage range you will use. (*3) IRBOUT1 specified in the electrical characteristics is the value at Ta=25℃. IRBOUT1 varies depending on the ambient temperature. To select the pull-up resistance taking ambient temperature into account, please calculate IRBOUT with the MIN. value of the ambient temperature range of -40℃≦Ta≦125℃. (*1) (*2) At release: VRESETB = (Vpull-Up)/(1+Rpull/ROFF) Vpull-Up: Voltage after pull-up ROFF: Resistance value 60MΩ(MIN.) when N-ch driver is OFF (calculated from VRESETB/ILEAK in electrical characteristics) Calculation example: If you wish to make VRESETB 5.99V or higher with Vpull-Up=6.0V Rpull=(Vpull-Up/VRESETB-1)×ROFF=(6/5.99-1)×60×106≒100kΩ, and thus to make the output voltage 5.99V or higher at release under the above conditions, the pull-up resistance must be 100kΩ or less. 9. With the XD6131 series, the Cd pin capacitor is discharged when the watchdog function is stopped with EN or ENB. If the watchdog function is restarted when the Cd pin voltage is Cd Low Level (TYP. 0.25V) or higher, the L level may be output to the output pin. When restarting the watchdog function, secure a sufficient period for stopping the function and discharge the Cd pin capacitor before use. 10. We place importance on improving our products and increasing reliability. However, please design safety into the device and system, including fail-safe design and post-aging treatment. 18/29 XD6130/XD6131 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (1) Detect, Release Voltage vs. Ambient Temperature (2) Detect, Release Voltage vs. Input Voltage XD6130,XD6131 (VDF(T)=1.6V) Rpull-up=100kΩ OutPut Voltage : VRESETB (V) 6 5 4 3 Ta=-40℃ Ta=25℃ 2 Ta=85℃ Ta=125℃ 1 0 0 1 2 3 4 5 6 Input Voltage : VIN (V) XD6130,XD6131 (VDF(T)=5.0V) XD6130,XD6131 (VDF(T)=3.0V) Rpull-up=100kΩ 5 4 Ta=-40℃ 3 Ta=25℃ 2 Ta=85℃ Ta=125℃ 1 0 0 1 2 3 4 Input Voltage : VIN (V) 5 6 Rpull-up=100kΩ 6 Detect Voltage : VDFL (V) Detect Voltage : VDFL (V) 6 5 4 Ta=-40℃ 3 Ta=25℃ 2 Ta=85℃ 1 0 Ta=125℃ 0 1 2 3 4 5 Input Voltage : VIN (V) 19/29 6 XD6130/XD6131 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (3) Supply Current vs. Input Voltage 20/29 XD6130/XD6131 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (3) Supply Current vs. Input Voltage (Continued) (4) Output Current vs. VRESETB (5) Output Current vs. Input Voltage 21/29 XD6130/XD6131 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (6) Cd Sink Current vs. Ambient Temperature (7) Release Delay Time1 vs. Ambient Temperature (8) Release Delay Time2 vs. Ambient Temperature 22/29 XD6130/XD6131 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (9) Watchdog Timeout Period vs. Ambient Temperature (10) WD High Level Threshold Voltage vs. Ambient Temperature (11) WD Low Level Threshold Voltage vs. Ambient Temperature 23/29 XD6130/XD6131 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (12) MRB High Level Threshold Voltage vs. Ambient Temperature (14) EN High Level Threshold Voltage vs. Ambient Temperature (16) ENB High Level Threshold Voltage vs. Ambient Temperature 24/29 (13) MRB Low Level Threshold Voltage vs. Ambient Temperature (15) EN Low Level Threshold Voltage vs. Ambient Temperature (17) ENB Low Level Threshold Voltage vs. Ambient Temperature XD6130/XD6131 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (18) MRB Pull-up Resistance vs. Ambient Temperature (19) EN Pull-up Resistance vs. Ambient Temperature (20) ENB Pull-down Resistance vs. Ambient Temperature (21) WD Pull-down Resistance vs. Ambient Temperature ENB Pull-down Resistance : RENB (kΩ) XD6131B 1000 900 800 700 600 500 400 300 -50 -25 0 25 50 75 100 125 150 Ambient Temperature : Ta (℃) 25/29 XD6130/XD6131 Series ■PACKAGING INFORMATION For the latest package information go to, www.torexsemi.com/technical-support/packages PACKAGE OUTLINE / LAND PATTERN THERMAL CHARACTERISTICS SOT-26 SOT-26 PKG SOT-26 Power Dissipation 26/29 XD6130/XD6131 Series ■MARKING RULE ●XD6130 series ① represents products series. SOT-26 6 ① 1 5 ② ③ 2 4 ④ ⑤ 3 MARK PRODUCT SERIES 5 XD6130******-Q ②③ represents type of detector and detect voltage. MARK 16 DETECT VOLTAGE (V) TYPE PRODUCT SERIES XD6130A161MR-Q 22 1.6 2.2 23 2.3 XD6130A231MR-Q 24 2.4 XD6130A241MR-Q 29 2.9 30 3.0 31 3.1 XD6130A311MR-Q 44 4.4 XD6130A441MR-Q 45 4.5 XD6130A451MR-Q 46 4.6 XD6130A461MR-Q XD6130A221MR-Q A XD6130A291MR-Q XD6130A301MR-Q *For another marking rule of detect voltage, please contact your local Torex sales office or representative. ④⑤ represents production lot number 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ, B1～ZZ in order. (G, I, J, O, Q, W excluded) * No character inversion used. 27/29 XD6130/XD6131 Series ■MARKING RULE ●XD6131 series ① represents products series. SOT-26 6 ① 5 ② ③ 4 ④ ⑤ 2 3 PRODUCT SERIES 5 XD6131******-Q ②③ represents type of detector and detect voltage. MARK 1 MARK A6 DETECT VOLTAGE (V) TYPE PRODUCT SERIES XD6131A161MR-Q B2 1.6 2.2 B3 2.3 XD6131A231MR-Q B4 2.4 XD6131A241MR-Q B9 2.9 XD6131A221MR-Q A XD6131A291MR-Q B0 3.0 C1 3.1 XD6131A311MR-Q D4 4.4 XD6131A441MR-Q D5 4.5 XD6131A451MR-Q D6 4.6 XD6131A461MR-Q E6 1.6 XD6131B161MR-Q F2 2.2 XD6131B221MR-Q F3 2.3 XD6131B231MR-Q F4 2.4 XD6131B241MR-Q F9 2.9 F0 3.0 H1 3.1 XD6131B311MR-Q K4 4.4 XD6131B441MR-Q K5 4.5 XD6131B451MR-Q K6 4.6 XD6131B461MR-Q B XD6131A301MR-Q XD6131B291MR-Q XD6131B301MR-Q *For another marking rule of detect voltage, please contact your local Torex sales office or representative. ④⑤ represents production lot number 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ, B1～ZZ in order. (G, I, J, O, Q, W excluded) * No character inversion used. 28/29 XD6130/XD6131 Series 1. 2. The product and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. The information in this datasheet is intended to illustrate the operation and characteristics of our products. We neither make warranties or representations with respect to the accuracy or completeness of the information contained in this datasheet nor grant any license to any intellectual property rights of ours or any third party concerning with the information in this datasheet. 3. Applicable export control laws and regulations should be complied and the procedures required by such laws and regulations should also be followed, when the product or any information contained in this datasheet is exported. 4. The product is neither intended nor warranted for use in equipment of systems which require extremely high levels of quality and/or reliability and/or a malfunction or failure which may cause loss of human life, bodily injury, serious property damage including but not limited to devices or equipment used in 1) nuclear facilities, 2) aerospace industry, 3) medical facilities, 4) automobile industry and other transportation industry and 5) safety devices and safety equipment to control combustions and explosions, excluding when specified for in-vehicle use or other uses. Do not use the product for in-vehicle use or other uses unless agreed by us in writing in advance. 5. Although we make continuous efforts to improve the quality and reliability of our products; nevertheless Semiconductors are likely to fail with a certain probability. So in order to prevent personal injury and/or property damage resulting from such failure, customers are required to incorporate adequate safety measures in their designs, such as system fail safes, redundancy and fire prevention features. 6. Our products are not designed to be Radiation-resistant. 7. Please use the product listed in this datasheet within the specified ranges. 8. We assume no responsibility for damage or loss due to abnormal use. 9. All rights reserved. No part of this datasheet may be copied or reproduced unless agreed by Torex Semiconductor Ltd in writing in advance. TOREX SEMICONDUCTOR LTD. 29/29