74HC595D

74HC595D CMOS Digital Integrated Circuits Silicon Monolithic 74HC595D 1. Functional Description • 8-Bit Shift Register/Latch (3-state) 2. General The 74HC595D is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The 74HC595D contains an 8-bit static shift register which feeds an 8-bit storage register. Shift operation is accomplished on the positive going transition of the SCK input. The output register is loaded with the contents of the shift register on the positive going transition of the RCK input. Since RCK and SCK signal are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3-state, it can be directly connected to 8-bit bus. This register can be used in serial-to-parallel conversion, data receivers, etc. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. Features (1) High speed: fMAX = 55 MHz (typ.) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25 (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V 4. Packaging SOIC16 Start of commercial production ©2016 Toshiba Corporation 1 2016-02 2016-12-27 Rev.4.0 74HC595D 5. Pin Assignment 6. Marking 7. IEC Logic Symbol ©2016 Toshiba Corporation 2 2016-12-27 Rev.4.0 74HC595D 8. Truth Table X: Don't care 9. Timing Chart ©2016 Toshiba Corporation 3 2016-12-27 Rev.4.0 74HC595D 10. System Diagram 11. Absolute Maximum Ratings (Note) Characteristics Symbol Note Rating Unit Supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to VCC + 0.5 V VOUT -0.5 to VCC + 0.5 V IIK ±20 mA Output diode current IOK ±20 mA Output current (QH') IOUT ±25 mA Output voltage Input diode current Output current (QA to QH) VCC/ground current ±35 ICC Power dissipation PD Storage temperature Tstg (Note 1) ±75 mA 500 mW -65 to 150  Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: PD derates linearly with -8 mW/ above 85  ©2016 Toshiba Corporation 4 2016-12-27 Rev.4.0 74HC595D 12. Operating Ranges (Note) Characteristics Symbol Test Condition Rating Unit Supply voltage VCC  2.0 to 6.0 V Input voltage VIN  0 to VCC V Output voltage VOUT  0 to VCC V Operating temperature Topr  -40 to 125  Input rise and fall times tr,tf  0 to 50 µs Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. ©2016 Toshiba Corporation 5 2016-12-27 Rev.4.0 74HC595D 13. Electrical Characteristics 13.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Symbol VIH VIL VOH Test Condition   VIN = VIH or VIL IOH = -20 µA VCC (V) Min Typ. Max Unit 2.0 1.50   V 4.5 3.15   6.0 4.20   2.0   0.50 4.5   1.35 6.0   1.80 2.0 1.9 2.0  4.5 4.4 4.5  6.0 5.9 6.0  High-level output voltage QH' IOH = -4 mA 4.5 4.18 4.31  IOH = -5.2 mA 6.0 5.68 5.80  High-level output voltage QA to QH IOH = -6 mA 4.5 4.18 4.31  IOH = -7.8 mA 6.0 5.68 5.80  IOL = 20 µA 2.0  0.0 0.1 4.5  0.0 0.1 Low-level output voltage VOL VIN = VIH or VIL 6.0  0.0 0.1 Low-level output voltage QH' IOL = 4 mA 4.5  0.17 0.26 IOL = 5.2 mA 6.0  0.18 0.26 Low-level output voltage QA to QH IOL = 6 mA 4.5  0.17 0.26 IOL = 7.8 mA V V V 6.0  0.18 0.26 IOZ VIN = VIH or VIL VOUT = VCC or GND 6.0   ±0.5 µA Input leakage current IIN VIN = VCC or GND 6.0   ±0.1 µA Quiescent supply current ICC VIN = VCC or GND 6.0   4.0 µA 3-state output OFF-state leakage current ©2016 Toshiba Corporation 6 2016-12-27 Rev.4.0 74HC595D 13.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Symbol VIH VIL VOH Test Condition   VIN = VIH or VIL IOH = -20 µA VCC (V) Min Max Unit 2.0 1.50  V 4.5 3.15  6.0 4.20  2.0  0.50 4.5  1.35 6.0  1.80 2.0 1.9  4.5 4.4  6.0 5.9  High-level output voltage QH' IOH = -4 mA 4.5 4.13  IOH = -5.2 mA 6.0 5.63  High-level output voltage QA to QH IOH = -6 mA 4.5 4.13  IOH = -7.8 mA 6.0 5.63  IOL = 20 µA 2.0  0.1 4.5  0.1 6.0  0.1 Low-level output voltage VOL VIN = VIH or VIL V V V Low-level output voltage QH' IOL = 4 mA 4.5  0.33 IOL = 5.2 mA 6.0  0.33 Low-level output voltage QA to QH IOL = 6 mA 4.5  0.33 IOL = 7.8 mA 6.0  0.33 ±5.0 µA 3-state output OFF-state leakage current IOZ VIN = VIH or VIL VOUT = VCC or GND 6.0  Input leakage current IIN VIN = VCC or GND 6.0  ±1.0 µA Quiescent supply current ICC VIN = VCC or GND 6.0  40.0 µA ©2016 Toshiba Corporation 7 2016-12-27 Rev.4.0 74HC595D 13.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Symbol VIH VIL VOH Test Condition   VIN = VIH or VIL IOH = -20 µA VCC (V) Min Max Unit 2.0 1.50  V 4.5 3.15  6.0 4.20  2.0  0.50 4.5  1.35 6.0  1.80 2.0 1.9  4.5 4.4  6.0 5.9  High-level output voltage QH' IOH = -4 mA 4.5 3.7  IOH = -5.2 mA 6.0 5.2  High-level output voltage QA to QH IOH = -6 mA 4.5 3.7  IOH = -7.8 mA 6.0 5.2  IOL = 20 µA 2.0  0.1 4.5  0.1 6.0  0.1 Low-level output voltage VOL VIN = VIH or VIL V V V Low-level output voltage QH' IOL = 4 mA 4.5  0.4 IOL = 5.2 mA 6.0  0.4 Low-level output voltage QA to QH IOL = 6 mA 4.5  0.4 IOL = 7.8 mA 6.0  0.4 ±10.0 µA 3-state output OFF-state leakage current IOZ VIN = VIH or VIL VOUT = VCC or GND 6.0  Input leakage current IIN VIN = VCC or GND 6.0  ±1.0 µA Quiescent supply current ICC VIN = VCC or GND 6.0  160.0 µA ©2016 Toshiba Corporation 8 2016-12-27 Rev.4.0 74HC595D 13.4. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 6 ns) Characteristics Minimum pulse width (SCK, RCK) Minimum pulse width (SCLR) Minimum setup time (SI-SCK) Minimum setup time (SCK - RCK) Minimum setup time (SCLR -RCK) Minimum hold time Minimum removal time (SCLR) Clock frequency ©2016 Toshiba Corporation Symbol Test Condition tw(L),tw(H) See 14. AC Waveform, Fig. 14.2 tw(L) tS tS tS th trem See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 f  9 VCC (V) Limit Unit 2.0 75 ns 4.5 15 6.0 13 2.0 75 4.5 15 6.0 13 2.0 50 4.5 10 6.0 9 2.0 75 4.5 15 6.0 13 2.0 100 4.5 20 6.0 17 2.0 0 4.5 0 6.0 0 2.0 50 4.5 10 6.0 9 2.0 6 4.5 30 6.0 35 ns ns ns ns ns ns MHz 2016-12-27 Rev.4.0 74HC595D 13.5. Timing Requirements (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 6 ns) Characteristics Minimum pulse width (SCK, RCK) Minimum pulse width (SCLR) Minimum setup time (SI-SCK) Minimum setup time (SCK - RCK) Minimum setup time (SCLR -RCK) Minimum hold time Minimum removal time (SCLR) Clock frequency ©2016 Toshiba Corporation Symbol Test Condition tw(L),tw(H) See 14. AC Waveform, Fig. 14.2 tw(L) tS tS tS th trem See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 f  10 VCC (V) Limit Unit 2.0 95 ns 4.5 19 6.0 16 2.0 95 4.5 19 6.0 16 2.0 65 4.5 13 6.0 11 2.0 95 4.5 19 6.0 16 2.0 125 4.5 25 6.0 21 2.0 0 4.5 0 6.0 0 2.0 65 4.5 13 6.0 11 2.0 5 4.5 25 6.0 28 ns ns ns ns ns ns MHz 2016-12-27 Rev.4.0 74HC595D 13.6. Timing Requirements (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 6 ns) Characteristics Minimum pulse width (SCK, RCK) Minimum pulse width (SCLR) Minimum setup time (SI-SCK) Minimum setup time (SCK - RCK) Minimum setup time (SCLR -RCK) Minimum hold time Minimum removal time (SCLR) Clock frequency Symbol Test Condition tw(L),tw(H) See 14. AC Waveform, Fig. 14.2 tw(L) tS tS tS th trem See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 See 14. AC Waveform, Fig. 14.2 f  VCC (V) Limit Unit 2.0 110 ns 4.5 22 6.0 19 2.0 110 4.5 22 6.0 19 2.0 75 4.5 15 6.0 13 2.0 110 4.5 22 6.0 19 2.0 150 4.5 30 6.0 26 2.0 0 4.5 0 6.0 0 2.0 75 4.5 15 6.0 13 2.0 4 4.5 20 6.0 24 ns ns ns ns ns ns MHz 13.7. AC Characteristics (Unless otherwise specified, CL = 15 pF, VCC = 5 V, Ta = 25 , Input: tr = tf = 6 ns) Characteristics Symbol Test Condition Min Typ. Max Unit ns Output transition time (QH') tTLH,tTHL See 14. AC Waveform, Fig. 14.1  4 8 Propagation delay time (SCK-QH') tPLH,tPHL See 14. AC Waveform, Fig. 14.1  12 21 Propagation delay time(SCLR-QH') tPHL See 14. AC Waveform, Fig. 14.1  15 30 Maximum clock frequency fMAX 35 55  ©2016 Toshiba Corporation  11 MHz 2016-12-27 Rev.4.0 74HC595D 13.8. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 6 ns) Characteristics Symbol Output transition time (Qn) tTLH,tTHL Output transition time (QH') tTLH,tTHL Propagation delay time (SCK-QH') tPLH,tPHL Propagation delay time (SCLR -QH') tPHL Propagation delay time (RCK-Qn) Note tPLH,tPHL Test Condition CL (pF) VCC (V) Min Typ. Max Unit See 14. AC Waveform, Fig. 14.1 50 2.0  25 60 ns 4.5  7 12 6.0  6 10 See 14. AC Waveform, Fig. 14.1 50 2.0  30 75 4.5  8 15 6.0  7 13 2.0  45 125 4.5  15 25 6.0  13 21 2.0  60 175 4.5  18 35 6.0  15 30 2.0  60 150 4.5  20 30 6.0  17 26 2.0  75 190 4.5  25 38 6.0  22 32 2.0  45 135 4.5  15 27 6.0  13 23 2.0  60 175 4.5  20 35 6.0  17 30 2.0  30 150 4.5  15 30 6.0  14 26 2.0 6 17  4.5 30 50  6.0 35 59  See 14. AC Waveform, Fig. 14.1 50 See 14. AC Waveform, Fig. 14.1 50 See 14. AC Waveform, Fig. 14.1 50 150 Output enable time tPZL,tPZH RL = 1 kΩ 50 150 Output disable time Maximum clock frequency tPLZ,tPHZ RL = 1 kΩ fMAX Input capacitance CIN Power dissipation capacitance CPD 50  (Note 1) 50 ns ns ns ns ns ns MHz   3  pF   41  pF Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation. ICC(opr) = CPD × VCC × fIN + ICC ©2016 Toshiba Corporation 12 2016-12-27 Rev.4.0 74HC595D 13.9. AC Characteristics (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 6 ns) Characteristics Symbol Output transition time (Qn) tTLH,tTHL Output transition time (QH') tTLH,tTHL Propagation delay time (SCK-QH') tPLH,tPHL Propagation delay time (SCLR -QH') tPHL Propagation delay time (RCK-Qn) tPLH,tPHL Test Condition CL (pF) VCC (V) Min Max Unit See 14. AC Waveform, Fig. 14.1 50 2.0  75 ns 4.5  15 6.0  13 See 14. AC Waveform, Fig. 14.1 50 2.0  95 4.5  19 6.0  16 2.0  155 4.5  31 6.0  26 2.0  220 4.5  44 6.0  37 2.0  190 4.5  38 6.0  32 2.0  240 4.5  48 6.0  41 2.0  170 4.5  34 6.0  29 2.0  220 4.5  44 6.0  37 2.0  190 4.5  38 6.0  33 2.0 5  4.5 25  6.0 28  See 14. AC Waveform, Fig. 14.1 50 See 14. AC Waveform, Fig. 14.1 50 See 14. AC Waveform, Fig. 14.1 50 150 Output enable time tPZL,tPZH RL = 1 kΩ 50 150 Output disable time Maximum clock frequency ©2016 Toshiba Corporation tPLZ,tPHZ fMAX RL = 1 kΩ 50  13 50 ns ns ns ns ns ns MHz 2016-12-27 Rev.4.0 74HC595D 13.10. AC Characteristics (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 6 ns) Characteristics Symbol Output transition time (Qn) tTLH,tTHL Output transition time (QH') tTLH,tTHL Propagation delay time (SCK-QH') tPLH,tPHL Propagation delay time (SCLR -QH') tPHL Propagation delay time (RCK-Qn) tPLH,tPHL Test Condition CL (pF) VCC (V) Min Max Unit See 14. AC Waveform, Fig. 14.1 50 2.0  90 ns 4.5  18 6.0  15 See 14. AC Waveform, Fig. 14.1 50 2.0  115 4.5  23 6.0  20 2.0  240 4.5  48 6.0  31 2.0  265 4.5  53 6.0  45 2.0  265 4.5  53 6.0  45 2.0  285 4.5  57 6.0  48 2.0  225 4.5  45 6.0  38 2.0  265 4.5  53 6.0  45 2.0  225 4.5  45 6.0  38 2.0 4  4.5 20  6.0 24  See 14. AC Waveform, Fig. 14.1 50 See 14. AC Waveform, Fig. 14.1 50 See 14. AC Waveform, Fig. 14.1 50 150 Output enable time tPZL,tPZH RL = 1 kΩ 50 150 Output disable time Maximum clock frequency ©2016 Toshiba Corporation tPLZ,tPHZ fMAX RL = 1 kΩ 50  14 50 ns ns ns ns ns ns MHz 2016-12-27 Rev.4.0 74HC595D 14. AC Waveform Fig. 14.1 tTLH, tTHL, tPLH, tPHL Fig. 14.2 tw, ts, th, trem ©2016 Toshiba Corporation 15 2016-12-27 Rev.4.0 74HC595D Package Dimensions Unit: mm Weight: 0.15 g (typ.) Package Name(s) Nickname: SOIC16 ©2016 Toshiba Corporation 16 2016-12-27 Rev.4.0 74HC595D RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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