SSM3J334R,LF(T

SSM3J334R TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSVI) SSM3J334R ○Power Management Switch Applications Unit: mm • Low ON-resistance: RDS(ON) = 71 mΩ (max) (@VGS = -10 V) RDS(ON) = 105 mΩ (max) (@VGS = -4.5 V) RDS(ON) = 136 mΩ (max) (@VGS = -4.0 V) Absolute Maximum Ratings (Ta = 25°C) Characteristic Drain-Source voltage Gate-Source voltage Drain current Symbol Rating Unit VDSS -30 V VGSS ± 20 V DC ID (Note 1) -4 Pulse IDP (Note 1,2) -16 PD (Note 3) Power dissipation A 1 t < 10s W 2 Channel temperature Tch 150 °C Storage temperature range Tstg −55 to 150 °C Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: The channel temperature should not exceed 150°C during use. Note 2: PW ≤ 1ms, Duty ≤ 1％ Note 3: Mounted on a FR4 board. (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2) Marking SOT-23F 1: Gate 2: Source 3: Drain JEDEC ― JEITA ― TOSHIBA Weight: 2-3Z1S 11 mg (typ.) Equivalent Circuit (Top View) 3 3 KFL 1 2 1 2 Start of commercial production 2010-08 © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation 1 2018-10-04 SSM3J334R Electrical Characteristics (Ta = 25°C) Characteristic Drain-Source breakdown voltage Symbol Test Conditions Min Typ. Max Unit -30   V V (BR) DSS ID = -10 mA, VGS = 0 V -21   V Drain cut-off current IDSS VDS = -30 V, VGS = 0 V   -1 µA Gate leakage current IGSS VGS = ±16 V, VDS = 0 V   ±10 µA -0.8  -2.0 V 2.3 4.6  S V (BR) DSX ID = -10 mA, VGS = 10 V Gate threshold voltage Vth Forward transfer admittance Yfs Drain–source ON-resistance RDS (ON) Input capacitance VDS = -10 V, ID = -100 µA VDS = -10 V, ID = -1.0 A (Note 4) ID = -3.0 A, VGS = -10 V (Note 4)  54 71 ID = -2.0 A, VGS = -4.5 V (Note 4)  80 105 ID = -1.0 A, VGS = -4.0 V (Note 4)  89 136  280   55   40   Ciss Output capacitance Coss Reverse transfer capacitance Crss Switching time .(Note 5) Turn-on time ton Turn-off time toff Total Gate Charge VDS = -15 V, VGS = 0 V f = 1 MHz VDD = -15 V, ID = -1.0 A VGS = 0 to -4.5 V, RG = 10 Ω Qg Gate-Source Charge Qgs1 Gate-Drain Charge Qgd Drain-Source forward voltage VDSF VDD = -15 V, ID = -4.0 A, VGS = -10 V ID = 4.0 A, VGS = 0 V (Note 4) 13   22   5.9   0.8   1.2   0.9 1.2 mΩ pF ns nC V Note4: Pulse test Note5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain-source breakdown voltage is lowered in this mode. Switching Time Test Circuit (a) Test Circuit (b) VIN 0V 90% OUT 0 IN 10% −4.5 V RG −4.5V 10 µs RL (c) VOUT VDS (ON) 90% VDD VDD = -15 V RG = 10 Ω Duty ≤ 1% VIN: tr, tf < 5 ns Common Source Ta = 25°C 10% VDD tr ton tf toff Notice on Usage Let Vth be the voltage applied between gate and source that causes the drain current (ID) to be low (-100μA for the SSM3J334R). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower than Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on). Take this into consideration when using the device. Handling Precaution When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. Thermal resistance Rth (ch-a) and power dissipation PD vary depending on board material, board area, board thickness and pad area. When using this device, please take heat dissipation into consideration © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation 2 2018-10-04 SSM3J334R ID – VDS ID – VGS -10 -100 -4.5 V -10 V Common Source VDS = -10 V VGS = -4.0 V -10 Pulse test Drain current ID Drain current ID (A) (A) -8 -6 -4 -2 Common Source Ta = 25 °C Pulse test -0.5 -1.0 Drain–source voltage VDS Ta = 100 °C -0.01 −25 °C 25 °C -0.0001 0 -2.0 -1.5 -0.1 -0.001 0 0 -1 -1.0 (V) -4.0 (V) RDS (ON) – VGS 200 ID = -1.0 A Common Source Pulse test Drain–source ON-resistance RDS (ON) (mΩ) Drain–source ON-resistance RDS (ON) (mΩ) -3.0 Gate–source voltage VGS RDS (ON) – VGS 200 -2.0 150 100 Ta = 100 °C 25 °C 50 ID = -2.0 A Common Source Pulse test 150 100 Ta = 100 °C 25 °C 50 − 25 °C − 25 °C 0 0 -4 -8 -12 -16 Gate–source voltage VGS 0 -20 0 (V) -4 Pulse test Drain–source ON-resistance RDS (ON) (mΩ) Drain–source ON-resistance RDS (ON) (mΩ) Common Source Ta = 25 °C 150 -4.0 V 100 -4.5 V VGS = -10 V 0 0 -2.0 -4.0 -8.0 -6.0 Drain current ID -20 (V) RDS (ON) – Ta 200 50 -16 Gate–source voltage VGS RDS (ON) – ID 200 -12 -8 100 -2.0 A / -4.5 V -3.0 A / -10 V 50 0 50 100 150 Ambient temperature Ta (°C) (A) © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation ID = -1.0 A / VGS = -4.0 V 150 0 −50 -10.0 Common Source Pulse test 3 2018-10-04 SSM3J334R Vth – Ta |Yfs| – ID (S) Common Source VDS = -10 V ID = -100 μA Forward transfer admittance Yfs Gate threshold voltage Vth (V) -2.0 -1.6 -1.2 -0.8 -0.4 0 −50 0 50 100 150 100 Common Source VDS = -10 V 30 Ta = 25 °C Pulse test 10 3.0 1.0 0.3 0.1 -0.01 C – VDS (V) Ciss Gate–source voltage VGS Capacitance C (pF) 300 100 50 Coss 30 Crss 10 5 Common Source 3 Ta = 25 °C f = 1 MHz VGS = 0 V -8 VDD = -15 V -6 -1 -10 -100 Drain–source voltage VDS -2 Common Source ID = -4.0 A Ta = 25 °C 2 4 6 Total Gate Charge (A) Drain reverse current IDR 10 toff tf ton 10 tr -0.01 Qg (nC) Common Source VGS = 0 V Pulse test D IDR G S 1 0.1 25 °C 0.01 100 °C 1 -0.001 8 IDR – VDS 100 Common Source VDD = -15 V VGS = 0 to -4.5 V Ta = 25 °C RG = 10Ω 1000 0 (V) t – ID 10000 VDD = -24 V -4 0 1 -0.1 (ns) (A) -10 500 - -100 Dynamic Input Characteristic 1000 Switching time t -10 Drain current ID Ambient temperature Ta (°C) 100 -1 -0.1 -0.1 Drain current ID -1 0.001 0 -10 0.4 0.6 0.8 1.0 Drain–source voltage VDS (A) © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation 0.2 −25 °C 4 1.2 (V) 2018-10-04 SSM3J334R rth – tw P D – Ta 1600 a: Mounted on FR4 board (25.4mm × 25.4mm × 1.6mm , Cu Pad: 645 mm2) b: Mounted on FR4 board (25.4mm × 25.4mm × 1.6mm , Cu Pad: 0.72 mm2 ×3) b Power dissipation PD (mW) Transient thermal impedance rth (°C/W ) 1000 a 100 10 Single pulse a. Mounted on FR4 board (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2) b. Mounted on FR4 board (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.72 mm2 ×3) 1 0.001 0.01 0.1 1 10 100 a 800 b 400 0 -40 1000 -20 0 20 40 60 80 100 120 140 160 Ambient temperature Ta (°C) Pulse width tw (s) © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation 1200 5 2018-10-04 SSM3J334R RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”. • TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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