TA8552AFN

TA8552AFN TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA8552AFN PLL Data Synchronizer For DAT Streamer The TA8552AFN is PLL data synchronizer for digital audio tape (DAT) strteamer, digital data storage (DDS). Features · The TA8552AFN incorporates edge detector, data synchronizer, and latch for data separator. Also the TA8552AFN is available to correspond to ×1, ×2 and ×3 of data transfer rates by adjusting external devices. The data synchronizer is avalable to correspond to ±7% variation of data transfer rate. By employing full differential signal processing in PLL loop, the TA8552AFN eliminates the influence of external noise. Fast & stable locking is realized by switching between the frequency detective mode and the phase detective mode. Operating power supply voltage range: 4.5V to 5.5V Small package; SSOP30−P−300−0.65 NC RVCO1 AGND2 CVCO1 RVCO2 CVCO2 AVCC2 TMON1 TMON2 XTMON2 V TTLO MODESEL TSTCPMP RD XRD · · Weight: 0.17g (typ.) Pin Connectoion Top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COB COA AGND1 RCP2 RCP1 AVCC1 DETSEL TSTCLK DVCC3 PBDT PBCK DGND3 TSTSEL2 REFCLK TSTSEL1 · · Handle with care to prevent devices from deterioration by static electricity. 1 2002-10-30 TA8552AFN Block Diagram DETSEL MODESEL RCP1 RCP2 REFCLK Frequency detecter Edge detecter Detecter selector Phase detecter Selecter 1 / 2 counter Charge − pump COA RD XRD ECL / TTL VCO COB Delay (2) D Q PBCK PBDT TSTCLK TSTSEL1 RVCO1 RVCO2 CVCO1 CVCO2 TSTSEL2 2 2002-10-30 TA8552AFN Pin Function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name NC RVCO1 AGND2 CVCO1 RVCO2 CVCO2 AVCC2 TMON1 TMON2 XTMON2 V_TTLO MODESEL TSTCPMP RD Function NC terminal. (open at normal use) VCO adjusting terminal. Connect an external resistor (RVCO1) between VCC. Analog ground for VCO. VCO adjusting terminal. Connect a capacitor (CVCO) between this pin and pin6. VCO adjusting terminal. Connect an external resistor (RVCO2) between VCC. VCO adjusting terminal. Connect a capacitor (CVCO) between this pin and pin4. Analog power supply voltage for VCO. NC terminal (open at normal use) NC terminal (open at normal use) NC terminal (open at normal use) Input terminal for TTL voh (high voltage level of pin20, and pin21 output) limitting. Input terminal for switching the normal mode and the serching mode. (H: Normal mode, L: Serching mode) NC terminal. (open at normal use.) Input terminal of data (normal phase) Input terminal of data (reverse phase). (this terminal is active when TSTSEL1 = L and TSTSEL2 = H. Otherelse, short with VCC.) Input terminal for test mode selecting. (refer the chapter of "test mode") Reference clock input of frequency synchronizer. Input terminal for test mode selecting. (refer the chapter of "test mode") Digital ground for TTL output. Output terminal of data latch clock. Output terminal of data latch. Digital power supply voltage for TTL output. Input terminal of ×1 / 2 vco test clock. (short with VCC at mormal use.) Input terminal for switching the frequency detective mode and the phase detective mode. (L : The frequency detective mode H : The phase detective mode.) Analog power supply voltage. In / Out ― ― ― ― ― ― ― ― ― ― ― TTL-in ― ECL-in or TTL-in (ECL-in) ― TTL-in ― ― TTL-out TTL-out ― ― 15 16 17 18 19 20 21 22 23 XRD TSTSEL1 REFCLK TSTSEL2 DGND3 PBCK PBDT DVCC3 TSTCLK 24 DETSEL TTL-in ― 25 AVCC1 3 2002-10-30 TA8552AFN Pin No. 26 27 28 29 30 Pin Name RCP1 RCP2 AGND1 COA COB Function Adjusting terminal of charge pump at normal mode. Connect an external resistor (Rcp1) between GND. Adjusting terminal of charge pump at normal mode. Connect an external resistor (Rcp2) between GND. Analog ground Connecting terminal of loop filter. Connect an external loop filter between this pin and 30pin. Connecting terminal of loop filter. Connect an external loop filter between this pin and 29pin. In / Out ― ― ― ― ― Absolute Maximum Rating (Ta = 27°C) Parameter Supply voltage Input voltage Output voltage Storage temperature Symbol AVCC VIN VOUT Tstg Rating 7 -0.3~VCC+0.3 -0.3~VCC+0.3 −55~150 Unit V V V °C Recommended Operating Condition Parameter Supply voltage Operation temperature Symbol AVCC Topr Condition ― ― Min. 4.5 -5 Typ. 5 ― Max. 5.5 75 Unit V °C Power Supply (unless otherwise specifide, Ta = 27°C, VCC = 5.0V) Parameter Supply current Symbol IPLCC Condition TSTSEL1 = H, TSTSEL2 = L DETSEL = L, MODSEL = H Min. Typ. Max. 65 Unit mA 4 2002-10-30 TA8552AFN Electrical Characteristic (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter High level input voltage (1) Low level input voltage (1) High level input current (1) Low level input current (1) High level input voltage (2) Low level input voltage (2) High level input current (2) Low level input current (2) High level output voltage (1) Low level output voltage (1) Output rise time (1) Output fall time (1) Input voltage range to VTTLO terminal Symbol VIH VIL IIH IIL VIHE VILE IIHE IILE VOH VOL TOR TOF VTTLO Test Circuit ― ― ― ― ― ― ― ― ― ― ― ― ― Test Condition TTL input pins TTL input pins TTL input pins TTL input pins ECL input pins ECL input pins ECL input pins ECL input pins TTL output pins IOH = 400µA TTL output pins IOL = 4mA TTL output pins 1.5V to 3.5V CL≤30pF TTL output pins 3.5V to 1.5V CL≤30pF *1 *1 Min. 2.0 ― ― ― VCC -1.0 ― ― ― VTTLO -0.2 ― ― ― 2.7 ― ― ― ― Typ. ― ― ― ― ― ― ― ― Max. ― 0.4 20 -360 ― VCC -1.5 2.0 1.6 VTTLO +0.2 1.0 5 5 3.3 Unit V V µA µA V V mA mA V V ns ns V *1; Design guaranteed value. Charge Pump (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Range of output current setting Accuracy of output current setting Leak current Symbol ICP Test Circuit ― ― ― ― Condition At normal mode At serching mode At normal mode At serching mode Between COA pin and COB pin, at high impedance *1 *2 Min. 30 ― -6 -8 -3.5 Typ. ― ― ― ― Max. ― 800 +6 +8 +3.5 Unit µA Iacu Ireak % µA *1; Output current is set by an external resistor (Rcp1), as following; 2×1.3 / Rcp1 = (output current at normal mode). *2; Output current is set by external resisters (Rcp1, Rcp2), as following; 2×1.3 / Rcp1+8×1.3 / Rcp2 = (output current at search mode). (Note) The above values are all at open loop. 5 2002-10-30 TA8552AFN VCO (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter Input voltage of VCO (V (COB -COA)) Symbol Test Circuit ― Condition RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF fVCO = 28.224MHz RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF V (COB -COA) = 0.6V RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF V (COB -COA) = -0.6V RVCO1 = 3.75 kΩ RVCO2 = 1.21 kΩ CVCO = 39pF Voltage (COB -COA) Excursion 0.3V to -0.3V PBCK pin at ×3 transfer rate Min. Typ. Max. Unit VVCO *1 0.25 0.45 V Upper limitation of VCO frequency fmax ― *1 29.5 MHz Lower limitation of VCO frequency fmin ― *1 23.5 MHz Control gain (F / V) GVCO ― *1 6 7.7 MHz / V VCO jitter tjit ― *2 300 ps *1; CVCO inclides the package capacitance. *2; Design guaranteed value. (Note) The above values are all at open loop, measured at the PBCK pin Closed Loop (unless otherwise specified, Ta = 27°C, VCC = 5.0V) Parameter VCO jitter in closed loop VCO jitter in closed loop Symbol tjit2N tjit2S Test Circuit ― ― Condition In search mode lock to REFCLK In normal mode lock to RD Min. Typ. Max. 0.5 0.4 Unit ns ns Values of external parts are (RVCO1 = 3.75 kΩ, RVCO2 = 1.21 kΩ, CVCO = 39pF (including storage capacitor), RCP1 = 8.25k, RCP2 = 30.1k). 6 2002-10-30 TA8552AFN Character Of VCO The connection of input voltage and output frequency of VCO (measured at PBCK after the 1 / 2 frequency counter) is written as following; 1 × I + I  8×C vco × DV O ofs (Vin>2Vop) fvco = I I 1 ( O × Vin + O + Iofs ) 8×C vco ×DV 4Vop 2 1 ×I 8×C vco × DV ofs (2Vop>Vin> -2Vop) (Vin< -2Vop) Where; Cvco is an external capacitor between 4pin and 6pin, ∆V = 0.35V, Vop = 0.275V, Vin is the input voltage of VCO (differential), IO = 3×1.3 / Rvco1, and lofs = 2×1.3 / Rvco2･ fVCO I0 + IOFS 8 CVCO ∆V I0 + IOFS 2 8 CVCO ∆V IOFS 8 CVCO ∆V − 2 Vop 0 2 Vop VIN So, the gain of VCO is defined as following (at PBCK); I 1 ×O 8×Cvco ×DV 4Vop 7 2002-10-30 TA8552AFN And, upper limitation f upper, and lower limitation of VCO frequency f lower is defined as follows; fupper = (IO+Iofs) / 8Cvco ∆V flower =Iofs / 8Cvco ∆V I 0 can be determined by selecting Rvco1, and I ofs can by Rvco2. So, you can independently determine the gain of VCO, upper limitation and lower limitation of VCO frequency by selecting Cvco, Rvco1, and Rvco2･ 【Example】When, Cvco = 22.1pF, Rvco1 = 2.6kΩ, Rvco2 = 2.6 kΩ, 1.3 / (2.6´10 3 )´3 8´22.1´10 -12 ´0.35 ´ 4´0.275 Gain of VCO ; = 22MHz / V Upper limitation of VCO frequency ; 1.3 / (2.6´10 3 )´3 +1.3 / (2.6´10 3 )´2 8´ 22.1´10 -12 ´0.35 = 40.4MHz Lower limitation of VCO frequency ; 1.3 / (2.6´10 3 )´ 2 8´ 22.1´10 -12 ´0.35 = 16.2MHz f 40.4MHz Gain; 22MHz / V 28.224MHz 16.2MHz V − 0.55V 0 + 0.55V 8 2002-10-30 TA8552AFN Function Description: The angular frequency (ωn) and dumping facter (ζ) are adjusted by external devices. The setting procedure is shown as following. The setting conditions to lock PLL inside a constant time; · · · Data transfer rate: 28.224Mbps (fM = 28.244MHz) The capturing signal of PLL: The rectangle wave of 14.112MHz (data pattern is 101010...), The term of this data is continuous 180 bits. The capturing time of PLL: 1 / (14.114×106) ×180 = 12.75×10-6s 12.75×10-6×0.9 = 11.5µs (this 0.9 is a factor of margin.) 【The transfer function of PLL】 Phase comparater θi + − θo 1 / 2 counter 1/2 Kf Loop filter Z (s) VCO K0 / s CL1 RL CL2 Z (s) The transfer function (F (S)), the angular frequency (ωn), and the dumping facter (ζ) of the above composition are defined as following (However CL2 is ignored as CL2≪CL1): K )1/ 2 CL1 wn = ( z= RL CL1wn 2 【Calculation of ζ】 The dumping factor (ζ) is set to 0.7 as the most stable response characteristic. Besides ωn t is assumed to set as 6. 9 2002-10-30 TA8552AFN 【Calculation of ωn】 The capturing time of PLL is expected as above 11.5µs. Therefore (ωn) is deternimated as the following: ωn = 6 / (11.5×10-6) = 552krad / s 【Calculation of K0 (VCO control gain)】 K0 is determined as the following; K0 = 40MHz / V = 251.3Mrad / V 【Calculation of Kf (phase detector gain)】 Kf is estimated as the following (the current of charge pump is set as ±50µA.) 1 1 ･ ×50×10-6 = 3.98×10-6(A / rad) 2 2F Kf = The current of charge pump (Ichp) is set by an external resister (Rcp1), connected with Rcp1 (26pin). When "H"level voltage inputs to MODESEL (12pin), Ichp is set as the following: Ichp = 2×1.3 / RCP1→RCP1 = 2×1.3 / Ichp = 2×1.3 / 50×10-6 = 52×103Ω Therefore, when RCP1 is 52kΩ, Ichp is set as ±50µA 【Calculation of external devices of loop-filter】 Kf´K 0 3.98´10 -6 ´251.3´10 6 = = 1800 ´ 10 - 6 F 2wn 2´ (522´10 3 )2 CL1 = RL = 2z 2´0.7 = = 1.5 ´ 10 3 W CL1 wn -12 ´522´10 3 1800´10 CL2 = CL1 / 10 = 180pF 10 2002-10-30 TA8552AFN Modesel Switching Function The TA8552AFN has a function to correspond with the high-speed serching mode of DAT streamer. In the searching mode, the data transfer rate will shift with small percentage error. The TA8552AFN is available to solve this problem by extending the lock-in-range (∆ωL). In the serching mode the current of charge pump will be increased to raise the phase detecter gain, then the lock-in-range (∆ωL) will extend. This function is selected by modesel (12pin). (H: Normal mode / L: Searching mode) 【Calculation of the charge pump's current in the searching mode】 The charge pump's current in the searching mode is estimated as the following (the shift rateX of data, transfer is assumed as X = 7% in this example); 6 f ´ X´2p I chp = M ´ 8p = 28.224 ´10 ´0.07 ´2´3.14 ´ 8 ´ 3.14 = 830 ´ 10 - 6 (A) R´K 0 3 ´251.3 ´10 6 1.5´10 When "L" level voltage inputs to modesel (12pin), the charge pump's current (Ichp) increases. In the normal mode, the charge pump's current (Icp1) is set by an external resister (Rcp1). And in the searching mode, another current (Icp2), is set by an external resisiter (Rcp2), adds to Icp1. This (Rcp2) is the resister to be connected with RCP2 (27pin) The additional current (Icp2) is determined by the following: Icp2 = 8×1.3 / Rcp2 Therefore, Rcp2 is estimated as the following: R cp2 = 8´1.3 = 13.3 ´ 10 3 W - 6 - 50´10 - 6 830´10 Modesel function is summarized by the followings Mode Modesel (12pin) Charge pump current Ichp Setting definition Normal Mode H Icp1 2×1.3 / Rcp1 High-speed Searghing Mode L Icp1+Icp2 2×1.3 / Rcp1+8×1.3 / Rcp2 11 2002-10-30 TA8552AFN Timing Chart Of Latch 4.704 MHz, 360 pulse for x1−Speed 9.408 MHz, 360 pulse for x2−Speed 14.112 MHz, 360 pulse for x3−Speed Synk−byte Data D1 D2 D3 D4 D5 D6 D7 D8 D9 RD Locked by PLL Out of edge det. PBCK Out of latch 12 2002-10-30 TA8552AFN (Note) Test Monitor Output Terminal Tstsel 1 L H L H 2 L L H H Datainput TTL input from 14pin (RD) TTL input from 14pin (RD) ECL input from 14pin (RD) and 15pin (XRD) TTL input from 14pin (RD) Function ― PBCK (20pin) & PBDT (21pin) becomes disable ― The internal PLL becomes disable, and the external clock from tstclk (23pin) becomes enable as input data signal. (Note) ● W e commend the use of this IC under the comdition of ECL input from 14pin (RD) and 15pin (XRD) when (TSTSEL1, TSTSEL2) = (L, H) ● It is possible of the use of TTL input from 14pin (RD) when (TSTSEL1, TSTSEL2) = (L, L) 13 2002-10-30 TA8552AFN Application Diagram When the data transfer rate is 28.224Mbps, the application diagram is shown below. 1500pF CL2 RCP2 13.3kΩ CL1 1.5kΩ 0.1µF VCC RVCO1 NC1 1 2 30 COB 29 28 27 26 25 24 RUCO1 2.7kΩ GND 3 AGND2 22.1pF COA AGND1 GND RCP2 RCP1 AVCC1 VCC H / phase comparate mode L / frequency comparate mode 1500pF RCP1 52kΩ CVCO1 CVCO RVCO2 CVCO2 4 5 6 7 8 9 10 11 12 0.1µF VCC RVCO2 2.7kΩ VCC AVCC2 DETSEL TMON1 TMON2 XMON2 H / normal L / search 3.3V V TTL0 23 TSTCLK 22 21 20 19 18 17 16 DVCC3 PBDT PBCK VCC OUT OUT GND MODESEL TSTCPMP 13 RD XRD 14 15 DGND3 TSTSEL2 REFCLK TSTSEL1 TTL in 28.224MHz TTL in VCC Data in ECL in or Xdata in Data in Test set 1 Test set 2 1800pF RL 180pF 14 2002-10-30 TA8552AFN Package Dimensions Weight: 0.17g (typ.) 15 2002-10-30 TA8552AFN RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 16 2002-10-30