TB62206FG
TOSHIBA BiCD Process IC Silicon Monolithic
TB62206FG
BiCD PWM 2−Phase Bipolar Stepping Motor Driver
The TB62206FG is designed to drive a 2−phase bipolar
stepping motor. With BiCD process technology, this device
enables output withstand voltage of 40 V and maximum current
of 1.8 A to be achieved.
Features
•
Bipolar stepping motor driver IC
•
Internal PWM current control
•
2−phase/1−2 phase excitation is available
•
Monolithic BiCD IC
Weight: 0.79 g (typ.)
DMOS FET used for output power transistor
•
High voltage output and High current: 40 V/1.8 A (max)
•
On−chip thermal shutdown circuit, overcurrent protection circuit and power−on reset circuit (POR)
•
Package: HSOP20−P−450−1.00
Pin Assignment
.
CR
1
20 TORQUE
VDD
2
19 OUT B
Vref A
3
18 ENABLE B
Vref B
4
17 ENABLE A
RS B
5
16 OUT B
FIN (GND)
RS A
6
FIN (GND)
15 OUT A
VM 7
14 PHASE B
Ccp C 8
13 PHASE A
Ccp B
12 OUT A
9
Ccp A 10
11 STANDBY
Note:
Please be careful about the thermal conditions during use, like operating current, PCB conditions, ambient temperature,
etc.
This IC may be broken if it is soldered at wrongly rotated position because high voltage is applied to low voltage part.
Please be sure that 1PIN position and PCB pattern is correct before soldering process.
© 2014 TOSHIBA Corporation
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TB62206FG
Block Diagram
STANDBY
ENABLE A
VDD
Input logic
ENABLE B
PHASE A
Chopper OSC
PHASE B
CR
OSC
TORQUE
Vref
CR-CLK
Converter
Current Level Set
Torque Control
Current Feedback (×2)
RS
VRS
Output Control
(Mixed Decay Control)
RS COMP
VM
VM
Ccp C
Ccp B
Ccp A
STANDBY
ISD
Charge
Pump
Unit
Output
(H-Bridge)
×2
ENABLE
VM
TSD
VDDR/VMR
Protect
VDD
Protection Unit
Stepping
motor
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TB62206FG
Function Table－Output
X:
Phase
Enable
OUT X
OUT X
X
L
OFF
OFF
H
H
H
L
L
H
L
H
Don't care
Others
Pin Name
H
L
Notes
ENABLE X
Output
Output OFF
PHASE X
OUT X: H
OUT X : H
In high level, current flows OUT X → OUT X
STANDBY
Motor operation enable
All functions of the
IC stopped
When STANDBY = L, output stopped while
charge pomp stopped.
TORQUE
100%
71%
Output is OFF regardless of its phase’s
state.
High-level
Protection Function
(1)
Thermal shutdown circuit
While Tj = 150°C, all outputs are OFF. To turn-on, change the state of the STANDBY pin in the
order of H, L, H.
It has temperature hysteresis to prevent the output from oscillating. (∆T = 35°C)
(2)
POR (Power-On Reset Circuit: VM and VDD power supply monitor circuit)
Output is forcibly turned off until VM and VDD reach their specified levels.
(3)
ISD
Output is forcibly turned off when current higher than the specified level flows in the output block.
To turn-on, change the state of the STANDBY pin in the order of H, L, H.
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TB62206FG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Logic supply voltage
VDD
7
V
Motor supply voltage
VM
40
V
IOUT
1.8
A
Current detect pin voltage
VRS
VM ± 4.5 V
V
Charge pump pin maximum voltage
(CCP1 pin)
VH
VM + 7.0
V
Logic input voltage
VIN
to VDD + 0.4
V
Output current
(Note 1)
(Note 2)
(Note 3)
Power dissipation
(Note 4)
1.4
PD
W
3.2
Operating temperature
Topr
−40 to 85
°C
Storage temperature
Tstg
−55 to 150
°C
Junction temperature
Tj
150
°C
Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.5 A or
less per phase.
The current value maybe controlled according to the ambient temperature or board conditions.
Note 2: Input 7 V or less as VIN
Note 3: Measured for the IC only. (Ta = 25°C)
Note 4: Measured when mounted on the board. (Ta = 25°C)
Ta: IC ambient temperature
Topr: IC ambient temperature when starting operation
Tj: IC chip temperature during operation Tj (max) is controlled by TSD (thermal shut down circuit)
Operating Range (Ta = 0 to 85°C, (Note 5))
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
Power supply voltage
VDD
4.5
5.0
5.5
V
Motor supply voltage
VM
VDD = 5.0 V, Ccp1 = 0.22 µF,
Ccp2 = 0.02 µF
13
24
35
V
Ta = 25°C, per phase
1.2
1.5
A
Output current
IOUT (1)
GND
VDD
V
fPHASE
VDD = 5.0 V
1.0
150
kHz
Chopping frequency
fchop
VDD = 5.0 V
50
100
150
kHz
Vref reference voltage
Vref
VM = 24 V, Torque = 100%
GND
3.0
4.0
V
Current detect pin voltage
VRS
VDD = 5.0 V
0
±1.0
±4.5
V
Logic input voltage
Phase signal input frequency
VIN
Note 5: Please design in consideration of the maximum current so that Tj does not exceed 120°C.
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TB62206FG
Electrical Characteristics 1 (unless otherwise specified, Ta = 25°C, VDD = 5 V, VM = 24 V)
Characteristics
Symbol
Test
Circuit
Min
Typ.
Max
2.0
VDD
VDD
+ 0.4
GND
− 0.4
GND
0.8
Data input pins
200
400
700
Data input pin which contains
pull-down resistance
35
50
75
1.0
1.0
VDD = 5 V, all inputs connected
to ground, Logic, output all off
1.0
2.0
3.0
IDD2
Output OPEN, fPHASE = 1.0 kHz
LOGIC ACTIVE, VDD = 5 V,
ChargePump = charged
1.0
2.5
3.5
IM1
Output OPEN, all inputs
connected to ground, Logic,
output all off, ChargePump =
no operation
1.0
2.0
3.0
IM2
OUT OPEN, fPHASE = 1 kHz
LOGIC ACTIVE, VDD = 5 V,
VM = 24 V, Output off,
ChargePump = charged
2.0
4.0
5.0
OUT OPEN, fPHASE = 4 kHz
LOGIC ACTIVE, 100 kHz
chopping (emulation), Output
OPEN,
ChargePump = charged
10
13
HIGH
VIN (H)
LOW
VIN (L)
DC
Input voltage
Input hysteresis voltage
VIN (HIS)
DC
IIN (H)
Input current
IIN (H)
Data input pin which contains
no pull-down resistance
IDD1
DC
Power dissipation (VM pin)
Data input pins
DC
IIN (L)
Power dissipation (VDD pin)
Test Condition
DC
IM3
Unit
V
mV
µA
mA
mA
Output standby current
Upper
DC
DC
VRS = VM = 24 V, VOUT = 0 V,
STANDBY = H, PHASE = H
−200
−150
µA
Output bias current
Upper
IOB
DC
VOUT = 0 V, STANDBY = H
−100
−50
µA
DC
VRS = VM = CcpA = VOUT = 24
V, LOGIC IN = ALL = L
1.0
µA
Vref = 3.0 V, Vref (Gain) = 1/5.0
TORQUE = (H) = 100% set
100
Vref = 3.0 V, Vref (Gain) = 1/5.0
TORQUE = (L) = 71% set
66
71
76
Output leakage current
Comparator reference
voltage ratio
Lower
IOL
HIGH
(reference)
VRS (H)
LOW
VRS (L)
DC
%
Output current differential
∆IOUT1
DC
Differences between output
current channels
−5
5
%
Output current setting differential
∆IOUT2
DC
IOUT = 1000 mA
−5
5
%
IRS
DC
VRS = 24 V, VM = 24 V
STANDBY = L
1
2
µA
RON (D-S) 1
IOUT = 1.0 A, VDD = 5.0 V
Tj = 25°C, Drain-Source
0.5
0.6
RON (S-D) 1
IOUT = 1.0 A, VDD = 5.0 V
Tj = 25°C, Source-Drain
0.5
0.6
RON (D-S) 2
IOUT = 1.0 A, VDD = 5.0 V
Tj = 105°C, Drain-Source
0.6
0.75
RON (S-D) 2
IOUT = 1.0 A, VDD = 5.0 V
Tj = 105°C, Source-Drain
0.6
0.75
RS pin current
Output transistor drain-source
ON-resistance
DC
5
Ω
2014-10-01
TB62206FG
Electrical Characteristics 2 (unless otherwise specified, Ta = 25°C, VDD = 5 V, VM = 24 V)
Symbol
Test
Circuit
Vref input voltage
Vref
DC
Vref input current
Iref
Characteristics
Min
Typ.
Max
Unit
VM = 24 V, VDD = 5 V,
STANDBY = H, Output on,
PHASE = 1 kHz
GND
4.0
V
DC
STANDBY = H, Output on,
VM = 24 V, VDD = 5 V,
Vref = 3.0 V
20
35
50
µA
Vref (GAIN)
DC
VM = 24 V, VDD = 5 V,
STANDBY = H, Output on,
Vref = 0.0 to 4.0 V
1/4.8
1/5.0
1/5.2
TjTSD
DC
VDD = 5 V, VM = 24 V
130
170
°C
∆TjTSD
DC
TjTSD = 130 to 170°C
TjTSD
− 50
TjTSD
− 35
TjTSD
− 20
°C
VDD return voltage
VDDR
DC
VM = 24 V, STANDBY = H
2.0
3.0
4.0
V
VM return voltage
VMR
DC
VDD = 5 V, STANDBY = H
8.0
9.0
10
V
Over current protected circuit
operation current
(Note 2)
ISD
VDD = 5 V, VM = 24 V
3.0
A
Vref attenuation ratio
TSD temperature
(Note 1)
TSD return temperature difference
(Note 1)
Test Condition
Note 1: Thermal shut down (TSD) circuit
When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal
reset circuit is activated switching the outputs of both motors to off.
When the temperature is set between 130 (min) to 170°C (max), the TSD circuit operates.
When the TSD circuit is activated, the charge pump is halted, and TROTECT pin outputs VDD voltage.
Even if the TSD circuit is activated and STANDBY goes H → L → H instantaneously, the IC is not reset
until the IC junction temperature drops −20°C (typ.) below the TSD operating temperature (hysteresis
function).
Note 2: Overcurrent protection circuit
When current exceeding the specified value flows to the output, the internal reset circuit is activated, and the
ISD turns off the output.
Until the STANDBY signal goes Low to High, the overcurrent protection circuit remains activated.
During ISD, IC turns STANDBY mode and the charge pump halts.
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TB62206FG
AC Electrical Characteristics (Ta = 25°C, VM = 24 V, VDD = 5 V, 6.8 mH/5.7 Ω)
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
fPHASE
AC
166
kHz
tw (tCLK)
100
twp
50
twn
AC
50
tr
100
tf
100
tpLH
PHASE to OUT
1000
tpHL
Output Load: 6.8 mH/5.7 Ω
2000
tpLH
CR to OUT
500
tpHL
Output Load: 6.8 mH/5.7 Ω
1000
Noise rejection dead band time
tBRANK
IOUT = 1.0 A
200
300
500
ns
CR reference signal oscillation
frequency
fCR
Cosc = 560 pF, Rosc = 3.6 kΩ
800
kHz
40
100
150
kHz
100
kHz
100
200
µs
Characteristics
Clock frequency
Minimum Clock Pulse Width
Output transistor switching
characteristic
Chopping frequency possible range
fchop (min)
fchop (max)
Chopping set frequency
fchop
Output Load: 6.8 mH/5.7 Ω
VM = 24 V, VDD = 5 V, Output
ACTIVE (IOUT = 1.0 A)
Step fixed, Ccp1 = 0.22 µF,
Ccp2 = 0.022 µF
Output ACTIVE (IOUT = 1.0 A),
CR CLK = 800 kHz
ns
ns
Ccp1 = 0.22 µF,
Charge pump rise time
tONG
Ccp2 = 0.022 µF
VM = 24 V, VDD = 5 V,
STANDBY = L → H
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TB62206FG
Current Waveform and Setting of MIXED DECAY MODE
To control the constant current, the rate of Mixed Decay Mode which determines current amplitude
(ripple current) should be 37.5%.
fchop
CR pin
internal
CLK
waveform
DECAY MODE 1
Set current value
NF
37.5%
MIXED
DECAY
MODE
MDT
Charge mode → NF: set current value reached → Slow mode
→ Mixed decay timing → Fast mode → Charge mode
MIXED DECAY MODE Waveform (current waveform)
fchop
fchop
Internal
CR CLK
signal
IOUT
Set current value
Set current
value
NF
NF
25%
MIXED
DECAY
MODE
RNF
MDT (MIXED DECAY TIMING) point: 37.5% fixed
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TB62206FG
PHASE Signal, Internal CR CLK, and Output Current Waveform
(when PHASE signal is input in 2 phase excitation mode)
37.5％ MIXED DECAY MODE
fchop
fchop
fchop
Set current
value
IOUT
0
MDT
Set current value
NF
NF
PHASE signal input
Reset CR-CLK counter here
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TB62206FG
Current Discharge Path when ENABLE Input During Operation
In Slow Mode, when all output transistors are forced to switch off, coil energy is discharged in the
following MODES:
Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow
to the parasitic diodes.
VM
VM
RRS
RRS
RS pin
U1
ON
VM
(Note)
RRS
RS pin
U2
U1
OFF
OFF
Load
(Note)
Load
OFF
ON
ON
L1
L2
L1
PGND
Charge mode
RS pin
U1
OFF
OFF
(Note)
ENABLE OFF
Load
L2
ON
PGND
Slow mode
U2
U2
OFF
L1
L2
OFF
OFF
PGND
Forced OFF mode
As shown in the figure above, an output transistor has parasitic diodes.
To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse
direction to that in normal operation. As a result, the parasitic diodes are not used. If all the output
transistors are forced to switch off, the energy of the coil is discharged via the parasitic diodes.
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TB62206FG
Output Transistor Operating Mode
VM
VM
RRS
RRS
RS pin
RRS
RS pin
U1
U2
U1
OFF
OFF
L1
L2
L1
OFF
ON
ON
ON
VM
(Note)
RS pin
(Note)
Load
U2
U1
OFF
OFF
Load
PGND
U2
Load
L2
L1
L2
ON
ON
OFF
PGND
Charge mode
Current flows
into the coil.
ON
(Note)
PGND
Slow mode
Current flows between
the coil and the IC.
Fast mode
The energy in the coil flows
back to the power supply.
Output Transistor Operation Functions
Mode
Tr
U1
U2
L1
L2
CHARGE
ON
OFF
OFF
ON
SLOW
OFF
OFF
ON
ON
FAST
OFF
ON
ON
OFF
Note: The above table is an example where current flows in the direction of the arrows in the above figures.
When the current flows in the opposite direction of the arrows, see the table below.
Mode
Tr
U1
U2
L1
L2
CHARGE
OFF
ON
ON
OFF
SLOW
OFF
OFF
ON
ON
FAST
ON
OFF
OFF
ON
In this IC, three modes as shown above are automatically switched to control the constant current.
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TB62206FG
Power Supply Sequence (recommended)
VDD (max)
VDD (min)
VDD
VDDR
GND
VM
VM (min)
VM
VMR
GND
Active
Internal operable
Non-active
STANDBY
INPUT (Note 1)
H
STANDBY
L
Takes up to tONG until operable.
Non-operable area
Note 1: If the VDD drops to the level of the VDDR or below while the specified voltage is input to the VM pin, the IC is
internally reset.
This is a protective measure against malfunction. Likewise, if the VM drops to the level of the VMR or below
while regulation voltage is input to the VDD, the IC is internally reset as a protective measure against
malfunction.
To avoid malfunction, when turning on VM or VDD, to input the STANDBY signal at the above timing is
recommended.
It takes time for the output control charge pump circuit to stabilize. Wait up to tONG time after power on
before driving the motors.
Note 2: When the VM value is between 8 to 11 V, the internal reset is released, thus output may be on. In such a
case, the charge pump cannot drive stably because of insufficient voltage. The Standby state should be
maintained until VM reaches 13 V or more.
Note 3: Since VDD = 0 V and VM = voltage within the rating are applied, output is turned off by internal reset.
At that time, a current of several mA flows due to the Pass between VM and VDD.
When voltage increases on VDD output, make sure that specified voltage is input.
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TB62206FG
How to Calculate Set Current
This IC drives the motor, controlling the PWM constant current in reference to the frequency of CR
oscillator.
At that time, the maximum current value (set current value) can be determined by setting the sensing
resistor (RRS) and reference voltage (Vref).
IOUT (max) =
Torque (Torque = 100, 71%)
1
x Vref (V) x
5.0
RRS (Ω) x 100(%)
1/5.0 is Vref (gain): Vref attenuation ratio. (for the specifications, see the electrical characteristics.)
For example, when applying Vref = 3 V and torque = 100% to drive out IOUT of 0.8 A, RRS = 0.75 Ω (0.5 W
or more) is required.
(for 1-2 phase excitation with 71% of torque, the peak current should be set to 100%).
How to Calculate the Chopping and OSC Frequencies
At constant current control, this IC chops frequency using the oscillation waveform (saw tooth waveform)
determined by external capacitor and resistor as a reference.
The TB62206FG requires an oscillation frequency of eight times the chopping frequency.
The oscillation frequency is calculated as follows:
fCR =
1
0.523 × (C × R + 600 × C)
For example, when Cosc = 560 pF and Rosc = 3.6 kΩ are connected, fCR = 813 kHz.
At this time, the chopping frequency fchop is calculated as follows:
fchop = fCR/8 = 101 kHz
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TB62206FG
IC Power Dissipation
IC power dissipation is classified into two: power consumed by transistors in the output block and power
consumed by the logic block and the charge pump circuit.
•
Power consumed by the Power Transistor (calculated with RON = 0.60 Ω)
•
In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower
transistors of the H bridges.
The following expression expresses the power consumed by the transistors of a H bridge.
P (out) = 2 (Tr) × IOUT (A) × VDS (V) = 2 × IOUT2 × RON .............................. (1)
The average power dissipation for output under 4-bit micro step operation (phase difference between
phases A and B is 90°) is determined by expression (1).
Thus, power dissipation for output per unit is determined as follows (2) under the conditions below.
RON = 0.60 Ω (＠1.0 A)
IOUT (Peak: max) = 1.0 A
VM = 24 V
VDD = 5 V
P (out) = 2 (Tr) × 1.02 (A) × 0.60 × 2 (Ω) = 2.40 (W) ........................................ (2)
Power consumed by the logic block and IM
The following standard values are used as power dissipation of the logic block and IM at operation.
I (LOGIC) = 2.5 mA (typ.):
I (IM3) = 10.0 mA (typ.): operation/unit
I (IM1) = 2.0 mA (typ.): stop/unit
The logic block is connected to VDD (5 V). IM (total of current consumed by the circuits connected to
VM and current consumed by output switching) is connected to VM (24 V). Power dissipation is
calculated as follows:
P (Logic&IM) = 5 (V) × 0.0025 (A) + 24 (V) × 0.010 (A) = 0.25 (W) ............... (3)
Thus, the total power dissipation (P) is
P = P (out) + P (Logic&IM) = 2.65 (W)
Power dissipation at standby is determined as follows:
P (standby) + P (out) = 24 (V) × 0.002 (A) + 5 (V) × 0.0025 (A) = 0.06 (W)
For thermal design on the board, evaluate by mounting the IC.
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TB62206FG
Test Waveforms
t phase
Phase
tpLH
VM
90%
90%
tpHL
50%
50%
10%
10%
GND
tr
Figure 1
tf
Timing Waveforms and Names
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TB62206FG
OSC-Charge Delay
OSC-Fast Delay
H
OSC (CR)
L
tchop
H
OUTPUT
Voltage A
50%
L
H
OUTPUT
Voltage A
50%
50%
L
Set current
OUTPUT
Current
L
Charge
Slow
Fast
OSC-Charge DELAY:
Because the rising edge level of the OSC waveform is used for converting the OSC waveform to the
internal CR CLK, a delay of up to 1.25 ns (@fchop = 100 kHz: fCR = 400 kHz) occurs between the OSC
waveform and the internal CR CLK.
CR-CR CLK DELAY
CR Waveform
Internal CR CLK
Waveform
Figure 2
Timing Waveforms and Names (CR and output)
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TB62206FG
PD – Ta (package power dissipation)
PD – Ta
3.5
(2)
2.5
Power dissipation
PD
(W)
3
2
1.5
1
(1)
0.5
0
0
25
50
75
100
125
150
Ambient temperature Ta (°C)
(4)
(5)
HSOP20 Rth (j-a) only (96°C/W)
When mounted on the board (140 mm × 70 mm × 1.6 mm: 38°C/W: typ.: under evaluation)
Note: Rth (j-c): 8.5°C/W
Transient thermal resistance at soldering process depends on the PCB condition to be used.
Please pay attention to the thermal conditions when designing PCB, and be sure to check
the thermal conditions at the actual evaluation.
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TB62206FG
Relationship between VM and VH (charge pump voltage)
Note: VDD = 5 V
VM – VH (&Vcharge UP)
50
VH voltage
charge up voltage
VM voltage
Absolute Maximum rating
40
Charge pump
output voltage
VH voltage, charge up voltage
(V)
Input STANDBY
30
VM voltage
Absolute Maximum rating
VMR
20
10
operation area
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Supply voltage VM (V)
Charge pump voltage VH = VDD + VM (= Ccp A)
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TB62206FG
Operation of Charge Pump Circuit
RRS
RS
VDD = 5 V
VM
VH
VM = 24 V
Ccp A
7
i2
Output
i1
Tr2
Di2
Di1
(2)
(1)
Comparator
&
Controller Output
H switch
Vz
Di3
(2)
R1
Ccp B
Ccp 2
0.022 µF
Ccp 1
0.22 µF
Ccp C
Tr1
VH = VM + VDD = charge pump voltage
i1 = charge pump output current
i2 = gate block power dissipation
•
Initial charging
(1)
•
When RESET is released, Tr1 is turned ON and Tr2 turned OFF. Ccp 2 is charged from Ccp 2 via
Di1.
(2) Tr1 is turned OFF, Tr2 is turned ON, and Ccp 1 is charged from Ccp 2 via Di2.
(3) When the voltage difference between VM and VH (Ccp A pin voltage = charge pump voltage)
reaches VDD or higher, operation halts (steady state).
Actual operation
(4)
(5)
Ccp 1 charge is used at fchop switching and the VH potential drops.
Charges up by (1) and (2) above.
Output switching
Initial charging
Steady state
VH
VM
(1)
(2)
(3)
(4)
(5)
(4)
(5)
t
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TB62206FG
Charge Pump Rise Time
Ccp 1 voltage
VDD + VM
VM + (VDD × 90%)
VM
5V
STANDBY
50%
0V
tONG
tONG:
Delay time taken for capacitor Ccp 2 (charging capacitor) to fill up Ccp 1 (storing capacitor) to VM + VDD
after STANDBY is released.
The internal IC cannot drive the gates correctly until the voltage of Ccp 1 reaches VM + VDD. Be sure to
wait for tONG or longer before driving the motors.
Basically, the larger the Ccp 1 capacitance, the smaller the voltage fluctuation, though the initial charge
up time is longer.
The smaller the Ccp 1 capacitance, the shorter the initial charge-up time but the voltage fluctuation is
larger.
Depending on the combination of capacitors (especially with small capacitance), voltage may not be
sufficiently boosted.
When the voltage does not increase sufficiently, output DMOS RON turns lower than the normal, and it
raises the temperature.
Thus, use the capacitors under the capacitor combination conditions (Ccp 1 = 0.22 µF, Ccp 2 = 0.022 µF)
recommended by Toshiba.
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Overcurrent Shutdown (ISD) Circuitry
ISD Dead Time and ISD On-Time
fosc Oscillation
(Chopper Waveform)
fosc
(OSC_M)
MIN
MAX
MIN
MAX
(Dead Time)
tISD(Mask)
ISD On-Time
An overcurrent starts to flow into the output transistors.
Figure for reference: Timing chart in case the over current flows in the motor.
The overcurrent shutdown (ISD) circuitry has a dead time to prevent false detection by the spike current in
switching. The dead time synchronizes with the frequency of OSC (OSC_M) for configuration of chopping frequency.
It is configured as follows.
Time from the flow of the over current to the output steps to the stop of the output is as follows.
Dead time = 4 × fosc_M frequency
In setting,
Min: 4 × fosc_M frequency
Max: 8 × fosc_M frequency (+ Synchronizing time +1fosc_M time)
It should be noted that these values assume a case in which an overcurrent condition is detected in an ideal
manner. The ISD circuitry might not work, depending on the control timing of the output transistors.
Therefore, a protection fuse must always be added to the VM power supply as a safety precaution. The optimal
fuse capacitance varies with usage conditions, and one that does not adversely affect the motor operation or exceed
the power dissipation rating of the TB62206FG should be selected.
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TB62206FG
External Capacitor for Charge Pump
When driving the stepping motor with VDD = 5 V, fchop = 150 kHz, L = 10 mH under the conditions of VM
= 13 V and 1.5 A, the logical values for Ccp 1 and Ccp 2 are as shown in the graph below:
Ccp 1 – Ccp 2
0.05
Applicable range
0.045
Ccp 2 capacitance
(µF)
0.04
0.035
0.03
0.025
0.02
Recommended
value
0.015
0.01
0.005
0
0
0.05
0.1 0.15 0.2 0.25
0.3 0.35 0.4
Ccp 1 capacitance
0.45 0.5
(µF)
Choose Ccp 1 and Ccp 2 to be combined from the above applicable range. We recommend Ccp 1 : Ccp 2 at
10 : 1 or more. (if our recommended values (Ccp 1 = 0.22 µF, Ccp 2 = 0.022 µF) are used, the drive conditions
in the specification sheet are satisfied. (there is no capacitor temperature characteristic as a condition.)
When setting the constants, make sure that the charge pump voltage is not below the specified value and
set the constants with a margin (the larger Ccp 1 and Ccp 2, the more the margin).
Some capacitors exhibit a large change in capacitance according to the temperature. Make sure the above
capacitance is obtained under the usage environment temperature.
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Driving Mode
2-Phase Excitation Mode
In 2-Phase Excitation, ENABLE is always High
Phase B
Phase A
①
②
③
④
①
②
③
100
[%]
Phase B
0
Phase A
−100
STEP
150
①
②
100
50
B相
Phase B
0
-150
-100
-50
0
50
100
150
-50
-100
③
④
-150
A相 A
Phase
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TB62206FG
1-2 Phase Excitation
ENABLE B
ENABLE A
Phase B
Phase A
①
②
③
④
⑤
⑥
⑦
⑧
①
②
③
④
100
[%]
Phase B
Phase A
0
−100
STEP
150
④
③
②
100
B相
50
Phase B
-150
⑤
-100
①
0
-50
0
50
100
150
-50
-100
⑥
⑦
⑧
-150
A相 A
Phase
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TB62206FG
Sequence examples including reverse (1/2 step)
CCW
①
②
③
④
⑤
⑥
CW
STOP
⑦
⑧
①
②
③
②
①
⑧
⑦
⑥
⑤
④
③
Phase A
Phase B
ENABLE A
ENABLE B
Time (Step)
: Don't Care
●
Electrical angle representation of the sequence
②
①
A
⑧
③
100
-100
100
0
B
④
Step proceeded to ①→②.. ⑦→
①→②....⑦→⑧→①→②→③ま
でステップ進行し､逆転､③→②
⑧ → ① → ② → ③ , and is
→①→⑧....④→③へ進行する例
reversed. This is an example of
です。 to
progress
二回目の③のポイントが逆転ポ
③→②→①→⑧..④→③.
Second
イントです。
time
③ is a reversal point.
-100
⑦
⑤
⑥
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TB62206FG
Application Circuit (example)
The values for the respective devices are all recommended values. For values under each input condition,
see the above-mentioned recommended operating conditions.
Rosc = 3.6 kΩ
Vref A
CR
Vref AB
Vref B
Cosc = 560 pF
3V
1 µF
SGND
VM
VDD
RRS A
RRS A 0.66 Ω
A
A
B
M
B
RRS B
Stepping
motor
RRS B
0.66 Ω
FIN
PGND
5V
SGND
FIN
5V
0V
ENABLE A
5V
0V
5V
0V
EANBLE B
5V
0V
PHASE B
5V
0V
STANDBY
SGND
PHASE A
10 µF
Ccp A Ccp B
TORQUE
5V
0V
Ccp C
Ccp 1
Ccp 2
0.22 µF 0.022 µF
SGND
24 V
100 µF
SGND
Note: Adding bypass capacitors is recommended.
Make sure that GND wiring has only one contact point, and to design the pattern that allows the heat
radiation.
To control setting pins in each mode by SW, make sure to pull down or pull up them to avoid high
impedance.
To input the data, see the section on the recommended input data.
The IC may be destroyed due to short circuit between output pins, an output pin and the VDD pin, or an
output pin and the GND pin.
Design an output line, VDD (VM) line and GND line with great care.
Also a low-withstand-voltage device may be destroyed when mounted in the wrong orientation, which
causes high-withstanding voltage to be applied to the device.
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TB62206FG
Package Dimensions
Weight: 0.79 g (typ.)
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified
for explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for
explanatory purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough
evaluation is required, especially at the mass production design stage.
Toshiba does not grant any license to any industrial property rights by providing these examples of
application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
IC Usage Considerations
Notes on handling of ICs
[1] The absolute absolute maximum ratings of a semiconductor device are a set of ratings that must not
be exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
[2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in
case of over current and/or IC failure. The IC will fully break down when used under conditions that
exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal
pulse noise occurs from the wiring or load, causing a large current to continuously flow and the
breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case
of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location,
are required.
[3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into
the design to prevent device malfunction or breakdown caused by the current resulting from the
inrush current at power ON or the negative current resulting from the back electromotive force at
power OFF. IC breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is
unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause
injury, smoke or ignition.
[4] Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and
exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
In addition, do not use any device that is applied the current with inserting in the wrong orientation
or incorrectly even just one time.
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TB62206FG
[5] Carefully select external components (such as inputs and negative feedback capacitors) and load
components (such as speakers), for example, power amp and regulator.
If there is a large amount of leakage current such as input or negative feedback condenser, the IC
output DC voltage will increase. If this output voltage is connected to a speaker with low input
withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can
cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge
Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly.
Points to remember on handling of ICs
(1) Over current Protection Circuit
Over current protection circuits (referred to as current limiter circuits) do not necessarily protect
ICs under all circumstances. If the Over current protection circuits operate against the over current,
clear the over current status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the over current protection circuit to not operate properly or IC breakdown before
operation. In addition, depending on the method of use and usage conditions, if over current
continues to flow for a long time after operation, the IC may generate heat resulting in breakdown.
(2) Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal
shutdown circuits operate against the over temperature, clear the heat generation status
immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.
(3) Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the
device so that heat is appropriately radiated, not to exceed the specified junction temperature (TJ)
at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat
radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown.
In addition, please design the device taking into considerate the effect of IC heat radiation with
peripheral components.
(4) Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to
the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power
supply is small, the device’s motor power supply and output pins might be exposed to conditions
beyond absolute maximum ratings. To avoid this problem, take the effect of back-EMF into
consideration in system design.
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TB62206FG
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH
MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
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limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
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including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES
OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
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