TB9081FG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB9081FG
Automotive GATE-driver for Brushless motor
TB9081FG is Pre-driver IC automotive for brushless motor.
Fail-safe relay pre-drivers are also built in in addition to
3-phase pre-drivers.
The charge pump, the motor current detection circuit, the
oscillator, and the SPI communication circuit are built in.
The miscellaneous abnormal detections are carried and the
operation after failure detection conditions and failure
detections can be set up. About each setup, these can set up
through a SPI communication.
Also, it has built-in ABIST / LBIST functions for diagnosing
the normal operation of the miscellaneous abnormal detection
function.
LQFP64-P-1010-0.50E
Weight: 0.35 g (typ.)
Features
•
•
•
•
•
•
•
•
•
•
•
3-phase pre-drivers : PWM control to 20kHz
Build-in fail-safe relay pre-drivers
Build-in Charge Pump
High response Current Detection circuit
Miscellaneous-abnormal-detection circuits
(Under voltage (VB, VCC) / Over voltage (VCC) / Over temp. / FET short-circuit detection)
Build-in ABIST/LBIST functions
Operating voltage range : VB=4.5 to 28V, VCC=3.0 to 5.5V
Operational temperature range : -40 to 125°C
Package : LQFP-64pin (0.5mm pitch)
AEC-Q100 Qualified
TM-SILTM
Developed according to ISO 26262 ASIL-D
Safety Manual and Safety Analysis Report
Functional redundancy and built-in ABIST and LBIST
SPI interface with CRC check
The product(s) is/are compatible with RoHS regulations (EU directive 2011 / 65 / EU)
as indicated, if any, on the packaging label ("[[G]]/RoHS COMPATIBLE", "[[G]]/RoHS
[[Chemical symbol(s) of controlled substance(s)]]", "RoHS COMPATIBLE" or "RoHS
COMPATIBLE, [[Chemical symbol(s) of controlled substance(s)]]>MCV").
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TB9081FG
Table of contents
Internal block diagram
Package pin layout (top view)
Pin description
Functional descriptions
(1) Charge pump circuit
(2) Pre-drivers
(3) Current detector
(4) Oscillator/divider
(5) Abnormal detection circuit
(5-1) VB1/VB2 under voltage detection
(5-2) VCC1/VCC2 under voltage detection
(5-3) VCC1/VCC2 over voltage detection
(5-4) Over temperature detection
(5-5) Short-circuit detection
(5-6) Oscillation frequency monitoring
(6) ALARM input circuit
(7) EN_CP input circuit
(8) ABIST function
(9) SPI Communication circuit
(9-1) SPI communication operation
(9-2) Register map
Absolute maximum ratings
Electrical characteristics
Reference circuit diagram
PACKAGE
Revision history
RESTRICTIONS ON PRODUCT USE
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TB9081FG
VCPH
VCPL
CP2L
CP2H
Charge pump
OSC
CLKOUT
CP1L
VB1
VB2
CP1H
Internal block diagram
VCC1
VCC2
BR1O
BR2O
VCC_OP
Each voltage
detection circuit
HS
EN_CP
ALARM2
ALARM1
EN_CP
input
circuit
HUO
ALA RM
input
circuit
HVO
HWO
BR1I
BR2I
RUI
RVI
SHU
RWI
/CS
SDIN
SDOUT
Pre-Driver
RUO
11ch
SHV
RVO
Fo r Motor：6ch
Fo r Relay：5ch
SPI
SHW
RWO
SCK
LUO
HUI
HVI
HWI
LUI
LVI
LWI
LVO
LWO
PGND1
PGND2
PGND3
VRI
Current sensor
TSD1
TSD2
TSD3
V REF1
VRO
AMP1P
AMP1O
AMP2P
A MP1
AMP2N
AMP2O
AMP3P
A MP2
AMP1N
A MP3
AMP3N
BG1
BG2
AGND1
AGND2
TEST
FET short detection
Error Logic
AMP3O
NDIAG
Notes 1: Some of the functional blocks, circuit, or constants in the block diagram may be omitted or
simplified for explanatory purpose. (including individual block diagram)
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TB9081FG
BR2I
BR1I
HWI
HVI
HUI
LUI
LVI
LWI
/CS
SCK
VCC1
SDIN
SDOUT
AGND1
VRO
VRI
Package pin layout (top view)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AMP3O
49
32
EN_CP
AMP3N
50
31
PGND3
AMP3P
51
30
BR1O
AMP2O
52
29
BR2O
AMP2N
53
28
HUO
AMP2P
54
27
HVO
VCC_OP
55
26
HWO
AMP1O
56
25
VB1
AMP1N
57
24
VB2
AMP1P
58
23
CP1H
AGND2
59
22
VCPH
NDIAG
60
21
CP2H
CLKOUT
61
20
SHW
ALARM2
62
19
CP1L
TEST
63
18
SHV
ALARM1
64
17
CP2L
RVI
VCC2
RWI
PGND1
RUO
RVO
RWO
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9 10 11 12 13 14 15 16
VCPL
8
SHU
7
HS
6
PGND2
5
LUO
4
LVO
3
LWO
2
NC
1
RUI
TB9081FG
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TB9081FG
Pin description
Pin No.
Symbol
Input/output
Definition
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RUI
RVI
VCC2
RWI
PGND1
RUO
RVO
RWO
NC
LWO
LVO
LUO
PGND2
HS
SHU
VCPL
CP2L
SHV
CP1L
SHW
CP2H
VCPH
CP1H
VB2
VB1
HWO
HVO
HUO
BR2O
BR1O
PGND3
EN_CP
BR2I
BR1I
HWI
HVI
HUI
LUI
LVI
LWI
/CS
SCK
VCC1
SDIN
SDOUT
AGND1
VRO
VRI
AMP3O
AMP3N
AMP3P
AMP2O
AMP2N
AMP2P
VCC_OP
AMP1O
AMP1N
AMP1P
AGND2
NDIAG
CLKOUT
ALARM2
TEST
ALARM1
IN
IN
Power supply
IN
GND
OUT
OUT
OUT
OUT
OUT
OUT
GND
IN
IN
Power supply
OUT
IN
OUT
IN
IN/OUT
Power supply
IN/OUT
Power supply
Power supply
OUT
OUT
OUT
OUT
OUT
GND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Power supply
IN
OUT
GND
OUT
IN
OUT
IN
IN
OUT
IN
IN
Power supply
OUT
IN
IN
GND
OUT
OUT
IN
IN
IN
U-Phase Motor Relay Input
V-Phase Motor Relay Input
Power supply 2 (3.3V or 5V)
W-Phase Motor Relay Input
Power GND1
U-Phase Motor Relay Output
V-Phase Motor Relay Output
W-Phase Motor Relay Output
Pre-Driver Output LW
Pre-Driver Output LV
Pre-Driver Output LU
Power GND2
High-side Drain Input
Motor Connect PIN U-phase
Charge-pump voltage (for low sides)
2nd Charge Pump Drive Output
Motor Connect PIN V-phase
1st Charge Pump Drive Output
Motor Connect PIN W-phase
2nd Charge Pump Output
Charge-pump voltage (for high sides)
1st Charge Pump Output
Power Supply2 (Battery 12V)
Power Supply1 (Battery 12V)
Pre-Driver Output HW
Pre-Driver Output HV
Pre-Driver Output HU
BR2 Power supply relay Output
BR1 Power supply relay Output
Power GND 3
Charge-pump enable signal
BR2 Power supply relay Input
BR1 Power supply relay Input
Pre-Driver Input HW
Pre-Driver Input HV
Pre-Driver Input HU
Pre-Driver Input LU
Pre-Driver Input LV
Pre-Driver Input LW
SPI chip select
SPI clock input
Power supply 1 (3.3V or 5V)
SPI input
SPI Output
The GND 1 for analog circuits
Reference voltage amplifier Output
Reference voltage amplifier input
Current-detection amplifier Output 3
Current-detection amplifier input 3 (-)
Current-detection amplifier input 3 (+)
Current-detection amplifier Output 2
Current-detection amplifier input 2 (-)
Current-detection amplifier input 2 (+)
The power supply for Current-detection amplifier (5V/3.3V)
Current-detection amplifier Output 1
Current-detection amplifier input 1 (-)
Current-detection amplifier input 1 (+)
The ground 2 for analog circuits
Error Output Pin
Clock output
Pre-driver enable 2
Test terminal
Pre-driver enable 1
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Pull-Up/Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Up
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
Notes
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
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TB9081FG
●Description of an internal signal name
Internal signal
name
abst_pass
Normal signal of
abst_end
End signal of ABIST
gate_en_u
gate_en_v
gate_en_w
gate_en_r
State
Description
ABIST
H
L
ABIST normal
Enable
Enable
Enable
Enable
ABIST abnormal
ABIST
unfinished
Disable
Disable
Disable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Enable
Detection
Detection
Detection
Detection
Reset release
Detection
Disable
Disable
Release
Release
Release
Release
Reset
Release
ABIST end
cp_en
cp_off
vbl1
vbl2
vcl1
vcl2
por_x
vch
Pre-driver output enabling signal (U phase)
Pre-driver output enabling signal (V phase)
Pre-driver output enabling signal (W phase)
Pre-driver output enabling signal (relay)
Error output signal (Pre-driver output enabling, U
phase)
Error output signal (Pre-driver output enabling, V
phase)
Error output signal (Pre-driver output enabling, W
phase)
Error output signal (Pre-driver output enabling,
relay)
Enabling signal for charge pump circuit
Error output signal (charge pump circuit enabling)
VB1/VB2 under voltage detection signal 1
VB1/VB2 under voltage detection signal 2
VCC1/VCC2 under voltage detection signal 1
VCC1/VCC2 under voltage detection signal 2
Internal reset signal
VCC1/VCC2 over voltage detection signal
vphh
VCPH clamp voltage detection signal
Detection
Release
tsd1det
Over temperature detection signal1
Detection
Release
tsd2det
Over temperature detection signal2
Detection
Release
tsd3det
Over temperature detection signal3
Detection
Release
shuho
shvho
shwho
shulo
shvlo
shwlo
Short-circuit detection signal (U phase low side)
Short-circuit detection signal (V phase low side)
Short-circuit detection signal (W phase low side)
Short-circuit detection signal (U phase high side)
Short-circuit detection signal (V phase high side)
Short-circuit detection signal (W phase high side)
Detection
Detection
Detection
Detection
Detection
Detection
Release
Release
Release
Release
Release
Release
gate_off_u
gate_off_v
gate_off_w
gate_off_r
Symbol
Vb
Vcc
Pin name
VB1,VB2
VCC1,VCC2
Vccop
VCC_OP
Vcph
Vcpl
AGND
PGND
VCPH
VCPL
AGND1,AGND2
PGND1,PGND2,PGND3
Function/Application
Battery power supply
External 5V/3.3V power supply
The power supply for current detection
amplifier (5V/3.3V)
Charge pump voltage (for high sides)
Charge pump voltage (for low sides)
GND for analog circuitry
Power GND
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TB9081FG
Functional descriptions
(1)
Charge pump circuit
TB9081FG build in Charge pump for Pre-Drivers and it can control external Nch MOSFETs directly. Two
charge pump voltages the object for the high side drive of a motor and the object for the relay drive of a
motor, and for the low side drive of a motor is generated.
The charge pump voltage (Vcph) for a high side drive and a relay drive control by an internal circuit, and
if Vcph goes up to Vb+12V (Typ.), a charge pump will suspend operation. Furthermore, in consideration
of an overvoltage state, if Vcph goes up to 37V (Typ.), a charge pump will stop, and if Vcph is less than
36.5V (Typ.), a charge pump will resume operation.
The charge pump voltage (Vcpl) for a low side drive is generated from Vcph. If Vcpl goes up to 16V
(Typ.), a clamp will start and it will not become the voltage more than clamp voltage.
It is possible to build the switching circuit (CP_SW) in the Vb side of a charge pump circuit, to make a
transistor turn off by CP_SW, and to stop the supply to Vcph from Vb. Vcc voltage turns off the transistor
of CP_SW on condition of the conditions as for which below Vcc voltage detection voltage becomes, or
EN_CP=L. For details, please refer to a (7) EN_CP circuit.
Moreover, it is possible to operate or stop a charge pump by terminal EN_CP. The charge pump
operates at the time of EN_CP="H", and it stops at the time of EN_CP="L" and also suspends the supply
to Vcph from Vb .
A Vcph output voltage is set to 0V at the time of the charge-pump stop by EN_CP="L."
When the charge pump is stopped by the control in the IC, Vcph output voltage will become the
"Vb-3VF".
Vcc
Vb
CP_SW
Vcc
(por_x）
Logic
Vcc
SR1
Divider
Ccp=0.1μF
CP1H
(por_x）
Vcc
Vb
Vcc
50kΩ
(por_x）
Control
Circuit
(cp_off）
Error Logic
CP1L
Charge Pump1
(cp_en）
EN_CP
Rcp=15Ω
Vcc
SR2
Ccp=0.1μF
CP2H
(por_x）
Vcc
Vb
CP2L
Charge Pump2
(por_x）
(por_x）
Rcp=15Ω
Vcc
SR3
Vcc
(por_x）
Vb
VB+12V
detector
Pre-drv.
（High-side）
VCPH
Clamp
（16V）
Vcc
(vphh)
Fig.1- a
Cvcph1=10μF
Cvcph2=0.1μF
VCPL
36V
detector
Pre-drv.
（Low-side）
Cvcpｌ1=4.7μF
Cvcpｌ2=0.1μF
Charge pump circuit Block Diagram
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TB9081FG
(2)
Pre-drivers
TB9081FG has the pre-driver circuit it is for the motor relay drive, for the power relay drive, for the
low-side drive of the motor and for the high-side drive of the motor. Each pre-driver circuit has a
respective input and output terminals are controlled by a signal inputted to the input terminals.
Battery
Vcph
Vcc
BR1O
BR1I
1kΩ
50kΩ
Vcc
10kΩ
BR2O
BR2I
50kΩ
1kΩ
Vcc
Vcc
10kΩ
HUO
HUI
50kΩ
Vcc
HVI
50kΩ
Vcc
HVO
Pre-drv.
logic
HWO
HWI
50kΩ
Vcc
RUO
RUI
1kΩ
50kΩ
Vcc
10kΩ
RVO
M
RVI
50kΩ
1kΩ
Vcc
10kΩ
RWO
RWI
1kΩ
50kΩ
10kΩ
Vcpl
Vcc
LUO
Vcc
LVO
Vcc
LWO
LUI
50kΩ
LVI
50kΩ
LWI
50kΩ
Vcc
(clk4m)
output current
switching time
control logic
(gate_en_w)
(gate_en_v)
(gate_en_u)
(gate_en_r)
（por_x）
Fig.2- a
Pre-driver circuit Block Diagram
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TB9081FG
A power supply relay drive circuit is a circuit which controls FET for a relay on the battery power-supply
side.
A motor relay drive circuit is a circuit which controls FET for a relay on the motor side.
A truth table is shown in table 2-a and 2-b. Refer to the (6) ALARM input circuit for the details of the
internal signal (gate_en_r) in a truth table.
Moreover, resistance 1kΩ is built in the output of a power supply relay drive and a motor relay drive.
Furthermore, the diode for prevention of backflow at the time of reverse connection is built in the output of
a power supply relay drive circuit.
- Table 2- a
Input/output truth table 1 (power supply relay drive circuit)
- Power supply relay drive circuit 1
Input
Internal signal
BR1I
(gate_en_r)
L
H
H
H
*
L
*:Don't care
Output
BR1O
L
H
L
- Power supply relay drive circuit 2
Input
Internal signal
BR2I
(gate_en_r)
L
H
H
H
*
L
*:Don't care
Output
BR2O
L
H
L
- Table 2- b
Notes
-
Notes
-
Input/output truth table 2 (motor relay drive circuit)
- Motor relay drive circuit 1 (U phase)
Input
Internal signal
RUI
(gate_en_r)
L
H
H
H
*
L
*:Don't care
Output
RUO
L
H
L
- Motor relay drive circuit 2 (V phase)
Input
Internal signal
RVI
(gate_en_r)
L
H
H
H
*
L
*:Don't care
Output
RVO
L
H
L
- Motor relay drive circuit 3 (W phase)
Input
Internal signal
RWI
(gate_en_r)
L
H
H
H
*
L
*:Don't care
Output
RWO
L
H
L
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Notes
-
Notes
-
Notes
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TB9081FG
A high side drive circuit is a circuit which drives FET of the high side of a motor. A low side drive circuit is
a circuit which drives FET of the low side of a motor. A high side drive circuit and a low side drive circuit
built in each 3ch.
An input signal (HUI/HVI/HWI, LUI/LVI/LWI) is changed by a control block, and output (HUO/HVO/HWO,
LUO/LVO/LWO) is outputted. A truth table is shown in table 2-c. Refer to the (6) ALARM input circuit for
the details of the internal signal (gate_en_u, gate_en_v, gate_en_w) in a truth table.
When HUI/LUI, HVI/LVI, and HWI/LWI are H/H, an output will be L/L (prohibition input). The operation at
the time of prohibition input detection can be set up through a SPI communication.
Moreover, the current at the time of Turn on/Turn off of a high side drive circuit and a low side drive circuit
is the current limit after 8 μs (typ.). This current-limiting time can be set up a 3 value or no limit time
through a SPI communication.
When gate_en_u, gate_en_v, and gate_en_w switch from “H” to “L” by the failure detection and
ALARM1 or ALARM2 outputting low, and then, the high side drive circuit and the low side drive circuit
output high, it switches to “L”. At this time, it has an output current capability which is decided by the ON
resistance and the gate resistance of the output driver during the current limit time. However, only Vcc
under voltage detection, the output current capability will be the output limit current Iolmtl even within the
current limit time.
- Table 2- c Input/output truth table 3 (a high side drive circuit, a low side drive circuit)
- FET drive circuit 1 (U phase)
Input
Internal
signal
Output
Notes
HUI
LUI
(gate_en_u)
HUO
LUO
L
L
H
H
*
*: Don’t care
L
H
L
H
*
H
H
H
H
L
L
L
H
L
L
L
H
L
L
L
- FET drive circuit 2 (V phase)
Input
Internal
signal
Output
LVI
(gate_en_v)
HVO
LVO
L
L
H
H
*
*: Don’t care
L
H
L
H
*
H
H
H
H
L
L
L
H
L
L
L
H
L
L
L
Internal
signal
Output
LWI
(gate_en_w)
HWO
LWO
L
L
H
H
*
*: Don’t care
L
H
L
H
*
H
H
H
H
L
L
L
H
L
L
L
H
L
L
L
10
-
-
Inhibit input mode
-
Notes
HWI
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Inhibit input mode
Notes
HVI
- FET drive circuit 3 (W phase)
Input
-
-
Inhibit input mode
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TB9081FG
(3)
Current detector
TB9081FG are built three amplifiers for motor-current detection and one amplifier for reference voltage
generation (Fig3- a).
The amplifiers for motor-current detection can amplify the difference voltage which produces according
to the current which flows through the shunt resistance connected to the motor actuator.
The amplifier for reference voltage generation is used as buffer amplifier for reference voltage
generation.
As an external configuration of the current detection, it is available in either 1 shunt configuration or 3
shunt configuration.
Vccop
AMP1P
+
AMP1N
(vbg1)
AMP1O
Vccop
AMP2P
+
AMP2N
-
AMP2O
(vbg1)
Vccop
AMP3P
+
AMP3N
-
AMP3O
(vbg1)
Vccop
VRI
+
VRO
(vbg1)
Fig.3- a
Motor-current detection circuit Block Diagram
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TB9081FG
(4) Oscillator /divider
The oscillator has composition with built-in CR, and an Oscillation frequency is Fc=4MHz (typ.). An
oscillator will start operation after internal signal (por_x) release.
4 MHz (clk4m) is used as the system clock of a logic circuit, and an operation clock of the digital filter of the
short-circuit detector of external FET.
Clock 1MHz (clk1m), it is used as an operation clock of the digital filter of an ALARM detector.
Clock 500kHz (clk500k), it is used as an operation clock of a charge pump.
Clock 16kHz (clk16k), it is used as an operation clock of ABIST.
CLKOUT output (terminal) will output a clock set by the SPI (clk4m, clk500k, clk16k).
Vcc
(clk500k)
Divider
Logic
Charge
Pump
(clk1m)
ALARM
filter
(clk16k)
ABIST
control
(clk4m)
VCC1
VCC2
output current
switching time
control
FET Short
filter
Vcc
Low voltage
monitoring
（vcl2）
Vcc
(clk4m)
OSC
CLKOUT
mux
100Ω
SPI
communication
circuit
（vcl1）
（por_x）
Fig.4- a
Oscillator, divider Block Diagram
Fig.4-b
Timing chart of divider
(vcl1）
(vcl2）
(por_x）
（clk4m）
（clk1m）
（clk500k）
（clk16k）
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TB9081FG
(5)
Abnormal detection circuit
TB9081FG is built in miscellaneous abnormal detection circuit, such as the under voltage detection
(VB1, VB2, VCC1, VCC2), over voltage detection (VCC1, VCC2), over temperature detection, external
FET short-circuit detection and frequency abnormal detection.
The contents of a monitoring function list and the internal signal are shown below.
The details of operation are indicated in (5-1) and after.
When failure detection turns off the pre-driver circuit, the short-circuit detection function becomes
invalid. When the operation returns from the abnormalities after that and the operation of a pre-driver
circuit returns, a short-circuit detection function becomes effective again.
●Monitoring function list
Monitoring
function
SPI
Setup
Valid
00
Invalid
01
1*
-
Valid
00
Valid
01
10
11
00
Valid
01
10
11
000
VB1/VB2
Under voltage
VCC1/VCC2
Under voltage
Setup
bit
VCC1/VCC2
Over voltage
Over
temperature
001
010
011
100
101
External FET
Short-circuit
110
Valid
111
000
Valid
001
010
011
1**
0
Abnormalities
in frequency
Pre-driver
prohibition
input
detection
1
*Note 3
SPI
communication
error
Invalid
-
NDIAG
Initial
value
ABIST
pre-driver circuit OFF
-
-
○
L hold
pre-driver circuit OFF
pre-driver circuit OFF
Pre-driver / charge pump / dividing circuit
OFF
Pre-driver / charge pump circuit continued
operation
Pre-driver circuit OFF
Pre-driver / charge pump circuit OFF
pre-driver / charge pump circuit OFF-hold
Pre-driver / charge pump circuit continued
operation
pre-driver circuit OFF
pre-driver / charge pump circuit OFF
pre-driver / charge pump circuit OFF-hold
Pre-driver / charge pump circuit continued
operation
Pre-driver-circuit(only detection phase ) OFF
Pre-driver circuit (only detection phase)
OFF-hold
Pre-driver circuit (all phases) OFF
Pre-driver circuit (all phases) OFF-hold
Pre-driver (all phases) / charge pump circuit
OFF
Pre-driver (all phases) / charge pump circuit
OFF-hold
No detection
Pre-driver / charge pump circuit continued
operation
Pre-driver circuit OFF
Pre-driver / charge pump circuit OFF
Pre-driver / charge pump OFF-hold
No detection
Pre-driver OFF, when inputting inhibit
signals.
charge pump circuit continued operation
Pre-driver OFF, when inputting inhibit
signals.
charge pump circuit continued operation
Pre-driver / charge pump circuit continued
operation
○
-
-
○
○
-
L
H
L
-
○
○
L hold
○
-
○
○
L hold
○
-
-
○
L hold
○
H
L hold
-
H
H
○
L hold
○
L hold
Operation in detection
*Note 1
*Note 5
Register
writing
* Note 2
* Note 4
○
○
○
○
(Low
frequency)
-
-
-
-
*:don't care
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TB9081FG
Note 1)
It describes about Pre-driver, charge pump and divider.
The definition of OFF and OFF-hold is as follows.
OFF: the operation after returning from an abnormal state is possible.
OFF-hold: Hold OFF even after returning from an abnormal state.
Note 2) It describes about NDIAG operation in detection.
The `L hold` hold the output NDIAG=L even after releasing from the abnormal detection.
Note 3) If register setting=0, there is no register writing and NDIAG becomes H, even in case of the
abnormal detection.
If register setting=1, it has register writing and NDIAG becomes L, in case of the abnormal detection.
Note 4) if set to other than `L hold` in NDIAG, register will be cleared and NDIAG=H by recovering from the
abnormal detection,
Note 5) Both Pre-driver circuit (all phases) OFF and Pre-driver circuit OFF turn off power relay and motor
relay Pre-driver. Pre-driver-circuit(only detection phase) OFF turns off the high side and the low side
Pre-driver of detected phase only.
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TB9081FG
(5-1)
VB1/VB2 under voltage detection
Under voltage detection of VB1/VB2 is performed. Two detection comparators and two filters are
built in. If at least one filter outputs “H”, under voltage detection is performed.
The band gap voltage recognized as the reference of a detection comparator is generated from a
separate band gap circuit (BG1 and BG2).
VB1
Vcc
Vcc
vbg2
VB2
－
Vcc
BG2
Filter
SDOUT
under voltage
monitoring2
SPI
communication
circuit
Vcc
vbg1
SDIN
SCK
/CS
＋
－
Vcc
Logic
(vbl2)
＋
BG1
Filter
under voltage
monitoring1
(vbl1)
(clk4m)
（por_x）
NDIAG
Error Logic
(gate_en_u,v,w,r)
Pre-Dr.
Fig.5-1a
VB1/VB2 under voltage detection Block Diagram
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TB9081FG
➣ A-(1) Under voltage of Vb
If VB1 voltage and VB2 voltage are less than the threshold value of the under voltage detection voltage
(vthbll), L detection comparator of Vb outputs “H”.
➣ A-(2) Under voltage detection of Vb
After the detection filter time (Tbl), Vb under voltage detection signal (vbl1 and vbl2) outputs high, the
under voltage state is detected, and the pre-driver circuit is turned off. The oscillating circuit and the
charge pump circuit are not turned off.
The pre-driver circuit holds OFF until the under voltage is released.
The NDIAG output state after detection can be chosen among the 3 modes through SPI
communication.
A setup does not become effective even if the mode is changed in Vb under voltage detection state.
The setup becomes effective after Vb under voltage is released and the register (uvb) is cleared.
➣ A-(3) Return of Vb voltage (under voltage release)
If VB1 voltage and VB2 voltage exceed vthblh, Vb under voltage detection signal (vbl1 and vbl2)
outputs low, the under voltage state is released, and the pre-driver circuit recovers to the normal
operation. In case NDIAG outputs low, it outputs high when the register (uvb) is cleared through SPI
communication.
During under voltage detection, NDIAG outputs low because the register (uvb) is not cleared.
register
uvb_op = “01”
（initial value）
register
uvb_op = “00”
VB1
VB2
under voltage
detection
under voltage
release
under voltage
detection
Vthblh
Vthbll
register
uvb_op = “1*”
under voltage
release
Vthbll
Vthblh
under voltage
detection
under voltage
release
Vthbll
Vthblh
(1)
(2)
(3)
vbl1
Tbl
Tbl
Tbl
vbl2
Tbl
Tbl
Tbl
NDIAG
H*O/
L*O
L hold
control by
input signal
Pre-driver
OFF
control by
input signal
Pre-driver
OFF
control by
input signal
Pre-driver
OFF
control by
input signal
VCPL
VCPH
NDIAG：L hold
Pre-driver：OFF
Fig.5-1b
NDIAG：L output
Pre-driver：OFF
NDIAG：no L output
Pre-driver：OFF
Timing chart of VB1/VB2 under voltage detection
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TB9081FG
(5-2)
VCC1/VCC2 under voltage detection
Under voltage detection of VCC1/VCC2 is performed. Two detection comparators are built in. If at
least one comparator outputs “H”, under voltage detection is performed.
The band gap voltage recognized as the reference of a detection comparator is generated from a
separate band gap circuit (BG1 and BG2).
VCC2
Vcc
Vcc
vbg2
VCC1
＋
(vcl2)
Logic
SDOUT
－
Vcc
BG2
under voltage
monitoring2
SPI
communication
circuit
Vcc
vbg1
＋
SDIN
SCK
/CS
(vcl1)
－
under voltage
monitoring1
＋
(vch)
Filter
－
Vcc
BG1
NDIAG
Error Logic
Vcc
over voltage
monitoring
(gate_en_u,v,w,r)
(cp_en)
(clk4m)
Pre-Dr.
CP1
CP2
（por_x）
Fig.5-2a
VCC1/VCC2 under voltage detection Block Diagram
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TB9081FG
➣ B-(1) Under voltage of Vcc
VCC1 voltage and VCC2 voltage are less than the threshold value of the under voltage detection
voltage (vthcll).
➣ B-(2) Under voltage detection of Vcc
After the response relaxation time (Tcl), Vcc under voltage detection signal (vcl1 and vcl2) outputs high,
the under voltage state is detected, por_x outputs low, and NDIAG outputs low. Then, the pre-driver
circuit, the charge pump, and the oscillating circuit are turned off.
Each circuit holds OFF until the under voltage is released.
➣ B-(3) Return of Vcc voltage (under voltage release)
If VCC1 voltage and VCC2 voltage exceed vthclh, Vcc under voltage detection signal (vcl1 and vcl2)
outputs low, and the under voltage state is released.
➣ B-(4) Recover of normal operation
After LBIST and ABIST are performed, the normal operation recovers in case the judgment of BIST
“OK”. The charge pump circuit starts operation and the pre-driver circuit is turned on. In case the
judgment of BIST “NG”, the charge pump circuit and the pre-driver circuit do not operate.
NDIAG outputs high in the judgment of “OK”, and low in the judgment of “NG”.
(1)
VCC1
VCC2
Vthcll
vcl1
(3)
under voltage
detection
under voltage
release
Vthclh
Tcl
(2)
vcl2
Tcl
por_x
LBIST
ABIST
(4)
NDIAG
H*O/
L*O
control by BIST result
control by
input signal
Pre-driver
OFF
control by BIST result
and input signal
Oscillation start
clk4m
Oscillator
OFF
Charge pump
OFF
VCPL
VCPH
Fig.5-2b
control by BIST result
Timing chart of VCC1/VCC2 under voltage detection
* When Vcc is lower than the detection voltage of Vcc under voltage further, IC will be the stand-by state.
In the stand-by state, functions other than Vcc under voltage detection are turned off.
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TB9081FG
(5-3)
VCC1/VCC2 over voltage detection
Over voltage detection of VCC1/VCC2 is performed. The detection comparator and the filter are
built in. If the filter outputs high, over voltage detection is performed.
VCC2
Vcc
Vcc
vbg2
VCC1
＋
(vcl2)
Logic
SDOUT
－
Vcc
BG2
under voltage
monitoring2
SPI
communication
circuit
Vcc
vbg1
＋
SDIN
SCK
/CS
(vcl1)
－
under voltage
monitoring1
＋
(vch)
Filter
－
Vcc
BG1
NDIAG
Error Logic
Vcc
over voltage
monitoring
(gate_en_u,v,w,r)
(cp_en)
(clk4m)
Pre-Dr.
CP1
CP2
（por_x）
Fig.5-3a
VCC1/VCC2 over voltage detection Block Diagram
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TB9081FG
➣ C-(1) Vcc voltage rise
If VCC1 voltage and VCC2 voltage exceed the threshold value of over voltage detection (vthchh), H
detection comparator of Vcc outputs high.
➣ C-(2) Over voltage detection of Vcc
After the detection filter time (Tch), Vcc over voltage detection signal (vch) outputs high and NDIAG
outputs low.
The operation after detection can be chosen among 4 modes through SPI communication.
A setup does not become effective even if the mode is changed in Vcc over voltage detection state. The
setup becomes effective after Vcc over voltage is released and the register (ovc) is cleared.
➣C-(3) Return of Vcc voltage (over voltage release)
If VCC1 voltage and VCC2 voltage are less than vthchl, Vcc over voltage detection signal (vch) outputs
low and the over voltage is released.
In the case of register ovc_op is 11, even if the over voltage is released, each circuit continues OFF
and NDIAG keeps outputting low. When the register (ovc_op) is 00, 01, and 10, each circuit operates
normally and NDIAG keeps outputting low. When the register (ovc) is cleared through SPI
communication, each circuit operates normally and NDIAG outputs high.
During over voltage detection, the register (ovc) is not cleared and NDIAG outputs low.
register
ovc_op = “01”
（initial value）
register
ovc_op = “00”
high voltage
detection
VCC1
VCC2
(1)
vch
NDIAG
H*O/
L*O
high voltage
release
Vthchh
high voltage
detection
high voltage
release
Vthchh
Vthchl
register
ovc_op = “10”
high voltage
detection
high voltage
release
Vthchh
Vthchl
register
ovc_op = “11”
high voltage
detection
high voltage
release
Vthchh
Vthchl
Vthchl
(3)
(2)
Tch
Tch
L hold
Tch
L hold
control by
input signal
Pre-driver
OFF
Tch
L hold
control by
input signal
Pre-driver
OFF
L hold
control by
input signal
Charge pump
OFF
VCPL
VCPH
NDIAG：L hold
Pre-driver：OFF
NDIAG：L hold
Fig.5-3b
NDIAG：L hold
Pre-driver：OFF
Charge pump：OFF
Pre-driver
OFF-hold
Charge pump
OFF-hold
NDIAG：L hold
Pre-driver：OFF-hold
Charge pump：OFF-hold
Timing chart of VCC1/VCC2 over voltage detection
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TB9081FG
(5-4) Over temperature detection
Three over temperature detection comparators are built in. Three detection comparators and
three filters are built in. If at least one filter outputs high, the over temperature detection becomes
effective.
The band gap voltage recognized as the reference of a detection comparator is generated from
two band gap circuits (BG1 and BG2).
When chip temperature exceeds 170°C, the comparator switches and the over temperature is
detected. The operation after detection can be chosen among 4 modes through SPI
communication. When IC internal temperature becomes 160°C or less, the over temperature
detection is released.
Vcc
Vcc
vbg1
Vcc
+
Logic
-
2VF
SDOUT
AGND
Vcc
SPI
communication
circuit
BG1
SDIN
SCK
/CS
Vcc
Vcc
vbg2
(tsd1det)
+
Filter
Filter
AGND
2VF
Filter
NDIAG
Error Logic
(tsd3det)
Vcc
Vcc
（por_x） (gate_en_u,v,w,r)
(clk4m)
+
Pre-Dr.
-
2VF
(tsd2det)
(cp_en)
CP1
CP2
AGND
Vcc
BG2
Fig.5-4a
Over temperature detection Block Diagram
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TB9081FG
➣ D-(1) Over temperature detection
If the temperature exceeds Tsdh, after the detection filter time (Ttsd), the over temperature detection
signal (tsd1 to 3det) outputs high, and the over temperature is detected.
The operation after detection can be chosen among 4 modes through SPI communication.
A setup does not become effective even if the mode is changed during over temperature state. The
setup becomes effective when the over temperature state is released and the register (tsd*det) is
cleared.
➣ D-(2) Release of over temperature detection
If temperature is less than Tsdl, the over temperature detection signal (tsd1 to 3det) outputs low, and
the over temperature detection is released.
When register (tsd_op) is 11, even if the over temperature detection is released, each circuit continues
OFF and NDIAG leeps outputting low. When the register (tsd_op) is 00, 01, and 10, each circuit
operates normally. However, NDIAG holds low. When the register (tsd*det ) is cleared through SPI
communication, each circuit operates normally and NDIAG outputs high.
During over temperature detection, the register (tsd*det) is not cleared and NDIAG outputs low.
register
tsd_op = “00”
over temperature
release
over temperature
detection
(1)
temp Tsdh
tsd*det
NDIAG
H*O/
L*O
Tsdl
register
tsd_op = “10”
（initial value）
register
tsd_op = “01”
(2)
Ttsd
over temperature
detection
over temperature
release
Tsdl
Tsdh
Ttsd
L hold
over temperature
detection
over temperature
release
over temperature
detection
over temperature
release
Tsdh
Tsdl
Tsdh
Tsdl
Ttsd
L hold
Pre-driver
OFF
control by
input signal
register
tsd_op = “11”
Ttsd
L hold
control by
input signal
Pre-driver
OFF
L hold
control by
input signal
Charge pump
OFF
VCPL
VCPH
NDIAG：L hold
Pre-driver：OFF
NDIAG：L hold
Fig.5-4b
NDIAG：L hold
Pre-driver：OFF
Charge pump：OFF
Pre-driver
OFF-hold
Charge pump
OFF-hold
NDIAG：L hold
Pre-driver：OFF-hold
Charge pump：OFF-hold
Timing chart of over temperature detection
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TB9081FG
(5-5)
Short-circuit detection
Short-circuit of external MOSFET is detected by monitoring the dorain terminal and the source
terminal of the external MOSFET.
When short-circuit is detected, the operation after detection can be chosen among 8 modes
through SPI communication.
Moreover, detection threshold voltage and detection time can be set from four values through SPI
communication.
At the time of short-circuit detection release, in case that the register (sh_op) is 010, 100, and 110,
even if short-circuit detection is released, each circuit continues OFF and NDIAG holds L. When
the register (tsd_op) is 000, 001, 011, and 101, each circuit operates normally, but NDIAG holds L.
When the register (sc**) is cleared through SPI communication, each circuit operates normally and
NDIAG outputs high.
Vcc
HS
Pre-drv.
input circuit
Threshold
setting
vthh_sh
Vcc
HREF
HVO
Logic
Pre-drv.
logic
SPI
communication
circuit
Filter
(shuh)
Filter
SHU
(shvh)
+
-
SHV
+
-
SHW
M
Vcc
(shwho)
Error
Logic
Filter
(shwh)
Filter
(shul)
Filter
(shvl)
Vcc
(shulo)
+
-
LUO
+
-
LVO
Vcc
(shvlo)
Vcc
(shwlo)
Filter
(shwl)
（por_x）
(clk4m)
(gate_en_u)
+
Vcc
(shvho)
(gate_en_r)
HWO
Vcc
(shuho)
NDIAG
HUO
Pre-Drv.
+
-
LWO
LREF
vthl_sh
(Relay)
Threshold
setting
GND
(gate_en_v)
(gate_en_w)
Fig.5-5a
●Table5-5a
Short-circuit detection Block Diagram
Short-circuit detection state
Comparator input
SHU > LREF
SHV > LREF
SHW > LREF
SHU < HREF
SHV < HREF
SHW < HREF
Comparator output
shul = H
shvl = H
shwl = H
shuh = H
shvh = H
shwh = H
Input signal
LUI = H
LVI = H
LWI = H
HUI = H
HVI = H
HWI = H
Abnormal condition
External MOSFET short-circuit of HUO
External MOSFET short-circuit of HVO
External MOSFET short-circuit of HWO
External MOSFET short-circuit of LUO
External MOSFET short-circuit of LVO
External MOSFET short-circuit of LWO
* HREF = HS- Vthh_sh (detection threshold voltage of the High side), LREF = Vthl_sh (detection
threshold voltage of the Low side)
* The detection threshold voltage of the High side is specified between HS and SH* of the IC terminal.
Please set up the threshold value of HREF in consideration of the generating voltage by external
resistance of HS terminal and SH* terminal, and the voltage between drain and source of MOSFET of the
High side.
* The detection threshold voltage of the Low side is specified between SH* and PGND(s) of the IC
terminal.Please set up the threshold value of LREF in consideration of the generating voltage by external
resistance of SH* terminal, the generating voltage by the shunt resistance for current detection, and the
voltage between drain and source of MOSFET of the Low side.
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TB9081FG
register sh_op = “000”
Lo-side
short-circuit
detection
Lo-side
short-circuit
occured
Hi-side
short-circuit
detection
short-circuit
release
H*I
H*I
L*I
L*I
SH*
SH*
sh*h
sh*h
sh*l
short-circuit
release
sh*l
Tsf
Tsf
sh*ho
sh*ho
Tsf
sh*lo
Tsf
Tsf
sh*lo
NDIAG
NDIAG
L hold
H*O
H*O
L*O
L*O
VCPL
VCPH
VCPL
VCPH
L hold
NDIAG：L hold
Fig.5-5b
Timing chart of short-circuit detection (Register (sh_op) = ”000”)
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TB9081FG
register sh_op = “001”, ”011”
Lo-side
short-circuit
occured
Lo-side
short-circuit
detection
Hi-side
short-circuit
detection
short-circuit
release
H*I
H*I
L*I
L*I
SH*
SH*
sh*h
sh*h
sh*l
sh*l
Tsf
Tsf
sh*ho
sh*ho
Tsf
NDIAG
L hold
Pre-drv
OFF
H*O
Tsf
Tsf
sh*lo
sh*lo
NDIAG
short-circuit
release
Pre-drv
OFF
L hold
H*O
L*O
L*O
VCPL
VCPH
VCPL
VCPH
Pre-drv
OFF
Pre-drv
OFF
Pre-drv
OFF
NDIAG：L hold
Pre-driver：OFF
Fig.5-5c
Timing chart of short-circuit detection (Register ( sh_op) = ”001” and ”011”)
* "001" : Pre-driver OFF in only a detection phase.
"011": Pre-driver OFF in all phase
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TB9081FG
register sh_op = “010”(initial value), ”100”
Lo-side
short-circuit
occured
Lo-side
short-circuit
detection
Hi-side
short-circuit
detection
short-circuit
release
H*I
H*I
L*I
L*I
SH*
SH*
sh*h
sh*h
sh*l
short-circuit
release
sh*l
Tsf
Tsf
sh*ho
sh*ho
Tsf
sh*lo
Tsf
Tsf
sh*lo
NDIAG
NDIAG
L hold
Pre-drv
OFF-hold
H*O
H*O
Pre-drv
OFF-hold
L*O
L*O
L hold
Pre-drv
OFF-hold
Pre-drv
OFF-hold
VCPL
VCPH
VCPL
VCPH
NDIAG：L hold
Pre-driver：OFF-hold
Fig.5-5d
Timing chart of short-circuit detection (Register (sh_op) = ”010” and ”100”)
*”010”: Pre-driver OFF in only a detection phase
”100”: Pre-driver OFF in all phase
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TB9081FG
register sh_op = “101”
Lo-side
short-circuit
detection
Lo-side
short-circuit
occured
Hi-side
short-circuit
detection
short-circuit
release
H*I
H*I
L*I
L*I
SH*
SH*
sh*h
sh*h
sh*l
short-circuit
release
sh*l
Tsf
Tsf
sh*ho
sh*ho
Tsf
sh*lo
Tsf
Tsf
sh*lo
NDIAG
NDIAG
L hold
Pre-drv
OFF
H*O
Pre-drv
OFF
H*O
L*O
L*O
Charge pump
OFF
VCPL
VCPH
L hold
Pre-drv
OFF
Pre-drv
OFF
Charge pump Charge pump
OFF
OFF
Charge pump
OFF
Pre-drv
OFF
Charge pump
OFF
VCPL
VCPH
NDIAG：L hold
Pre-driver：OFF
Charge pump：OFF
Fig.5-5e
Timing chart of short-circuit detection (Register (sh_op) = ”101”)
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TB9081FG
register sh_op = “110”
Lo-side
short-circuit
detection
Lo-side
short-circuit
occured
Hi-side
short-circuit
detection
short-circuit
release
H*I
H*I
L*I
L*I
SH*
SH*
sh*h
sh*h
sh*l
sh*l
Tsf
short-circuit
release
Tsf
sh*ho
sh*ho
Tsf
sh*lo
Tsf
Tsf
sh*lo
NDIAG
L hold
NDIAG
Pre-drv
OFF-hold
H*O
H*O
Pre-drv
OFF-hold
L*O
L*O
Charge pump
OFF-hold
VCPL
VCPH
VCPL
VCPH
L hold
Pre-drv
OFF-hold
Pre-drv
OFF-hold
Charge pump
OFF-hold
NDIAG：L hold
Pre-driver：OFF-hold
Charge pump：OFF-hold
Fig.5-5f
Timing chart of short-circuit detection (Register (sh_op) = ”110”)
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TB9081FG
(5-6) Oscillating frequency monitoring
It detects the abnormality in frequency when oscillating frequency is low and high.
The low frequency detection circuit of oscillating frequency resets the input of a comparator for
every clk1m. If the frequency becomes low and reset is overdue, the output of a comparator is
reversed and the abnormality in frequency is detected at the rising edge of the following clk1m.
In the high frequency detection circuit of the oscillating frequency, a comparator repeats H/L
output for every clk1m. When oscillating frequency becomes high, a detection comparator
continues outputting H, and the detection comparator continues outputting H at the falling edge of
1st count of clk1m, the abnormality in high frequency is detected.
The operation in failure detection can be chosen among 5 modes through SPI communication.
A setup does not become effective even if the mode is changed in the frequency failure detection
state. The setup becomes effective after the abnormality in frequency are released and the
register (err_of and err_uf) is cleared.
Abnormality of frequency is not detected in case that the register (ferr_op) is 1**.
When frequency failure detection is released, in case that the register (ferr_op) is 011, even if
frequency failure detection is released, each circuit continues OFF and NDIAG holds L. In case
that the register (ferr_op) is 000, 001, and 010, each circuit recovers to the normal operation.
However, NDIAG holds L. When the register (err_of and err_uf) is cleared through SPI
communication, each circuit recovers to the normal operation and NDIAG outputs high.
Vcc
Logic
SDOUT
Vcc
Low frequency
monitoring
SPI
communication
circuit
Vcc
Vcc
(fsin)
(clk1m)
－
(fso_x)
＋
Cwdl
Abnormal
detection
circuit
SDIN
SCK
/CS
(clkslow)
(vbg2)
Vcc
（por_x）
NDIAG
Error Logic
Vcc
Vcc
(ffin)
－
(ffo_x)
＋
Cwdh
Abnormal
detection
circuit
(clkfast)
（por_x）
(gate_en_u,v,w,r)
(vbg2)
High frequency （por_x）
monitoring
Fig.5-6a
Pre-Dr.
(cp_en)
CP1
CP2
Frequency monitoring circuit
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Toshiba Electronic Devices & Storage Corporation
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TB9081FG
（clk1m）
（fsin）
（fso_x）
detect at the rising edge
of 1st count of clk1m
（clkslow）
NDIAG
Fig.5-6b
Timing chart of frequency monitoring (Low frequency)
（clk1m）
（ffin）
（ffo_x）
detect
at the falling edge
clk1m：1カウント目の
of
1st
count
of clk 1m
立下りエッジで検出
（clkfast）
NDIAG
Fig.5-6c
Timing chart of frequency monitoring (High frequency)
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Toshiba Electronic Devices & Storage Corporation
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2019-02-27
TB9081FG
(6)
ALARM input circuit
As an input terminal of an ALARM signal, TB9081FG have two terminals of ALARM1 and ALARM2.
An ALARM signal controls Enable/Disable of the Pre-drivers (a FET drive circuit, a motor relay drive
circuit, a power supply relay drive circuit).
In the case of ALARM1= "L" or ALARM2= "L", the Pre-drivers will be Disable. In the case of
ALARM1="H" and ALARM2="H", Enable/Disable is decided by the input and internal signal of each
Pre-drivers.
Also, the input side of the ALARM1 and ALARM2 terminal has a built-in digital filter (D.F.) for noise
removal. Digital filter time can be set through the SPI communication.
If ALARM1=“L” or ALARM2=“L” is detected, the short-circuit detection function is enabled.
Vcc
Vcc
Logic
(alm1）
ALARM1
(gate_en_u）
D.F.
50kΩ
Pre-Dr.
U phase
H-side/L-side
(gate_off_u）
(gate_en_v）
Vcc
Pre-Dr.
V phase
H-side/L-side
(gate_off_v）
ALARM2
(alm2）
D.F.
50kΩ
(gate_en_w）
Pre-Dr.
W phase
H-side/L-side
(gate_off_w）
(clk1m）
(gate_en_r）
Pre-Dr.
Relay
(gate_off_r）
Error Logic
(por_x）
Fig.6-a
Table 6-a
FET drive circuit control truth table
Input signal
ALARM1 ALARM2
FET drive circuit control Block Diagram
Internal input signal
(por_x)
Internal control signal
(gate_off_u) (gate_off_v) (gate_off_w) (gate_off_r) (gate_en_u) (gate_en_v) (gate_en_w) (gate_en_r)
*
*
*
L
*
*
*
-
*
*
*
-
*
*
*
-
L
L
L
L
L
L
L
-
L
L
L
-
L
L
L
-
H
-
-
-
H
-
-
-
-
L
-
-
-
L
-
-
-
H
-
-
-
H
-
-
-
-
L
-
-
-
L
-
-
-
H
-
-
-
H
-
FETdrive
circuit
L
*
*
*
L
*
*
*
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
(Note 1) “*”: Don’t care
(Note 2) Although "-":gate_off_* and gate_en_* have logic dependence in phase, the logic dependence to other
phase is nothing.
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Toshiba Electronic Devices & Storage Corporation
31
Disable
Disable
Disable
U phase
Disable
U phase
Enable
V phase
Disable
V phase
Enable
W phase
Disable
W phase
Enable
Relay Disable
Relay Enable
2019-02-27
TB9081FG
(7)
EN_CP input circuit
EN_CP signal controls Enable/Disable of a charge pump circuit.
In the case of input signal EN_CP= "L", the charge pump circuit will be Disable. In the case of
EN_CP="H", Enable/Disable of the charge pump circuit is decided by an internal signal.
Also, the charge pump SW circuit (CP_SW) will be Disable in case of input signal EN_CP = "L" or the
internal signal (por_x) = "L". In the case of EN_CP = (por_x) = "H", it will be Enable.
Vcc
Vcc
Logic
Vb
CP_SW
Divider
(por_x）
Vcc
EN_CP
Control
Circuit
(cp_en）
50kΩ
CP1H
(cp_off）
CP1
CP2
Error Logic
CP2H
(por_x）
VCPH
Fig.7-a
Table 7-a
EN_CP input circuit Block Diagram
Charge-pump-circuit control truth table
Input signal
Internal input signal
Internal control
signal
EN_CP
(por_x)
(cp_off)
(cp_en)
L
H
H
H
*
L
H
H
*
*
L
H
L
L
L
H
Charge pump
circuit
Charge pump
SW circuit
Disable
Disable
Disable
Enable
Disable
Disable
Enable
Enable
(Note) "*":Don't care
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2019-02-27
TB9081FG
(8)
ABIST function
At the time of IC starting, it is diagnosed whether miscellaneous abnormal detection is functioning
normally.
At the time of IC starting, a divider starts operation after VCC1/VCC2 under voltage release, and it
starts diagnosis of ABIST after LBIST completion. Diagnosis of ABIST is performed even when a
judgment of LBIST is NG.
At the time of ABIST starting, the input voltage of the comparator is changed by the switch for diagnosis,
and each detection comparator is reversed. Then, the diagnosis is performed. Diagnosis is performed
in order synchronizing with a clock (clk16k), and diagnostic information is input to the ABIST judgment
circuit. Also, NDIAG=L is kept during the diagnosis.
After completion of all diagnosis, the IC switches to the normal operation. When the abnormal detection
is not diagnosed, NDIAG will be H. When the abnormal detection is diagnosed, NDIAG will be L and
keep the diagnosis information.
A diagnostic part is as follows.
VCC1/VCC2 over voltage detection, VCPH clamp voltage detection, over temperature detection, and
frequency abnormal detection (low frequency side)
Vcc
VCC2
SPI
communication
circuit
Logic
VCC1
over voltage
monitoring
Vcc
＋
vbg1
(vch)
ABIST
Control
－
(clk16k)
（abst_end）
Error Logic
NDIAG
（abst_pass）
BG1
Divider
Normal
operation
Diagnosis
operation
Fig.8-a
(por_x）
ABIST Block Diagram (VCC1/VCC2 over voltage detection)
Table 8-a Circuit operation truth table (CP_SW circuit)
Input signal
EN_CP
Before
ABIST
CP_SW circuit
During
ABIST
ABIST
OK
L
H
Disable
Enable
Enable
Enable
Disable
Enable
ABIST
NG
Disable
Enable
Table 8-b Circuit operation truth table (charge pump circuit)
Input signal
EN_CP
Before
ABIST
Charge pump circuit
During
ABIST
ABIST
OK
ABIST
NG
L
H
Disable
Disable
Disable
Disable
Disable
Enable
Disable
Disable
Before
ABIST
Pre-diver circuit
During
ABIST
ABIST
OK
ABIST
NG
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Table 8-c Circuit operation truth table (pre-driver circuit)
Input signal
ALARM1
ALARM2
L
*
*
L
H
H
(Note)“*”: Don’t care
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Toshiba Electronic Devices & Storage Corporation
Disable
Disable
Enable
33
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TB9081FG
➣ H-(1) IC startup
At the time of IC starting, the divider is started the operation by the release of Vcc under voltage.
➣ H-(2) LBIST running
The divider starts the operation and starts the LBIST.
➣ H-(3) ABIST start up
The ABIST is started after the LBIST.
The detection comparator is changed every 2clk of clk16k, and diagnosed whether the detection
comparator is outputting the failure detection signal correctly.
The comparator for an over temperature detection is diagnosed to the beginning.
➣ H-(4) Diagnosis
Each comparator is diagnosed as follows.
VCC1/VCC2 over voltage, VCPH cramp voltage, and a frequency monitoring (low frequency)
➣ H-(5) ABIST completion
When all detection comparator diagnosis is completed, the IC switches to the normal operation
mode, and the charge pump circuit starts the operation. Then the pre-driver can be ON.
Also, the diagnosis result is output to the NDIAG.
In the case of the diagnosis NG, the charge pump circuit and the pre-driver circuit are kept OFF.
VB1
VB2
VCC1
VCC2
vcl1
vcl2
*2
Vthclh
under voltage
release
(1)
clk4m
(2) LBIST (3)
ABIST
clk16k
abnormal state
diagnosis
normal state
diagnosis
(4)
tsd1det
(5)
tsd2det
tsd3det
vch
vphh
clkl
NDIAG
control by BIST result
VCPL
VCPH
H*O/
L*O
control by BIST result
and EN_CP
*1
control by BIST result
and input signal
Fig.8-b
ABIST timing chart
*1 Regardless of EN_CP input signals, Vcph is equal to Vcpl=Vb-3VF (Vcpl
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