TC59LM836DKB-30,-33,-40
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
288Mbits Network FCRAM2 − 2,097,152-WORDS × 4 BANKS × 36-BITS DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network FCRAMTM containing 301,989,888 memory cells. TC59LM836DKB is organized as 2,097,152-words × 4 banks × 36 bits. TC59LM836DKB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM836DKB can operate fast core cycle compared with regular DDR SDRAM. TC59LM836DKB is suitable for Network and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition.
FEATURES
PARAMETER -30 CL = 4 tCK tRC tRAC Clock Cycle Time (min) CL = 5 CL = 6 Random Read/Write Cycle Time (min) Random Access Time (max) 4.0 ns 3.5 ns 3.0 ns 20.0 ns 20.0 ns 380 mA 100 mA 15 mA TC59LM836DKB -33 4.5 ns 3.75 ns 3.33 ns 22.5 ns 22.5 ns 360 mA 95 mA 15 mA -40 5.0 ns 4.5 ns 4.0 ns 25 ns 25 ns 340 mA 90 mA 15 mA
IDD1S Operating Current (single bank) (max) lDD2P Power Down Current (max) lDD6 Self-Refresh Current (max)
•
•
• • • • • • • • •
• • • • •
Fully Synchronous Operation • Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS. • Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.0 ns minimum Clock: 333 MHz maximum Data: 666 Mbps/pin maximum Quad Independent Banks operation Fast cycle and Short Latency Selectable Data Strobe Distributed Auto-Refresh cycle in 3.9 µs Self-Refresh Power Down Mode Variable Write Length Control Write Latency = CAS Latency-1 Programable CAS Latency and Burst Length CAS Latency = 4, 5, 6 Burst Length = 2, 4 Organization: 2,097,152 words × 4 banks × 36 bits Power Supply Voltage VDD: 2.5 V ± 0.125V VDDQ: 1.4 V ~ 1.9 V Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL. JTAG boundary scan Package: 144Ball BGA, 1mm × 0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ) Notice: FCRAM is trademark of Fujitsu limited, Japan.
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TC59LM836DKB-30,-33,-40
PIN NAMES
PIN A0~A13 BA0, BA1 DQ0~DQ35
CS
NAME Address Input Bank Address Data Input/Output Chip Select Function Control Power Down Control Clock Input Write Data Strobe Read Data Strobe Power (+2.5 V) Ground Power (+1.5V / +1.8 V) (for DQ buffer) Ground (for DQ buffer) Reference Voltage Not Connected
FN
PD
CLK, CLK LDS, UDS LQS, UQS VDD VSS VDDQ VSSQ VREF NC
TMS, TDI, TCK, TDO Boundary Scan Test Access Ports
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TC59LM836DKB-30,-33,-40
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 0.8mm
1 2 3 4 5 6 7 8 9 10 11 12
Index A VDD VSS VSS VDD VDD VSS
0.8mm VSS VDD
1mm
B
VDDQ DQ16 DQ17
VDDQ
VDDQ
DQ0
DQ1
VDDQ
C
VSSQ DQ14 DQ15
VSSQ
VSSQ
DQ2
DQ3
VSSQ
D
VDDQ DQ12 DQ13
VDDQ
VDDQ
DQ4
DQ5
VDDQ
E
VSSQ DQ10 DQ11
VSSQ
VSSQ
DQ6
DQ7
VSSQ
F
VDDQ
LDS
DQ9
VDDQ
VDDQ
DQ8
LQS
VDDQ
G
VSSQ VREF
CLK
VSSQ
VSSQ
A13
FN
VSSQ
H
VSS
PD
CLK
VSS
VSS
CS
NC
VSS
J
VDD
A12
A11
VDD
VDD
BA1
BA0
VDD
K
VSS
A9
A8
VSS
VSS
A0
A10
VSS
L
VDD
A7
A6
VDD
VDD
A2
A1
VDD
M
VDDQ
A5
A4
VDDQ
VDDQ
NC
A3
VDDQ
N
VSSQ
UDS
DQ26
VSSQ
VSSQ DQ27
UQS
VSSQ
P
VDDQ DQ25 DQ24
VDDQ
VDDQ DQ29 DQ28
VDDQ
R
VSSQ DQ23 DQ22
VSSQ
VSSQ DQ31 DQ30
VSSQ
T
VDDQ DQ21 DQ20
VDDQ
VDDQ DQ33 DQ32
VDDQ
U
VSSQ DQ19 DQ18
VSSQ
VSSQ DQ35 DQ34
VSSQ
V
TMS
TCK
VSS
VDD
VDD
VSS
TDO
TDI
: Depopulated ball
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TC59LM836DKB-30,-33,-40
BLOCK DIAGRAM
CLK
CLK PD
DLL CLOCK BUFFER
To each block
CS
FN
COMMAND DECODER
CONTROL SIGNAL GENERATOR
BANK #3 BANK #2 BANK #1 DATA CONTROL and LATCH CIRCUIT READ DATA BUFFER WRITE DATA BUFFER LDS LQS DQ BUFFER UDS UQS DQ0~DQ17 DQ18~DQ35 BANK #0 ROW DECODER
MODE REGISTER A0~A13 ADDRESS BUFFER UPPER ADDRESS LATCH LOWER ADDRESS LATCH
MEMORY CELL ARRAY
BA0, BA1
COLUMN DECODER
REFRESH COUNTER BURST COUNTER
WRITE ADDRESS LATCH/ ADDRESS COMPARATOR
Note: The TC59LM836DKB configuration is 4 Bank of 16384 × 128 × 36 of cell array with the DQ pins numbered DQ0~DQ35.
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TC59LM836DKB-30,-33,-40
ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD VDDQ VIN VOUT VREF Topr Tstg Tsolder PD IOUT PARAMETER Power Supply Voltage Power Supply Voltage (for DQ buffer) Input Voltage Output and DQ pin Voltage Input Reference Voltage Operating Temperature (case) Storage Temperature Soldering Temperature (10 s) Power Dissipation Short Circuit Output Current RATING −0.3~ 3.3 −0.3~VDD+ 0.3 −0.3~VDD+ 0.3 −0.3~VDDQ + 0.3 −0.3~VDD+ 0.3 0~85 −55~150 260 2.5 ±50 UNIT V V V V V °C °C °C W mA NOTES
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(TCASE = 0~85°C)
SYMBOL VDD VDDQ VREF VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) PARAMETER Power Supply Voltage Power Supply Voltage (for DQ buffer) Reference Voltage Input DC High Voltage Input DC Low Voltage Differential Clock DC Input Voltage Differential Input Voltage. CLK and CLK inputs (DC) Input AC High Voltage Input AC Low Voltage Differential Input Voltage. CLK and CLK inputs (AC) Differential AC Input Cross Point Voltage Differential Clock AC Middle Level MIN 2.375 1.4 VDDQ/2 × 95% VREF + 0.125 −0.1 −0.1 0.4 VREF + 0.2 −0.1 0.55 VDDQ/2 − 0.125 VDDQ/2 − 0.125 TYP. 2.5 VDDQ/2 MAX 2.625 1.9 VDDQ/2 × 105% VDDQ + 0.2 VREF − 0.125 VDDQ + 0.1 VDDQ + 0.2 VDDQ + 0.2 VREF − 0.2 VDDQ + 0.2 VDDQ/2 + 0.125 VDDQ/2 + 0.125 UNIT V V V V V V V V V V V V 2 5 5 10 7, 10 3, 6 4, 6 7, 10 8, 10 9, 10 NOTES
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TC59LM836DKB-30,-33,-40
NOTES: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) All voltages referenced to VSS, VSSQ. VREF is expected to track variations in VDDQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC). Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns. Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns. VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. VID is differential voltage of CLK input level and CLK input level. The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device. VISO means {VICK (CLK) + VICK ( CLK )} /2 Refer to the figure below.
CLK Vx
CLK
Vx VICK
Vx
Vx VICK
Vx VICK
VID (AC)
VICK VSS |VID (AC)|
0 V Differential VISO VISO (min) VSS VISO (max)
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) ± 0.04 V.
CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C)
SYMBOL CIN CINC CI/O CNC Input pin Capacitance Clock pin (CLK, CLK ) Capacitance DQ, LDS, UDS, LQS, UQS Capacitance NC pin Capacitance PARAMETER MIN 1.5 1.5 2.5 MAX 3.0 3.0 3.5 1.5 Delta 0.25 0.25 0.5 UNIT pF pF pF pF
Note: These parameters are periodically sampled and not 100% tested.
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TC59LM836DKB-30,-33,-40
RECOMMENDED DC OPERATING CONDITIONS (VDD = 2.5 V ± 0.125 V, VDDQ = 1.4 V ~ 1.9 V, TCASE = 0 ~ 85°C)
SYMBOL PARAMETER -30 Operating Current One bank read or write operation ; tCK = min; IRC = min, IOUT = 0mA ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ, Address inputs change up to 2 times during minimum IRC, Read data change twice per clock cycle Standby Current All banks: inactive state ; tCK = min, CS = VIH, PD = VIH ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; Other input signals change one time during 4 × tCK, DQ and DS inputs change twice per clock cycle Standby (power down) Current All banks: inactive state ; tCK = min, PD = VIL (power down) ; CAS Latency = 6, Free running QS mode ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; Other input signals change one time during 4 × tCK, DQ and DS inputs are floating (VDDQ/2) Write Operating Current (4Banks) 4 Bank interleaved continuous burst write operation ; tCK = min, IRC = min ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; Address inputs change once per clock cycle, DQ and DS inputs change twice per clock cycle Read Operating Current (4Banks) 4 Bank interleaved continuous burst read operation ; tCK = min, IRC = min, IOUT = 0mA ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ; Address inputs change once per clock cycle, Read data change twice per clock cycle Burst Auto Refresh Current Refresh command at every IREFC interval ; tCK = min; IREFC = min ; CAS Latency = 6, Free running QS mode ; 0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ, Address inputs change up to 2 times during minimum IREFC, DQ and DS inputs change twice per clock cycle Self-Refresh Current PD = 0.2 V ; Other input signals are floating (VDDQ/2), DQ and DS inputs are floating (VDDQ/2) MAX -33 -40 UNIT NOTES
IDD1S
380
360
340
1, 2
IDD2N
120
110
100
1, 2
IDD2P
100
95
90
1, 2
mA 850 800 750 1, 2
IDD4W
IDD4R
850
800
750
1, 2
IDD5B
380
360
340
1, 2, 3
IDD6
15
15
15
2
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters define the current between VDD and VSS. 3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI specification.
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TC59LM836DKB-30,-33,-40
RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = 2.5 V ± 0.125 V, VDDQ = 1.4 V ~ 1.9 V, TCASE = 0 ~ 85°C)
SYMBOL ILI ILO IREF IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) PARAMETER Input Leakage Current ( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V) Output Leakage Current (Output disabled, 0 V ≤ VOUT ≤ VDDQ) VREF Current Normal Output Driver VOH = 1.420 V VOL = 0.280 V VOH = 1.420 V VOL = 0.280 V VOH = 1.420 V VOL = 0.280 V VOH = VDDQ – 0.4V VOL = 0.4V VOH = VDDQ – 0.4V VOL= 0.4V Not defined Not defined MIN −5 −5 −5 −5.6 5.6 −9.8 9.8 −2.8 2.8 −4 4 −8 8 mA 1 MAX 5 UNIT µA µA µA NOTES
5 5
Output DC Current Strong Output Driver (V DDQ = 1.7V~1.9V) Weak Output Driver
mA
1
Normal Output Driver
Output DC Current Strong Output Driver (V DDQ = 1.4V~1.6V) Weak Output Driver
Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
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TC59LM836DKB-30,-33,-40
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
(VDD = 2.5 ± 0.125V, VDDQ = 1.4 ∼ 1.9V, TCASE = 0 ∼ 85°C)
-30 SYMBOL tRC PARAMETER MIN Random Cycle Time CL = 4 tCK Clock Cycle Time CL = 5 CL = 6 tRAC tCH tCL tCKQS tQSQ tQSQA tAC tOH tHP tQSP tQSQV tQHS tDQSS tDSPRE tDSPRES tDSPREH tDSP Random Access Time Clock High Time Clock Low Time QS Access Time from CLK Data Output Skew from QS Data Output Skew from QS to All DQ Data Access Time from CLK Data Output Hold Time from CLK CLK half period (minimum of Actual tCH, tCL) QS (read) Pulse Width Data Output Valid Time from QS DQ, QS Hold Skew factor DS (write) Low to High Setup Time DS (write) Preamble Pulse Width DS First Input Setup Time DS First Low Input Hold Time DS High or Low Input Pulse Width DS Input Falling Edge to Clock Setup Time CL = 4 CL = 5 CL = 6 20.0 4.0 3.5 3.0 0.45 × tCK 0.45 × tCK −0.45 −0.5 −0.5 min(tCH, tCL) tHP− tQHS tHP− tQHS 0.8×tCK 0.4×tCK 0 0.3×tCK 0.45×tCK 0.75 0.75 0.75 MAX 5.0 5.0 5.0 20.0 0.45 0.2 0.3 0.5 0.5 0.055 × tCK + 0.17 1.2×tCK 0.55×tCK 0.4 × tCK MIN 22.5 4.5 3.75 3.33 0.45 × tCK 0.45 × tCK −0.45 −0.5 −0.5 min(tCH, tCL) tHP− tQHS tHP− tQHS 0.8×tCK 0.4×tCK 0 0.3×tCK 0.45×tCK 0.8 0.8 0.8 0.45 × tCK 0.8 0.8 0.8 −0.4 × tCK 0.35 0.35 0.6 0.6 MAX 7.5 7.5 7.5 22.5 0.45 0.25 0.35 0. 5 0.5 0.055 × tCK + 0.17 1.2×tCK 0.55×tCK 0.4 × tCK MIN 25 5.0 4.5 4.0 0.45 × tCK 0.45 × tCK −0.5 −0.6 −0.6 min(tCH, tCL) tHP− tQHS tHP− tQHS 0.8×tCK 0.4×tCK 0 0.3×tCK 0.45×tCK 1.0 1.0 1.0 0.45 × tCK 1.0 1.0 1.0 −0.4 × tCK 0.4 0.4 0.7 0.7 MAX 7.5 7.5 7.5 25 0.5 0.3 0.4 0.6 0.6 0.055 × tCK + 0.17 1.2×tCK 0.55×tCK 0.4 × tCK 4, 11 4, 11 3 3 3, 8,10 3, 8 3 4, 8 4, 8 3 3 3 3 3 3 3 3, 8,10 -33 -40 UNIT NOTES
ns 3 4 3 3 4 3, 4 3, 4 3, 4 4 3, 4 3, 4 3, 4
tDSS
tDSPST
DS (write) Postamble Pulse Width 0.45 × tCK CL = 4 0.75 0.75 0.75 −0.4 × tCK 0.3 0.3 0.6 0.6 DS (write) Postamble CL = 5 Hold Time CL = 6 UDS – LDS Skew Data Input Setup Time from DS Data Input Hold Time from DS Command/Address Input Setup Time Command/Address Input Hold Time
tDSPSTH
tDSSK tDS tDH tIS tIH
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TC59LM836DKB-30,-33,-40
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-30 SYMBOL PARAMETER MIN tLZ tHZ tQPDH tPDEX tT tFPDL tREFI tPAUSE Data-out Low Impedance Time from CLK Data-out High Impedance Time from CLK Last output to PD High Hold Time Power Down Exit Time Input Transition Time
PD Low Input Window for Self-Refresh Entry
-33 MAX 0.5 1 5 3.9 1 2 MIN −0.5 0 0.6 0.1 −0.5 × tCK 0.4 200 5 6 7 1 4 5 6 2 2 3 1 7 7 7 1 19 23 25 19 23 25 IREFC 200 MAX 0.5 1 5 3.9 1 2 MIN −0.6 0 0.7 0.1
-40 UNIT NOTES MAX 0.6 1 5 3.9 1 2 cycle µs 3 5 ns 3 3, 6, 8 3, 7, 8
−0.5 0 0.6 0.1 −0.5 × tCK 0.4 200 5 6 7 1 4 5 6 2 2 3 1 7 7 7 1 19 23 25 19 23 25 IREFC 200
−0.5 × tCK 0.4 200 5 6 7 1 4 5 6 2 2 3 1 7 7 7 1 19 23 25 19 23 25 IREFC 200
Auto-Refresh Average Interval Pause Time after Power-up CL = 4 Random Read/Write Cycle Time CL = 5 (applicable to same bank) CL = 6 RDA/WRA to LAL Command Input Delay (applicable to same bank) LAL to RDA/WRA Command Input Delay (applicable to same bank) CL = 4 CL = 5 CL = 6
IRC
IRCD
IRAS
IRBD
Random Bank Access Delay (applicable to other bank) LAL following RDA to WRA Delay (applicable to other bank) BL = 2 BL = 4
IRWD
IWRD
LAL following WRA to RDA Delay (applicable to other bank) CL = 4 Mode Register Set Cycle Time
IRSC
CL = 5 CL = 6
IPD IPDA
PD Low to Inactive State of Input Buffer PD High to Active State of Input Buffer
CL = 4 IPDV Power down mode valid from REF command CL = 5 CL = 6 CL = 4 IREFC Auto-Refresh Cycle Time CL = 5 CL = 6 ICKD ILOCK REF Command to Clock Input Disable at Self-Refresh Entry DLL Lock-on Time (applicable to RDA command)
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TC59LM836DKB-30,-33,-40
AC TEST CONDITIONS
SYMBOL VIH (min) VIL (max) VREF VTT VSWING Vr VID (AC) SLEW VOTR PARAMETER Input High Voltage (minimum) Input Low Voltage (maximum) Input Reference Voltage Termination Voltage Input Signal Peak to Peak Swing Differential Clock Input Reference Level Input Differential Voltage Input Signal Minimum Slew Rate Output Timing Measurement Reference Voltage VALUE VREF + 0.2 VREF − 0.2 VDDQ/2 VREF 0.8 VX (AC) 1.0 2.5 VDDQ/2 UNIT V V V V V V V V/ns V 9 NOTES
VDDQ VIH min (AC) VSWING VREF VIL max (AC) VSS ∆T ∆T SLEW = (VIH min (AC) − VIL max (AC))/∆T Measurement point 25 Ω Output VTT
AC Test Load
NOTES: (1) Transition times are measured between VIH min (DC) and VIL max (DC). Transition (rise and fall) of input signals have a fixed slope. (2) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.8 × tCK, tCK = 3.3 ns, 0.8 × 3.3 ns = 2.64 ns is rounded up to 2.7 ns.) (3) These parameters are measured from the differential clock (CLK and CLK ) AC cross point. (4) These parameters are measured from signal transition point of DS crossing VREF level. (5) The tREFI (max) applies to equally distributed refresh method. The tREFI (min) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum. (6) Low Impedance State is specified at VDDQ/2 ± 0.1 V from steady state. (7) High Impedance State is specified where output buffer is no longer driven. (8) These parameters depend on the clock jitter. These parameters are measured at stable clock. (9) Output timing is measured by using Normal driver strength at VDDQ = 1.7 V ∼ 1.9 V. Output timing is measured by using Strong driver strength at VDDQ = 1.4 V~1.6 V. (10) These parameters are measured at tCK = minimum ∼ 6.0ns. When tCK is longer than 6.0ns, these parameters are specified as below for all speed version. tCKQS (MIN/MAX) = −0.6ns / 0.6ns, tAC (MIN/MAX) = −0.65ns / 0.65ns (11) These parameters are measured at VDDQ = 1.7 V∼1.9 V. Both tDS and tDH at VDDQ = 1.4 V∼1.6 V are specified as below for all speed version. tDS (MIN) = 0.4 ns , tDH (MIN) = 0.4 ns
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TC59LM836DKB-30,-33,-40
POWER UP SEQUENCE
(1) (2) (3) (4) (5) (6) (7) (8) (9) As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection. Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VREF. Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min). After stable power and clock, apply DESL and take PD =H. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1) Issue two or more Auto-Refresh commands (Note: 1). Ready for normal operation after 200 clocks from Extended Mode Register programming.
NOTES: (1) Sequence 6, 7 and 8 can be issued in random order. (2) (3) L = Logic Low, H = Logic High DQ output is Hi-Z state during power upsequence.
2.5V(TYP)
VDD
1.5V or 1.8V(TYP)
VDDQ
1/2 VDDQ (TYP)
VREF
CLK
CLK
tPDEX 200us(min) PD lPDA
Command
lRSC
lRSC
lREFC lLOCK = 200clock cycle(min)
lREFC
DESL RDA MRS DESL op-code
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
op-code
Address
EMRS DQ (Input)
MRS
DS
L/UQS
(Uni-QS mode)
Low
L/UQS
(Free Running mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
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TC59LM836DKB-30,-33,-40
TIMING DIAGRAMS
Input Timing
Command and Address
tCK CLK
CLK
tCK tCH tCL
tIS
CS
tIH 1st
tIS 2nd
tIH
tIS FN tIS A0~A13 BA0, BA1 1st
tIH
tIS 2nd
tIH
tIH UA, BA
tIS LA
tIH
Data
L/UDS tDS DQn (input) tDS DQm (input) tDH tDS tDH tDH tDS tDH
Refer to the Command Truth Table.
Timing of the CLK, CLK
tCH
CLK
tCL VIH VIH (AC) VIL (AC) VIL tCK tT tT
CLK
CLK
VIH VID (AC) VIL
CLK VX VX VX
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TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4) Unidirectional DS/QS mode
tCH CLK
CLK
tCL
tCK
tIS tIH Input (control & addresses) DS (Input)
LAL (after RDA) DESL
tCKQS
CAS latency = 4
tCKQS tQSP tQSP Low
tCKQS Low tQSQA tLZ tQSQ tQSQ Q0 tAC tQSQA tCKQS
LQS (output)
tQSQA tQSQV tQSQV Q1 tAC tQSQA tCKQS tQSP tQSP Low Q2 tAC Q3 tOH tQSQ tHZ
LDQ (output)
Hi-Z
UQS (output)
Low tQSQA tQSQA tQSQV Q2 tAC tCKQS tQSQ tHZ Q3 tOH tCKQS tQSP tQSP
UDQ (output)
Hi-Z tLZ tAC
Q0
Q1 tAC
CAS latency = 5
tCKQS Low tQSQA tLZ tQSQ tQSQ Q0 tAC tQSQA tCKQS
LQS (output)
Low tQSQA tQSQV tQSQV Q1 tAC tQSQA tCKQS tQSP tQSP Low tQSQA tQSQ tQSQA tHZ tQSQV Q0 tLZ tAC Q1 tAC Q2 tAC Q3 tOH Q2 tAC Q3 tOH tQSQ tHZ
LDQ (output)
Hi-Z
UQS (output)
Low
UDQ (output)
Hi-Z
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TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4) Unidirectional DS/QS mode
tCH CLK
CLK
tCL
tCK
tIS tIH Input (control & addresses) DS (Input)
LAL (after RDA) DESL
tCKQS
CAS latency = 6
tCKQS tQSP tQSP Low
tCKQS Low tQSQA tLZ tQSQ tQSQ Q0 tAC tQSQA tCKQS
LQS (output)
tQSQA tQSQV tQSQV Q1 tAC tQSQA tCKQS tQSP tQSP Low Q2 tAC Q3 tOH tQSQ tHZ
LDQ (output)
Hi-Z
UQS (output)
Low tQSQA
tQSQ tQSQA tQSQV tHZ Q0 Q1 tAC Q2 tAC Q3 tOH
UDQ (output)
Hi-Z tLZ tAC
Note:
DQ0 to DQ35 are aligned with QS. The correspondence of LQS, UQS to DQ. LQS UQS DQ0~DQ17 DQ18~DQ35
Rev 1.3 2005-03-07 15/65
TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4) Unidirectional DS/Free Running QS mode
tCH CLK
CLK
tCL
tCK
tIS tIH
LAL (after RDA) DESL
Input (control & addresses) DS (Input)
tCKQS
CAS latency = 4
tCKQS tQSP tQSP
tCKQS
LQS (output) tQSQA tLZ tQSQ LDQ (output) Hi-Z tAC tQSQA tCKQS UQS (output) tQSQA UDQ (output) Hi-Z tLZ tAC Q0 tQSQA tQSQV Q2 tAC tQSQ tHZ Q3 tOH tCKQS tQSP tQSP tQSQ Q0 Q1 tAC tQSQA tQSP tQSP tQSQA tQSQV tQSQV Q2 tAC Q3 tOH tCKQS tQSQ tHZ
Q1 tAC
tCKQS
CAS latency = 5
tCKQS
LQS (output) tQSQA tLZ tQSQ LDQ (output) Hi-Z tAC tQSQA tCKQS UQS (output) tQSQA UDQ (output) Hi-Z tLZ tAC Q0 tQSQA tQSQV Q2 tAC tQSQ tHZ Q3 tOH tQSQ Q0 Q1 tAC tQSQA tCKQS tQSP tQSP tQSQA tQSQV tQSQV Q2 tAC Q3 tOH tQSQ tHZ
Q1 tAC
Rev 1.3 2005-03-07 16/65
TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4) Unidirectional DS/Free Running QS mode
tCH CLK
CLK
tCL
tCK
tIS tIH
LAL (after RDA) DESL
Input (control & addresses) DS (Input)
tCKQS
CAS latency = 6
tCKQS tQSP tQSP
tCKQS
LQS (output) tQSQA tLZ tQSQ LDQ (output) Hi-Z tAC tQSQA tCKQS UQS (output) tQSQA UDQ (output) Hi-Z tLZ tAC Q0 tQSQA tQSQV Q2 tAC tQSQ tHZ Q3 tOH tQSQ Q0 Q1 tAC tQSQA tCKQS tQSP tQSP tQSQA tQSQV tQSQV Q2 tAC Q3 tOH tQSQ tHZ
Q1 tAC
Note:
DQ0 to DQ35 are aligned with QS. The correspondence of LQS, UQS to DQ. LQS UQS DQ0~DQ17 DQ18~DQ35
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TC59LM836DKB-30,-33,-40
Write Timing (Burst Length = 4) Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
tCH CLK
CLK
tCL
tCK
tIS tIH LAL (after WRA) DESL tDQSS tDSPRES tDSPSTH tDSS
Input (control & addresses)
CAS latency = 4
tDSPREH tDSP tDSP tDSP tDSPST
L/UDS (input) Preamble tDSPRE tDH DQ (input) D0 D1 tDQSS tDSPRES tDSS tDSPSTH tDSS tDSP tDSP tDSPST tDS tDSS tDS tDH D2 Postamble tDS tDH D3
CAS latency = 5
t tDSPREH DSP
L/UDS (input) Preamble tDSPRE Postamble tDS tDH D1 tDQSS tDSPRES tDSPREH tDSS tDS tDS tDH D2 D3 tDSS tDSPSTH tDH
DQ (input) tDQSS
D0
CAS latency = 6
tDSP tDSP tDSP tDSPST
L/UDS (input) Preamble tDSPRE tDS tDH DQ (input) tDQSS L/UQS (Uni-QS) Low D0 D1 tDQSS tDS tDS tDH D2 D3 tDH Postamble
L/UQS (Free Runninig) Note: DQ0 to DQ35 are sampled at both edges of DS. The correspondence of LDS, UDS to DQ. LDS UDS DQ0~DQ17 DQ18~DQ35
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TC59LM836DKB-30,-33,-40
tREFI, tPAUSE, IXXXX Timing
CLK
CLK
tREFI, tPAUSE, IXXXX tIS tIH tIS tIH
Input (control & addresses) Command Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc. Command
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TC59LM836DKB-30,-33,-40
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL DESL RDA WRA FUNCTION Device Deselect Read with Auto-close Write with Auto-close
CS
FN × H L
BA1~BA0 × BA BA
A13~A10 × UA UA
A9~A8 × UA UA
A7 × UA UA
A6~A0 × UA UA
H L L
• The Second Command (The next clock of RDA or WRA command)
SYMBOL LAL REF MRS FUNCTION Lower Address Latch Auto-Refresh Mode Register Set
CS
FN × × ×
BA1~ BA0 × × V
A13~ A12 V × L
A11~ A10 × × L
A9 × × L
A8 × × L
A7 × × V
A6~A0 LA × V
H L L
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address, LA = Lower Address 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and the command table below.
Read Command Table
COMMAND (SYMBOL) RDA (1st) LAL (2nd)
CS
FN H ×
BA1~BA0 BA ×
A13~A10 UA ×
A9~A8 UA ×
A7 UA ×
A6~A0 UA LA
NOTES
L H
Write Command Table
COMMAND(SYMBOL) WRA (1st) LAL (2nd)
CS
FN L ×
BA1~BA0 BA ×
A13 UA VW0
A12 UA VW1
A11 UA ×
A10 UA ×
A9~A8 UA ×
A7 UA ×
A6~A0 UA LA
L H
Notes: 5. A13~ A12 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Burst Length Function Write All Words BL=2 Write First One Word Reserved Write All Words BL=4 Write First Two Words Write First One Word L H H H H L H VW0 L VW1 × × L L
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TC59LM836DKB-30,-33,-40
FUNCTION TRUTH TABLE (continued)
Mode Register Set Command Table
COMMAND (SYMBOL) RDA (1st) MRS (2nd)
CS
FN H ×
BA1~BA0 × V
A13~A9 × V
A8 × V
A7 × V
A6~A0 × V
NOTES
L L
6
Notes: 6. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
FUNCTION COMMAND (SYMBOL) WRA (1st) REF (2nd) CURRENT STATE Standby Active
PD
n−1 H H
CS
FN
BA1~BA0 × ×
A13~A9 × ×
A8 × ×
A7 × ×
A6~A0 NOTES × ×
n H H L L L ×
Active Auto-Refresh
Self-Refresh Command Table
FUNCTION COMMAND (SYMBOL) WRA (1st) REF (2nd) SELFX CURRENT STATE Standby Active Self-Refresh Self-Refresh
PD
n−1 H H L L
CS
FN
BA1~BA0 × × × ×
A13~A9 × × × ×
A8 × × × ×
A7 × × × ×
A6~A0 NOTES × × × × 9 7, 8
n H L L H L L × H L × × ×
Active Self-Refresh Entry Self-Refresh Continue Self-Refresh Exit
Power Down Table
FUNCTION COMMAND (SYMBOL) PDEN PDEX CURRENT STATE Standby Power Down Power Down
PD
n−1 H L L
CS
FN × × ×
BA1~BA0 × × ×
A13~A9 × × ×
A8 × × ×
A7 × × ×
A6~A0 NOTES × × × 9
n L L H H × H 8
Power Down Entry Power Down Continue Power Down Exit Notes: 7. 8.
PD has to be brought to Low within tFPDL from REF command. PD should be brought to Low after DQ’s state turned high impedance.
9. When PD is brought to High from Low, this function is executed asynchronously.
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TC59LM836DKB-30,-33,-40
FUNCTION TRUTH TABLE (continued)
CURRENT STATE
PD
n−1 H H H H H L H H H H L H H H H L H H H H H L H H H H H L H H H H H L H H H H H L H L
CS
FN × H L × × × × × × × × × × × × × × H L × × × × H L × × × × H L × × × × H L × × × × × × × × × × ×
ADDRESS × BA, UA BA, UA × × × LA Op-code × × × LA × × × × × BA, UA BA, UA × × × × BA, UA BA, UA × × × × BA, UA BA, UA × × × × BA, UA BA, UA × × × × × × × × × × ×
COMMAND DESL RDA WRA PDEN LAL MRS/EMRS PDEN MRS/EMRS LAL REF PDEN REF (self) DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN PDEX SELFX
ACTION NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State Begin Read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh Entry Invalid Continue Burst Read to End Illegal Illegal Illegal Illegal Invalid Data Write&Continue Burst Write to End Illegal Illegal Illegal Illegal Invalid NOP → Idle after IREFC Illegal Illegal Self-Refresh Entry Illegal Refer to Self-Refreshing State NOP → Idle after IRSC Illegal Illegal Illegal Illegal Invalid Invalid Maintain Power Down Mode Exit Power Down Mode → Idle after tPDEX Illegal Invalid Maintain Self-Refresh Exit Self-Refresh → Idle after IREFC Illegal
NOTES
n H H H L L × H H L L × H H L L × H H H L L × H H H L L × H H H L L × H H H L L × × L H H × L H H H L L H L × H L H L × H L H L × H L L H L × H L L H L × H L L H L × H L L H L × × × H L × × H L
Idle
10
Row Active for Read
Row Active for Write
Read
11 11
Write
11 11
Auto-Refreshing
12
Mode Register Accessing
Power Down
L L H L L L
Self-Refreshing
Notes: 10. Illegal if any bank is not idle. 11. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA). 12. Illegal if tFPDL is not satisfied.
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TC59LM836DKB-30,-33,-40
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
ADDRESS Register BA1 0
*1
BA0 0
*1
A13~A8 0
A7
*3
A6~A4 CL
A3 BT
A2~A0 BL
TE
A7 0 1
TEST MODE (TE) Regular (default) Test Mode Entry
A3 0 1
BURST TYPE (BT) Sequential Interleave
A6 0 0 0 1 1 1 1
A5 0 1 1 0 0 1 1
A4 × 0 1 0 1 0 1
CAS LATENCY (CL)
A2 0 0 0 0 1
A1 0 0 1 1 ×
A0 0 1 0 1 ×
BURST LENGTH (BL) Reserved 2 4 Reserved
*2 *2
Reserved Reserved Reserved 4 5 6 Reserved
*2 *2 *2
*2
Extended Mode Register (Notes: 4)
ADDRESS Register BA1 0
*4
BA0 1
*4
A13~A7 0
A6~A5 SS
A4~A3 DIC (QS)
A2~A1 DIC (DQ)
A0
*5
DS
QS A6 0 0 1 1 A5 0 1 0 1 STROBE SELECT A4 Reserved Reserved
*2 *2
DQ A2 0 0 1 1 A1 0 1 0 1
A3 0 1 0 1
OUTPUT DRIVE IMPEDANCE CONTROL (DIC) Normal Output Driver Strong Output Driver Weak Output Driver Reserved
0 0 1 1
Unidirectional DS/QS Unidirectional DS/Free Running QS
A0 0 1 Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0. 2. “Reserved” places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to “0” (low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
DLL SWITCH (DS) DLL Enable DLL Disable
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TC59LM836DKB-30,-33,-40
STATE DIAGRAM
SELFREFRESH SELFX ( PD = H)
PD = L
POWER DOWN PDEX ( PD = H) PDEN ( PD = L) STANDBY (IDLE) MODE REGISTER WRA RDA MRS
PD = H
AUTOREFRESH
REF
ACTIVE (RESTORE)
ACTIVE
LAL
LAL
WRITE (BUFFER)
READ
Command input Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input.
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TC59LM836DKB-30,-33,-40
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 5 cycles Command RDA LAL DESL IRAS = 4 cycles RDA LAL
IRC = 5 cycles DESL IRAS = 4 cycles RDA LAL
IRC = 5 cycles DESL IRAS = 4 cycles UA RDA
IRCD=1 cycle Address UA LA
IRCD=1 cycle UA LA
IRCD=1 cycle UA LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 4 DQ (output) BL = 4 DS (input) QS (output) Low CL = 4 DQ (output) Hi-Z Q0 Q1 Q2 Q3 CL = 4 Q0 Q1 Q2 Q3 CL = 4 Q0 Hi-Z Q0 Q1 CL = 4 Q0 Q1 CL = 4 Q0
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 4 DQ (output) BL = 4 DS (input) QS (output) CL = 4 DQ (output) Hi-Z Q0 Q1 Q2 Q3 CL = 4 Q0 Q1 Q2 Q3 CL = 4 Q0 Hi-Z Q0 Q1 CL = 4 Q0 Q1 CL = 4 Q0
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TC59LM836DKB-30,-33,-40
SINGLE BANK READ TIMING (CL = 5)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 6 cycles Command RDA LAL DESL IRAS = 5 cycles RDA LAL
IRC = 6 cycles DESL IRAS = 5 cycles RDA LAL DESL
IRCD=1 cycle Address UA LA
IRCD=1 cycle UA LA
IRCD=1 cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 5 DQ (output) BL = 4 DS (input) QS (output) Low CL = 5 DQ (output) Hi-Z Q0 Q1 Q2 Q3 CL = 5 Q0 Q1 Q2 Q3 Hi-Z Q0 Q1 CL = 5 Q0 Q1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 5 DQ (output) BL = 4 DS (input) QS (output) CL = 5 DQ (output) Hi-Z Q0 Q1 Q2 Q3 CL = 5 Q0 Q1 Q2 Q3 Hi-Z Q0 Q1 CL = 5 Q0 Q1
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TC59LM836DKB-30,-33,-40
SINGLE BANK READ TIMING (CL = 6)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 7 cycles Command RDA LAL DESL IRAS = 6 cycles RDA LAL
IRC = 7 cycles DESL IRAS = 6 cycles RDA LAL
IRCD=1 cycle Address UA LA
IRCD=1 cycle UA LA
IRCD=1 cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 6 DQ (output) BL = 4 DS (input) QS (output) Low CL = 6 DQ (output) Hi-Z Q0 Q1 Q2 Q3 CL = 6 Q0 Q1 Q2 Hi-Z Q0 Q1 CL = 6 Q0 Q1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 6 DQ (output) BL = 4 DS (input) QS (output) CL = 6 DQ (output) Hi-Z Q0 Q1 Q2 Q3 CL = 6 Q0 Q1 Q2 Hi-Z Q0 Q1 CL = 6 Q0 Q1
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TC59LM836DKB-30,-33,-40
SINGLE BANK WRITE TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 5 cycles Command WRA LAL DESL IRAS = 4 cycles WRA LAL
IRC = 5 cycles DESL IRAS = 4 cycles WRA LAL
IRC = 5 cycles DESL IRAS = 4 cycles UA WRA
IRCD=1 cycle Address UA LA
IRCD=1 cycle UA LA
IRCD=1 cycle UA LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low WL = 3 DQ (input) BL = 4 DS (input) QS (output) Low WL = 3 DQ (input) D0 D1 D2 D3 WL = 3 D0 D1 D2 D3 WL = 3 D0 D1 D2 D3 D0 D1 WL = 3 D0 D1 WL = 3 D0 D1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) WL = 3 DQ (input) BL = 4 DS (input) QS (output) WL = 3 DQ (input) D0 D1 D2 D3 WL = 3 D0 D1 D2 D3 WL = 3 D0 D1 D2 D3 D0 D1 WL = 3 D0 D1 WL = 3 D0 D1
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TC59LM836DKB-30,-33,-40
SINGLE BANK WRITE TIMING (CL = 5)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 6 cycles Command WRA LAL DESL IRAS = 5 cycles WRA LAL
IRC = 6 cycles DESL IRAS = 5 cycles WRA LAL DESL
IRCD=1 cycle Address UA LA
IRCD=1 cycle UA LA
IRCD=1 cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low WL = 4 DQ (input) BL = 4 DS (input) QS (output) Low WL = 4 DQ (input) D0 D1 D2 D3 WL = 4 D0 D1 D2 D3 D0 D1 WL = 4 D0 D1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) WL = 4 DQ (input) BL = 4 DS (input) QS (output) WL = 4 DQ (input) D0 D1 D2 D3 WL = 4 D0 D1 D2 D3 D0 D1 WL = 4 D0 D1
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TC59LM836DKB-30,-33,-40
SINGLE BANK WRITE TIMING (CL = 6)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 7 cycles Command WRA LAL DESL IRAS = 6 cycles WRA LAL
IRC = 7 cycles DESL IRAS = 6 cycles WRA LAL
IRCD=1 cycle Address UA LA
IRCD=1 cycle UA LA
IRCD=1 cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low WL = 5 DQ (input) BL = 4 DS (input) QS (output) Low WL = 5 DQ (input) D0 D1 D2 D3 WL = 5 D0 D1 D2 D3 D0 D1 WL = 5 D0 D1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) WL = 5 DQ (input) BL = 4 DS (input) QS (output) WL = 5 DQ (input) D0 D1 D2 D3 WL = 5 D0 D1 D2 D3 D0 D1 WL = 5 D0 D1
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TC59LM836DKB-30,-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 5 cycles Command RDA LAL DESL WRA LAL
IRC = 5 cycles DESL RDA LAL
IRC = 5 cycles DESL WRA
Address
UA
LA
UA
LA
UA
LA
UA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 4 DQ BL = 4 DS (input) QS (output) Low CL = 4 DQ Hi-Z Q0 Q1 Q2 Q3 WL = 3 D0 D1 D2 D3 CL = 4 Q0 Hi-Z Q0 Q1 WL = 3 D0 D1 CL = 4 Q0
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 4 DQ BL = 4 DS (input) QS (output) CL = 4 DQ Hi-Z Q0 Q1 Q2 Q3 Read data WL = 3 D0 D1 D2 D3 Write data CL = 4 Q0 Hi-Z Q0 Q1 WL = 3 D0 D1 CL = 4 Q0
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TC59LM836DKB-30,-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 5)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 6 cycles Command RDA LAL DESL WRA LAL
IRC = 6 cycles DESL RDA LAL DESL
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 5 DQ BL = 4 DS (input) QS (output) Low CL = 5 DQ Hi-Z Q0 Q1 Q2 Q3 WL = 4 D0 D1 D2 D3 Hi-Z Q0 Q1 WL = 4 D0 D1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 5 DQ BL = 4 DS (input) QS (output) CL = 5 DQ Hi-Z Q0 Q1 Q2 Q3 Read data WL = 4 D0 D1 D2 D3 Write data Hi-Z Q0 Q1 WL = 4 D0 D1
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TC59LM836DKB-30,-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 6)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRC = 7 cycles Command RDA LAL DESL WRA LAL
IRC = 7 cycles DESL RDA LAL
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 6 DQ BL = 4 DS (input) QS (output) Low CL = 6 DQ Hi-Z Q0 Q1 Q2 Q3 WL = 5 D0 D1 D2 D3 Hi-Z Q0 Q1 WL = 5 D0 D1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 6 DQ BL = 4 DS (input) QS (output) CL = 6 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Read data WL = 5 D0 D1 D2 D3 Write data Hi-Z Q0 Q1 WL = 5 D0 D1
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TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles RDA LAL RDA LAL
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank Add.
Bank "a"
Bank "b" IRC (Bank"a") = 5 cycles
Bank "a"
Bank "b"
Bank "c"
Bank "d"
Bank "a"
Bank "b"
IRC (Bank"b") = 5 cycles
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 4 CL = 4 DQ (output) BL = 4 DS (input) QS (output) Low CL = 4 CL = 4 DQ (output) Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0 Qc1 Qc2
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0 Qc1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 4 DQ (output) BL = 4 DS (input) QS (output) CL = 4 DQ (output) Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0 Qc1 Qc2
CL = 4 Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0 Qc1
CL = 4
Note: lRC to the same bank must be satisfied.
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TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ TIMING (CL = 5)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles RDA UA Bank "a" LAL LA RDA UA Bank "b" IRC (Bank"a") = 6 cycles LAL LA DESL
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles RDA UA Bank "a" LAL LA RDA UA Bank "b" LAL LA RDA UA Bank "c" LAL LA RDA UA Bank "d" LAL LA RDA UA Bank "a" LAL LA
Command Address Bank Add.
IRC (Bank"b") = 6 cycles
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 5 CL = 5 DQ (output) BL = 4 DS (input) QS (output) Low CL = 5 CL = 5 DQ (output) Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input)
QS (output) CL = 5 CL = 5 DQ (output) BL = 4 DS (input) Hi-Z
Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0Qb1
QS (output) CL = 5 CL = 5 DQ (output) Hi-Z Note: lRC to the same bank must be satisfied.
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2
Rev 1.3 2005-03-07 35/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ TIMING (CL = 6)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles RDA UA Bank "a" LAL LA RDA UA Bank "b" IRC (Bank"a") = 7 cycles LAL LA DESL
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles RDA UA Bank "a" IRC (Bank"b") = 7 cycles LAL LA RDA UA Bank "b" LAL LA RDA UA Bank "c" LAL LA RDA UA Bank "d" LAL LA RDA UA Bank "a"
Command Address Bank Add.
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low CL = 6 CL = 6 DQ (output) BL = 4 DS (input) QS (output) Low CL = 6 CL = 6 DQ (output) Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) CL = 6 CL = 6 DQ (output) BL = 4 DS (input) QS (output) CL = 6 CL = 6 DQ (output) Hi-Z Note: lRC to the same bank must be satisfied.
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Rev 1.3 2005-03-07 36/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK WRITE TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles WRA LAL WRA LAL
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
Command
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
LA
UA Bank "b"
Bank Add.
IRC (Bank"a") = 5 cycles IRC (Bank"b") = 5 cycles
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low WL = 3 WL = 3 DQ (input) BL = 4 DS (input) QS (output) Low WL = 3 WL = 3 DQ (input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1 Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1 Dd0 Dd1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) WL = 3 WL = 3 DQ (input) BL = 4 DS (input) QS (output) WL = 3 WL = 3 DQ (input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1 Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1 Dd0 Dd1
Note: lRC to the same bank must be satisfied.
Rev 1.3 2005-03-07 37/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK WRITE TIMING (CL = 5)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles WRA UA Bank "a" LAL LA WRA UA Bank "b" IRC (Bank"a") = 6 cycles LAL LA DESL
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles WRA UA Bank "a" IRC (Bank"b") = 6 cycles LAL LA WRA UA Bank "b" LAL LA WRA UA Bank "c" LAL LA WRA UA Bank "d" LAL LA WRA UA Bank "a" LAL LA
Command Address Bank Add.
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low WL = 4 WL = 4 DQ (input) BL = 4 DS (input) QS (output) Low WL = 4 WL = 4 DQ (input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) WL = 4 WL = 4 DQ (input) BL = 4 DS (input) QS (output) WL = 4 DQ (input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1
WL = 4
Note: lRC to the same bank must be satisfied.
Rev 1.3 2005-03-07 38/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK WRITE TIMING (CL = 6)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles WRA LAL WRA LAL DESL
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles WRA LAL WRA LAL WRA LAL WRA LAL WRA
Command
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
Bank Add.
IRC (Bank"a") = 7 cycles IRC (Bank"b") = 7 cycles
Unidirectional DS/QS mode
BL = 2 DS (input) QS (output) Low WL = 5 WL = 5 DQ (input) BL = 4 DS (input) QS (output) Low WL = 5 WL = 5 DQ (input)
Da0 Da1 Da2 Da3 Db0 Db1Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1
Unidirectional DS/Free Running QS mode
BL = 2 DS (input) QS (output) WL = 5 WL = 5 DQ (input) BL = 4 DS (input) QS (output) WL = 5 WL = 5 DQ (input) Note: lRC to the same bank must be satisfied.
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Da0 Da1 Db0 Db1 Da0 Da1 Db0 Db1
Rev 1.3 2005-03-07 39/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
CLK
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA
Command
IWRD = 1 cycle Address Bank Add. UA Bank "a" LA UA Bank "b"
IRWD = 2 cycles IWRD = 1 cycle LA UA Bank "c" IRC (Bank"a") LA UA Bank "d" IRC (Bank"b")
IRWD = 2 cycles LA UA Bank "a" LA UA Bank "b" LA UA Bank "c"
Unidirectional DS/QS mode
CL = 4 DS (input) QS (output)
Low WL = 3
CL = 4
Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1
DQ CL = 5 DS (input) QS (output)
Hi-Z
Low WL = 4 CL = 5
Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1
DQ CL = 6 DS (input) QS (output)
Hi-Z
Low WL = 5 CL = 6
Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1
DQ CL = 4 DS (input) QS (output)
Hi-Z
Unidirectional DS/Free Running QS mode
CL = 4 WL = 3 DQ CL = 5 DS (input) QS (output) WL = 4 DQ CL = 6 DS (input) QS (output) WL = 5 DQ Hi-Z Note: lRC to the same bank must be satisfied. Hi-Z CL = 5
Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 6
Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1
Rev 1.3 2005-03-07 40/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
CLK
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRBD = 2 cycles WRA LAL RDA LAL DESL IRWD = 3 cycles LA UA WRA LAL RDA LAL DESL IRWD = 3 cycles LA UA Bank "a" WRA LAL RDA LAL
Command
IWRD = 1 cycle Address Bank Add. UA Bank "a" LA UA Bank "b"
IWRD = 1 cycle LA UA Bank "d" IRC (Bank"b")
IWRD = 1 cycle LA UA Bank "b" LA
Bank "c" IRC (Bank"a")
Unidirectional DS/QS mode
CL = 4 DS (input) QS (output)
Low WL = 3 CL = 4
Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3
DQ CL = 5 DS (input)
Hi-Z
QS (output)
Low CL = 5 WL = 4
DQ CL = 6 DS (input) QS (output)
Hi-Z
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
Low WL = 5 CL = 6
Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1
DQ CL = 4
Hi-Z
Unidirectional DS/Free Running QS mode
DS (input) QS (output) WL = 3 DQ CL = 5 DS (input) QS (output) WL = 4 DQ CL = 6 DS (input) CL = 6 WL = 5 DQ Hi-Z Note: lRC to the same bank must be satisfied.
Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1
CL = 4
Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3
Hi-Z
CL = 5
Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3
Hi-Z
QS (output)
Rev 1.3 2005-03-07 41/65
TC59LM836DKB-30,-33,-40
WRITE with VARIABLE WRITE LENGTH (VW) CONTROL (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BL = 2, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL
Address
UA
LA=#3 VW=All
UA
LA=#1 VW=1
VW0 = Low VW1 = don't care
VW0 = High VW1 = don't care
Bank Add.
Bank "a"
Bank "a"
DS (input) DQ (input) Lower Address BL = 4, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL WRA LAL DESL
D0 D1
D0
#3 #2
#1 (#0) Last one data is masked.
Address
UA
LA=#3 VW=All
UA
LA=#1 VW=1
UA
LA=#2 VW=2
VW0 = High VW1 = Low
VW0 = High VW1 = High
VW0 = Low VW1 = High
Bank Add.
Bank "a"
Bank "a"
Bank "a"
DS (input) DQ (input) Lower Address
D0 D1 D2 D3
D0
D0 D1
#3 #0 #1 #2
#1 (#2)(#3)(#0) Last three data are masked.
#2 #3 (#0)(#1) Last two data are masked.
Note: DS input must be continued till end of burst count even if some of laster data is masked.
Rev 1.3 2005-03-07 42/65
TC59LM836DKB-30,-33,-40
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
IPDA Command RDA LAL DESL DESL
RDA or WRA
Address
UA
LA tIS tIH IPD = 2 cycle
UA
PD
tQPDH
Unidirectional DS/QS mode
DS (input) QS (output)
lRC(min) , tREFI(max)
tPDEX
Low CL = 4
DQ (output)
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Unidirectional DS/Free Running QS mode
DS (input)
QS (output) CL = 4 DQ (output) Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Power Down Entry
Power Down Exit
Note: PD must be kept "High" level until end of Burst data output. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
Rev 1.3 2005-03-07 43/65
TC59LM836DKB-30,-33,-40
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
IPDA Command WRA LAL DESL DESL
RDA or WRA
Address
UA
LA tIS tIH IPD = 2 cycle
UA
PD
WL = 3
2 clock cycles lRC(min) , tREFI(max) tPDEX
Unidirectional DS/QS mode
DS (input) QS (output)
Low WL = 3
DQ (input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS (input) QS (output) WL = 3 DQ (input)
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
Rev 1.3 2005-03-07 44/65
TC59LM836DKB-30,-33,-40
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRSC = 7 cycles Command RDA LAL DESL RDA MRS DESL
RDA or WRA
LAL
Address
UA
LA
Valid (opcode)
UA
LA
Bank Add.
BA CL + BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode
DS (input) QS (output)
Low
DQ (output)
Q0 Q1
Unidirectional DS/Free Running QS mode
DS (input)
QS (output)
DQ (output)
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2 clock cycles.
Rev 1.3 2005-03-07 45/65
TC59LM836DKB-30,-33,-40
MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRSC = 7 cycles Command WRA LAL DESL RDA MRS DESL
RDA or WRA
LAL
Address
UA
LA
Valid (opcode)
UA
LA
Bank Add.
BA WL+BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode
DS (input)
QS (output)
Low
DQ (input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS (input)
QS (output)
DQ (input)
D0 D1 D2 D3
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2 clock cycles.
Rev 1.3 2005-03-07 46/65
TC59LM836DKB-30,-33,-40
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRSC = 7 cycles Command RDA LAL DESL RDA MRS
Valid (opcode)
DESL
RDA or WRA
LAL
Address
UA
LA
UA
LA
Bank Add.
BA CL + BL/2
BA0="1" BA1="0"
BA
Unidirectional DS/QS mode
DS (input) QS (output)
Low
DQ (output)
Q0 Q1
Unidirectional DS/Free Running QS mode
DS (input)
QS (output)
DQ (output) Note:
Q0 Q1
Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2 clock cycles. When DQ strobe mode is changed by EMRS, QS output is invalid for lRSC period. DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Rev 1.3 2005-03-07 47/65
TC59LM836DKB-30,-33,-40
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IRSC = 7 cycles Command WRA LAL DESL RDA MRS DESL
RDA or WRA
LAL
Address
UA
LA
Valid (opcode)
UA
LA
Bank Add.
BA WL+BL/2
BA0="1" BA1="0"
BA
Unidirectional DS/QS mode
DS (input)
QS (output)
Low
DQ (input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS (input)
QS (output)
DQ (input)
D0 D1 D2 D3
Note:
When DQ strobe mode is changed by EMRS, QS output is invalid for lRSC period. DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2 clock cycles.
Rev 1.3 2005-03-07 48/65
TC59LM836DKB-30,-33,-40
AUTO-REFRESH TIMING (CL = 4, BL = 4)
Unidirectional DS/QS mode
0 CLK
CLK
1
2
3
4
5
6
7
n−1
n
n+1
n+2
IRC = 5 cycles Command RDA LAL DESL WRA REF
IREFC = 19 cycles DESL RDA or WRA LAL or MRS or REF
Bank,Address
Bank, UA
LA IRAS = 4 cycles IRCD = 1 cycle Low CL = 4
IRCD = 1 cycle QS (output) DQ (output) Low
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Unidirectional DS/Free Running QS mode
CLK
CLK
IRC = 5 cycles Command RDA LAL DESL WRA REF
IREFC = 19 cycles DESL RDA or WRA LAL or MRS or REF
Bank,Address
Bank, UA
LA IRAS = 4 cycles IRCD = 1 cycle
IRCD = 1 cycle QS (output)
CL = 4 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Hi-Z
Note: In case of CL = 4, IREFC must be meet 19 clock cycles. When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is average interval time in 8 Refresh cycles that is sampled randomly. t1 CLK t2 t3 t7 t8
W RA REF
W RA REF
W RA REF
WRA REF
WRA REF
8 Refresh cycle tREFI = Total time of 8 Refresh cycle 8 = t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8 8
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area than Read / Write operation.
Rev 1.3 2005-03-07 49/65
TC59LM836DKB-30,-33,-40
SELF-REFRESH ENTRY TIMING
Unidirectional DS/QS mode
0 CLK
CLK
1
2
3
4
5
m−1
m
m+1
IRCD = 1 cycle WRA REF
IREFC DESL Auto Refresh Self Refresh Entry
Command
tFPDL (min) tFPDL (max)
PD
tQPDH QS (output) DQ (output) Qx Notes: 1. 2. Low Hi-Z is don’t care.
IPDV *2 ICKD Hi-Z
PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode. When PD is brought to "Low" after lPDV, TC59LM836DKB perform Auto Refresh and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM836DKB will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. 3. It is desirable that clock input is continued at least lCKD from REF command even though PD is brought to “Low” for Self-Refresh Entry. 4. In case of Self-Refresh entry after Write Operation, the delay time from the LAL command following WRA to the REF command is Write latency (WL)+2 clock cycles minimum.
SELF-REFRESH EXIT TIMING
Unidirectional DS/QS mode
0 CLK
CLK
*2
1
2
m−1
m
m+1
m+2
n−1
n
n+1
p−1
p
IREFC Command DESL
*3
IREFC WRA
*4
Command (1st)*5 Command (2nd)*5 RDA IRCD = 1 cycle
*6
REF
*4
DESL
LAL
*6
IRCD = 1 cycle
PD
tPDEX ILOCK QS (output) DQ (output) Hi-Z Low Hi-Z Self-Refresh Exit Notes: 1. is don’t care. 2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode. 3. DESL command must be asserted during IREFC after PD is brought to “High”. 4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 5. Any command (except Read command) can be issued after IREFC. 6. Read command (RDA + LAL) can be issued after ILOCK.
Rev 1.3 2005-03-07 50/65
TC59LM836DKB-30,-33,-40
SELF-REFRESH ENTRY TIMING
Unidirectional DS/Free Running QS mode
0 CLK
CLK
1
2
3
4
5
m−1
m
m+1
IRCD = 1 cycle WRA REF
IREFC DESL Auto Refresh Self Refresh Entry
Command
tFPDL (min) tFPDL (max)
PD
tQPDH QS (output) DQ (output) Qx Notes: 1. 2. is don’t care.
IPDV *2 ICKD Hi-Z
Hi-Z
PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode. When PD is brought to "Low" after lPDV, TC59LM836DKB perform Auto Refresh and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM836DKB will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. 3. It is desirable that clock input is continued at least lCKD from REF command even though PD is brought to “Low” for Self-Refresh Entry.
SELF-REFRESH EXIT TIMING
Unidirectional DS/Free Running QS mode
0 CLK
CLK
*2
1
2
m−1
m
m+1
m+2
n−1
n
n+1
p−1
p
IREFC Command DESL
*3
IREFC WRA
*4
Command (1st)*5 Command (2nd)*5 RDA IRCD = 1 cycle
*6
REF
*4
DESL
LAL
*6
IRCD = 1 cycle
PD
tPDEX QS (output) DQ (output) Hi-Z Self-Refresh Exit Notes: 1. is don’t care.
ILOCK
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode. 3. DESL command must be asserted during IREFC after PD is brought to “High”. 4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 5. Any command (except Read command) can be issued after IREFC. 6. Read command (RDA + LAL) can be issued after ILOCK. 7. QS output is invalid until DLL lock from Self-Refresh exit.
Rev 1.3 2005-03-07 51/65
TC59LM836DKB-30,-33,-40
FUNCTIONAL DESCRIPTION Network FCRAM
TM
The FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM is competent to perform fast random core access, low latency and high-speed data transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and CLK . The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL: CS & FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.
BANK ADDRESSES: BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS).
BA0 Bank #0 Bank #1 Bank #2 Bank #3 0 1 0 1
BA1 0 0 1 1
ADDRESS INPUTS: A0~A13
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle.
I/O Organization 36 bits
UPPER ADDRESS A0~A13
LOWER ADDRESS A0~A6
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DATA INPUT/OUTPUT: DQ0~DQ35
The input data of DQ0 to DQ35 are taken in synchronizing with the both edges of DS input signal. The output data of DQ0 to DQ35 are outputted synchronizing with the both edges of QS output signal.
DATA STROBE: LDS, UDS, LQS, UQS
Method of data strobe is chosen by Extended mode register. LDS and LQS are for DQ0 to DQ17. UDS and UQS are for DQ18 to DQ35. (1) Unidirectional DS / QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. During Write, Auto-Refresh and NOP cycle, QS assert always “Low” level. QS is Hi-Z in Self-Refresh mode. (2) Unidirectional DS / Free running QS mode DS is input signal and QS is output signal. Both edge of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
VDD and VSS are power supply pins for memory core and peripheral circuits. VDDQ and VSSQ are power supply pins for the output buffer.
REFERENCE VOLTAGE: VREF
VREF is reference voltage for all input signals.
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COMMAND FUNCTIONS and OPERATIONS
TC59LM836DKB are introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state after lRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS has to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after lRC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = W RA + REF)
TC59LM836DKB are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by lREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = W RA + REF with PD = “L”)
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM836DKB become Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within tFPDL from the REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period. In addition, it is desirable that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as PD held “Low”. During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh exit.
Power Down Mode ( PD = “L”)
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM836DKB become Power Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for lPDA cycle after PD goes high. The Power Down exit function is asynchronous operation.
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Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A13, BA0 and BA1 address inputs. The TC59LM836DKB have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. The four fields are as follows: (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has three function fields. The three fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. (E-3) Data Strobe Select Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation. • Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS
BA1 0 0 1 BA0 0 1 × Mode Register Set Regular MRS Extended MRS Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words.
A2 0 0 0 0 1 A1 0 0 1 1 × A0 0 1 0 1 × BURST LENGTH Reserved 2 words 4 words Reserved Reserved
(R-2) Burst Type field (A3) The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
A3 0 1 BURST TYPE Sequential Interleave
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• Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device
CAS Latency = 4 (Free Running QS mode) CLK CLK
Command QS DQ
RDA
LAL
Data Data Data Data 0 1 2 3
Addressing sequence for Sequential mode
DATA Data 0 Data 1 Data 2 Data 3 ACCESS ADDRESS n n+1 n+2 n+3 BURST LENGTH 2 words (address bits is LA0) not carried from LA0~LA1 4 words (address bits is LA1, LA0) not carried from LA1~LA2
• Addressing sequence of Interleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA Data 0 Data 1 Data 2 Data 3 ACCESS ADDRESS ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0 ּּּA8 A7 A6 A5 A4 A3 A2 A1 ּּּA8 A7 A6 A5 A4 A3 A2 ּּּA8 A7 A6 A5 A4 A3 A2
A1 A1
A0
BURST LENGTH 2 words 4 words
A0
A0
(R-3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum value of CAS Latency depends on the frequency of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1
CAS LATENCY
Reserved Reserved Reserved Reserved 4 5 6 Reserved
(R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation. (R-5) Reserved field in the Regular Mode Register • Reserved bits (A8 to A13) These bits are reserved for future operations. They must be set to “0” for normal operation.
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Extended Mode Register fields
(E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must be set to “0” for normal operation. (E-2) Output Driver Impedance Control field (A1 to A4) This field is used to choose Output Driver Strength. Three types of Driver Strength are supported. QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.
QS A4 0 0 1 1 A3 0 1 0 1 A2 0 0 1 1 DQ A1 0 1 0 1 Normal Output Driver Strong Output Driver Weak Output Driver Reserved
OUTPUT DRIVER IMPEDANCE CONTROL
(E-3) Strobe Select (A6 / A5) Two types of data strobe are supported. This field is used to choose the type of data strobe. (1) Unidirectional DS/QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data at Read operation. (2) Unidirectional DS/Free running QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data and always clocking.
A6 0 0 1 1 A5 0 1 0 1 Reserved Reserved Unidirectional DS/QS mode Unidirectional DS/Free running QS mode STROBE SELECT
(E-4) Reserved field (A7 to A13) These bits are reserved for future operations and must be set to “0” for normal operation.
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BOUNDARY SCAN TEST ACCESS PORT OPERATIONS
The TC59LM836DKB has a serial boundary scan test access port (TAP) which is compatible with IEEE Standard 1149.1 – 1990, but which does not implement all the functions required for 1149.1 – 1990. TCK must be tied to VSS or VDD to disable the TAP when TAP operation is not required.
Test Access Port Signals
SYMBOL TCK Test Clock Input DESCRIPTION All Test Access Port inputs are sampled on the rising edge of TCK. To disable the TAP, TCK must be tied to VSS or VDD. The signal presented at TMS is sampled on the rising edge of TCK. This input is internally pulled up so as to recognize a floating input as a logical High (Test-Logic-Reset). Values presented at TDI are clocked into the selected register on the rising edge of TCK. This input is internally pulled up. This enables detection of when the TDI input to the board is open-circuit. TDO is the serial output for test instructions and data from the test logic. This output is controlled by the falling edge of TCK.
TMS
Test Mode Select Input
TDI
Test Data Input
TDO
Test Data Output
Test Access Port Registers
REGISTER Instruction Register Test Data Register ID Register Bypass Register Boundary Scan Register IDR [ 31 : 0 ] BR BSR [ 62 : 0 ] 32 1 63 The register includes information on revision number, organization and TOSHIBA ID number. The register connects TDI and TDO. The Boundary Scan register is comprised of boundary scan cells at each input and I/O pin. The BSCs are serially connected between TDI and TDO. SYMBOL IR [ 2 : 0 ] LENGTH (bits) 3 DESCRIPTION The Instruction register controls five states (EXTEST, Sample-Z, Sample, Bypass, ID code).
TAP Controller Instruction Set
IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 INSTRUCTION EXTEST ID CODE SAMPLE – Z RESERVED SAMPLE RESERVED RESERVED BYPASS DESCRIPTION Moves the Preloaded data on to the output pins. Samples the inputs connected to the BSCs. Access ID code. Tristates the RAM outputs and samples the inputs connected to the BSCs. This instruction is reserved for future use. Samples the inputs connected to the BSCs. Load the sampled data at I/Os to the parallel output of the BSCs. Does not affect RAM operation. This instruction is reserved for future use. This instruction is reserved for future use. Bypasses TDI and TDO using the Bypass register.
Note: The first bit to be scanned into TDI is taken to be the least significant bit (IR0).
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ID Register
BIT # Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 9 0 8 1 7 0 6 0 5 1 4 1 3 0 2 0 1 0 0 1 Fi
Content
Memory Type
TOSHIBA ID number
xe d
Boundary Scan Order
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 BALL LAYOUT U10 U11 T10 T11 R10 R11 P10 P11 N10 N11 M3 M11 L10 L11 K10 K11 J10 J11 G10 G11 H10 F11 F10 E11 E10 D11 D10 C11 C10 B11 BALL NAME DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 UQS A4 A3 A2 A1 A0 A10 BA1 BA0 A13 FN /CS LQS DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 BIT 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 R3 T2 T3 U2 U3 DQ22 DQ21 DQ20 DQ19 DQ18 D2 E3 E2 F3 F2 G3 H3 H2 J2 J3 K2 K3 L2 L3 M2 N2 N3 P2 P3 R2 DQ12 DQ11 DQ10 DQ9 LDS /CLK CLK /PD A12 A11 A9 A8 A7 A6 A5 UDS DQ26 DQ25 DQ24 DQ23 BALL LAYOUT B10 B3 B2 C3 C2 D3 BALL NAME DQ0 DQ17 DQ16 DQ15 DQ14 DQ13
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TAP CONTROLLER STATE DIAGRAM
TMS = 1
Test – Logic - Reset TMS = 0
TMS = 0
Run – Test / Idle
TMS = 1
Select – DR - Scan TMS = 0 Capture - DR TMS = 0
TMS = 1
Select – IR - Scan TMS = 0
TMS = 1
TMS = 1
Capture - IR TMS = 1 TMS = 0 Shift - IR TMS = 1 Exit1 - IR TMS = 0 Pause - IR TMS = 1 TMS = 0 Exit2 - IR TMS = 1 Update - IR TMS = 0 TMS = 0 TMS = 1 TMS = 0
TMS = 0
Shift - DR TMS = 1
TMS = 1
Exit1 - DR TMS = 0
TMS = 0
Pause - DR TMS = 1 Exit2 - DR TMS = 1 Update - DR
TMS = 0
TMS = 1 TMS = 0 Notes: 1. 2.
TMS = 1
To enter the Test-Logic-Reset state in order to initialize the device, keep TMS High for at least five rising edges of the TCK. The TDO output buffer is active only during shift operations (the Shift-DR and Shift-IR states) and is inactive (High-Z) during other states.
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TAP DC OPERATING CHARACTERISTICS
SYMBOL ILO PARAMETER Output Leakage Current (TDO pin) Input Leakage Current (TCK, TMS, TDI pins) Input High Voltage (TCK, TMS, TDI pins) Input Low Voltage (TCK, TMS, TDI pins) Output High Voltage (TDO pin) Output Low Voltage (TDO pin) TEST CONDITION Output Deselected VOUT=0 to VDD VIN = 1.7V to VDD VIN = 0 to 0.7V IOH = −2 mA IOL = 2 mA MIN −10 −20 −100 VREF+0.4 −0.1 1.5 TYP MAX 10 10 10 VDD+0.2 VREF−0.4 VDD 0.45 UNIT µA µA µA V
II
VIH VIL VOH VOL
V V V
AC CHARACTERISTICS ( VDD = 2.5V ± 0.125V, VDDQ = 1.4V ~ 1.9V, TCASE = 0 ~ 85°C )
TC59LM836DKB SYMBOL PARAMETER MIN tTHTH tTHTL tTLTH tMVTH tTHMX tCS tCH tDVTH tTHDX tTLQV tTLQX tTLQLZ tTLQHZ TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup Time to TCK TMS Hold Time to TCK Capture Setup time to TCK Capture Hold time to TCK TDI Setup Time to TCK TDI Hold Time to TCK Output Valid Time from TCK Low Output Hold Time from TCK Low Output Low-Z Time from TCK Low Output High-Z Time from TCK Low 50 20 20 10 10 10 10 10 10 0 5 MAX 20 5 ns UNIT
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TAP AC TEST CONDITIONS
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time Input Timing Measurement Reference Level Output Timing Measurement Reference Level CONDITION TDO 1.8V / 0.0V 2ns 0.9V 0.9V Output Load RL = 50 Ω VL = 0.9V Z = 50 Ω
TAP TIMING DIAGRAMS
tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTHTL tTLTH
tCS tCH Capture Data tTLQLZ TDO tTLQV tTLQX tTLQHZ
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PACKAGE DIMENSIONS
P-TFBGA144-1119-0.80BZ
18.5
0.2 S B
0.2 S A 4 0.15
11.0
0.2 S
S 1.2MAX 0.4 0.05 0.15MIN 0.1 S
0.5 0.05 A
A B C D E F G H J K L M N P R T U INDEX 1 2 3 4 5 6 7 8 9 10 11 12
0.08 0.75
V
S AB
0.8 B
Weight: 0.30g (typ.)
2.0 2.0
1.1
0.5
1.0
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REVISION HISTORY
− Rev.1.0 (Feb. 26 ’2004) − Rev.1.1 (May. 25 ‘2004) • IDD6 spec changed from 10mA to 15mA (page 1, 7) • VSWING in AC Test conditions changed from 0.7 V to 0.8 V (page 11) • Corrected typo (page 54) − Rev.1.2 (Aug. 27 ‘2004) • Some notes in the page 8 moved to page 7 (page 7, 8). • Note 2 changed as below (page 7). Before: These parameters depend on the output loading. The specified values are obtained with the output open After: These parameters define the current between VDD and VSS. • • • • Corrected TYPO (page 9, 14~18, 61, 62). tCK,MAX for “-30” changed from 7.5 ns to 5.0 ns (page 9) Package drawing minor change (page 63). Package weight (0.30g) added (page 63)
− Rev.1.3 (Mar.7 ‘2005) • Corrected figure of lPDA based AC timing spec table (page 12, 43, 44, 50, 51).
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RESTRICTIONS ON PRODUCT USE
• The information contained herein is subject to change without notice.
030619EBA
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations.
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