TC74ACT161P

TC74ACT161,163P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT161P,TC74ACT161F,TC74ACT161FN TC74ACT163P,TC74ACT163F,TC74ACT163FN Synchronous Presettable 4-Bit Binary Counter TC74ACT161P/F/FN Asynchronous Clear TC74ACT163P/F/FN Synchronous Clear The TC74ACT161 and T163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs fabricated with silicon gate and double-layer metal wiring C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These devices may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. Presetting of these IC’s is synchronous to the rising edge of CK. The clear function of the TC74ACT163 is synchronous to CK, while the TC74ACT161 are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Note: xxxFN (JEDEC SOP) is not available in Japan. TC74ACT161P, TC74ACT163P TC74ACT161F, TC74ACT163F TC74ACT161FN, TC74ACT163FN Features • • • • High speed: fmax = 110 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 8 μA (max) at Ta = 25°C Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω • • transmission lines. ∼ Balanced propagation delays: tpLH − tpHL Pin and function compatible with 74F161/163 Weight DIP16-P-300-2.54A SOP16-P-300-1.27A SOL16-P-150-1.27 : 1.00 g (typ.) : 0.18 g (typ.) : 0.13 g (typ.) 1 2007-10-01 TC74ACT161,163P/F/FN Pin Assignment IEC Logic Symbol TC74ACT161 TC74ACT163 Truth Table Inputs CLR (161) CLR (163) LOAD Outputs ENT X X L X H X CK (161) X CK (163) QA L A QB L B QC L C QD L D Function Reset to “0” Preset Data No Count No Count Count No Count ENP X X X L H X L H H H H H L H H H H X X L H H H X No Change No Change Count Up No Change X: Don’t care A, B, C, D: Logic level of data inputs Carry: Carry = ENT･QA･QB･QC･QD 2 2007-10-01 TC74ACT161,163P/F/FN Timing Chart 3 2007-10-01 TC74ACT161,163P/F/FN System Diagram (Note) (Note) (Note) (Note) (Note) Note: Truth table of internal F/F TC74ACT161 D X L H X CK X R H L L L Q L L H Q TC74ACT163 D X L X X CK R H L L L Q L L H Q H H L H H L No Change No Change X: Don’t care 4 2007-10-01 TC74ACT161,163P/F/FN Absolute Maximum Ratings (Note 1) Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating −0.5 to 7.0 −0.5 to VCC + 0.5 −0.5 to VCC + 0.5 ±20 ±50 ±50 ±125 500 (DIP) (Note 2)/180 (SOP) −65 to 150 Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be applied up to300 mW. Operating Ranges (Note) Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Symbol VCC VIN VOUT Topr dt/dV Rating 4.5 to 5.5 0 to VCC 0 to VCC −40 to 85 0 to 10 Unit V V V °C ns/V Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 5 2007-10-01 TC74ACT161,163P/F/FN Electrical Characteristics DC Characteristics Test Condition Characteristics Symbol VCC (V) ⎯ ⎯ IOH = −50 μA VIN = VIH or IOH = −24 mA VIL IOH = −75 mA VIN = VIH or IOL = 24 mA VIL IOL = 75 mA VIN = VCC or GND VIN = VCC or GND Per input: VIN = 3.4 V Other input: VCC or GND IOL = 50 μA 4.5 to 5.5 4.5 to 5.5 4.5 4.5 (Note) 5.5 4.5 4.5 (Note) 5.5 5.5 5.5 5.5 Min 2.0 ⎯ 4.4 3.94 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Ta = 25°C Typ. ⎯ ⎯ 4.5 ⎯ ⎯ 0.0 ⎯ ⎯ ⎯ ⎯ ⎯ Max ⎯ 0.8 ⎯ ⎯ ⎯ 0.1 0.36 ⎯ ±0.1 8.0 1.35 Ta = −40 to 85°C Min 2.0 ⎯ 4.4 3.80 3.85 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max ⎯ 0.8 ⎯ ⎯ ⎯ 0.1 0.44 1.65 ±1.0 80.0 1.5 μA μA mA V V V V Unit High-level input voltage Low-level input voltage High-level output voltage VIH VIL VOH Low-level output voltage Input leakage current Quiescent supply current VOL IIN ICC IC Note: This spec indicates the capability of driving 50 Ω transmission lines. One output should be tested at a time for a 10 ms maximum duration. Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Minimum pulse width (CK) Minimum pulse width ( CLR ) tW (L) tW (H) Figure 1 5.0 ± 0.5 Ta = 25°C Limit 5.0 Ta = −40 to 85°C Limit 5.0 ns Unit (Note1) tW (L) Figure 4 5.0 ± 0.5 5.0 5.0 ns Minimum pulse width ( LOAD , ENP, ENT) Minimum set-up time (A, B, C, D) Minimum set-up time ( CLR ) Minimum hold time ( LOAD , ENP, ENT) Minimum hold time (A, B, C, D) Minimum hold time ( CLR ) Minimum removal time ( CLR ) (Note 1) (Note 2) (Note 2) ts Figure 2, Figure 3 5.0 ± 0.5 6.0 6.0 ns ts Figure 2 5.0 ± 0.5 4.0 4.0 ns ts Figure 5 5.0 ± 0.5 3.0 3.0 ns th Figure 2, Figure 3 5.0 ± 0.5 1.0 1.0 ns th Figure 2 5.0 ± 0.5 2.0 2.0 ns th Figure 5 5.0 ± 0.5 2.0 2.0 ns trem Figure 4 5.0 ± 0.5 1.0 1.0 ns Note 1: For TC74ACT161 only Note 2: For TC74ACT163 only 6 2007-10-01 TC74ACT161,163P/F/FN AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns) Characteristics Propagation delay time (CK-Q) Propagation delay time (CK-CARRY, count mode) Propagation delay time (CK-CARRY, preset mode) Propagation delay time (ENT-CARRY) Propagation delay time (Note 2) ( CLR -Q) Propagation delay time (Note 2) ( CLR -CARRY) Maximum clock frequency Input capacitance Power dissipation capacitance fmax CIN CPD (Note 1) ⎯ ⎯ ⎯ Symbol Test Condition VCC (V) Min ⎯ Ta = 25°C Typ. 7.2 Max 10.5 Ta = −40 to 85°C Min 1.0 Max 12.0 Unit tpLH tpHL tpLH tpHL Figure 1 5.0 ± 0.5 ns Figure 1 5.0 ± 0.5 ⎯ 8.5 13.0 1.0 15.0 ns tpLH tpHL tpLH tpHL Figure 2 5.0 ± 0.5 ⎯ 9.7 15.0 1.0 17.0 ns Figure 6 5.0 ± 0.5 ⎯ 6.6 10.0 1.0 11.5 ns tpHL Figure 4 5.0 ± 0.5 ⎯ 6.3 10.0 1.0 11.5 ns tpHL Figure 4 5.0 ± 0.5 ⎯ 7.7 12.3 1.0 14.0 ns 5.0 ± 0.5 70 ⎯ ⎯ 100 5 32 ⎯ 60 ⎯ ⎯ ⎯ MHz pF pF 10 ⎯ 10 ⎯ Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ΔICC which is obtained from the following formula: C C C C C ΔICC = fCK ⋅ VCC ( QA + QB + QC + QD + CO ) 2 4 8 16 16 CQA~CQD and CCO are the capacitances at QA~QD and CARRY OUT, respectively. fCK is the input frequency of the CK. Note 2: for TC74ACT161 only 7 2007-10-01 TC74ACT161,163P/F/FN Switching Characteristics Test Waveform Count Mode Clear Mode (TC74ACT161) Figure 1 Figure 4 Preset Mode Clear Mode (TC74ACT163) Figure 2 Figure 5 Count Enable Mode Cascade Mode (fix maximum count) Figure 3 Figure 6 8 2007-10-01 TC74ACT161,163P/F/FN Typical Application Parallel Carry N-Bit Counter 9 2007-10-01 TC74ACT161,163P/F/FN Package Dimensions Weight: 1.00 g (typ.) 10 2007-10-01 TC74ACT161,163P/F/FN Package Dimensions Weight: 0.18 g (typ.) 11 2007-10-01 TC74ACT161,163P/F/FN Package Dimensions (Note) Note: This package is not available in Japan. Weight: 0.13 g (typ.) 12 2007-10-01 TC74ACT161,163P/F/FN RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 20070701-EN GENERAL • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 13 2007-10-01