TC74VHC123AFK(EL,K

TC74VHC123AF/AFK,TC74VHC221AF/AFK CMOS Digital Integrated Circuits Silicon Monolithic TC74VHC123AF,TC74VHC123AFK, TC74VHC221AF,TC74VHC221AFK 1. Functional Description • Dual Monostable Multivibrator TC74VHC123AF/AFK: Retriggerable TC74VHC221AF/AFK: Non-Retriggerable 2. General The TC74VHC123A/221A are high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate C2MOS technology. There are two trigger inputs, A input (negative edge), and B input (positive edge). These inputs are valid for a slow rise/fall time signal (tr = tf = 1 s) as they are schmitt trigger inputs. This device may also be triggered by using CLR input (positive edge). After triggering, the output stays in a MONOSTABLE state for a time period determined by the external resistor and capacitor (RX, CX). A low level at the CLR input breaks this state. Limits for CX and RX are: External capacitor, CX: No limit External resistor, RX: VCC = 2.0 V more than 5 kΩ VCC ≥ 3.0 V more than 1 kΩ An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 3. Features (Note) (1) High speed: Propagation delay time = 8.1 ns (typ.) at VCC = 5.0 V (2) Low power dissipation: Standby state: 4.0 µA (max) at Ta = 25  Active state: 750 µA (max) at Ta = 25  (3) High noise immunity: VNIH = VNIL = 28 % VCC (min) (4) Power-down protection is provided on all inputs. (5) Balanced propagation delays: tPLH ≈ tPHL (6) Wide operating voltage range: VCC(opr) = 2.0 to 5.5 V (7) Pin and function compatible with TC74HC123A,TC74HC221A type. Note: In the case of using only one circuit, CLR should be tied to GND, RX/CXCXQQ should be tied to OPEN, the other inputs should be tied to VCC or GND. Start of commercial production ©2016-2017 Toshiba Electronic Devices & Storage Corporation 1 2013-05 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 4. Packaging TC74VHC123AF,TC74VHC221AF TC74VHC123AFK, TC74VHC221AFK SOP16 US16 5. Pin Assignment 6. IEC Logic Symbol TC74VHC123AF,TC74VHC123AFK ©2016-2017 Toshiba Electronic Devices & Storage Corporation TC74VHC221AF,TC74VHC221AFK 2 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 7. Truth Table X: Don't care 8. Block Diagram (1) CX, RX, DX are external Capacitor, resistor, and diode, respectively. (2) External clamping diode, DX; The external capacitor is charged to VCC level in the wait state, i.e. when no trigger is applied. If the supply voltage is turned off, CX is discharges mainly through the internal (parasitic) diode. If CX is sufficiently large and VCC drops rapidly, there will be some possibility of damaging the IC through in rush current or latch-up. If the capacitance of the supply voltage filter is large enough and VCC drops slowly, the in rush current is automatically limited and damage to the IC is avoided. The maximum value of forward current through the parasitic diode is ±20 mA. In the case of a large CX, the limit of fall time of the supply voltage is determined as follows: tf ≥ (VCC - 0.7) CX/20 mA (tf is the time between the supply voltage turn off and the supply voltage reaching 0.4 VCC.) In the even a system does not satisfy the above condition, an external clamping diode (DX) is needed to protect the IC from rush current. ©2016-2017 Toshiba Electronic Devices & Storage Corporation 3 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 9. System Diagram Fig. 9.1 TC74VHC123AF, TC74VHC123AFK Fig. 9.2 TC74VHC221AF, TC74VHC221AFK ©2016-2017 Toshiba Electronic Devices & Storage Corporation 4 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 10. Timing Chart Fig. 10.1 TC74VHC123AF, TC74VHC123AFK Fig. 10.2 TC74VHC221AF, TC74VHC221AFK ©2016-2017 Toshiba Electronic Devices & Storage Corporation 5 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 11. Functional Description (1) Standby state The external capacitor (CX) is fully charged to VCC in the stand-by state. That means, before triggering, the QP and QN transistors which are connected to the RX/CX node are in the off state. Two comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off. The total supply current is only leakage current. (2) Trigger operation Trigger operation is effective in any of the following three cases. First, the condition where the A input is low, and the B input has a rising signal; second, where the B input is high, and the A input has a falling signal; and third, where the A input is low and the B input is high, and the CLR input has a rising signal. After a trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The external capacitor discharges through QN. The voltage level at the RX/CX node drops. If the RX/CX voltage level falls to the internal reference voltage VrefL, the output of C1 becomes low. The flip-flop is then reset and QN turns off. At that moment C1 stops but C2 continues operating. After QN turns off, the voltage at the RX/CX node starts rising at a rate determined by the time constant of external capacitor CX and resistor RX. Upon triggering, output Q becomes high, following some delay time of the internal F/F and gates. It stays high even if the voltage of RX/CX changes from falling to rising. When RX/CX reaches the internal reference voltage VrefH, the output of C2 becomes low, the output Q goes low and C2 stops its operation. That means, after triggering, when the voltage level of the RX/CX node reaches VrefH, the IC returns to its MONOSTABLE state. With large values of CX and RX, and ignoring the discharge time of the capacitor and internal delays of the IC, the width of the output pulse, twOUT, is as follows: twOUT = 1.0 × CX × RX (3) Retrigger operation When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is effective only if the IC is charging CX. The voltage level of the RX/CX node then falls to VrefL level again. Therefore the Q output stays high if the next trigger comes in before the time period set by CX and RX. If the new trigger is very close to previous trigger, such as an occurrence during the discharge cycle, it will have no effect. The minimum time for a trigger to be effective 2 nd trigger, trr (min), depends on VCC and CX.(TC74VHC123A) (4) Reset operation In normal operation, the CLR input is held high. If CLR is low, a trigger has no effect because the Q output is held low and the trigger control F/F is reset. Also, QP turns on and CX is charged rapidly to VCC. This means if CLR is set low, the IC goes into a wait state. ©2016-2017 Toshiba Electronic Devices & Storage Corporation 6 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 12. Absolute Maximum Ratings (Note) Characteristics Symbol Rating Unit Supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to 7.0 V VOUT -0.5 to VCC + 0.5 V IIK -20 mA Output diode current IOK ±20 mA Output current IOUT ±25 mA VCC/ground current ICC ±50 mA Power dissipation PD 180 mW Storage temperature Tstg -65 to 150  Output voltage Input diode current Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 13. Operating Ranges (Note) Characteristics Supply voltage Symbol Test Condition Rating Unit VCC  2.0 to 5.5 V VIN  0 to 5.5 V VOUT  0 to VCC V Input voltage Output voltage Note Operating temperature Topr  -40 to 85  Input rise and fall times dt/dv VCC = 3.3 ± 0.3 V 0 to 100 ns/V VCC = 5.0 ± 0.5 V 0 to 20 External capacitor CX (Note 1)  No limitation F External resistor RX (Note 1) VCC = 2.0 V ≥5k Ω VCC ≥ 3.0 V ≥1k Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note 1: The maximum allowable values of CX and RX are a function of leakage of capacitor CX, the leakage of TC74VHC123A/221A, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MΩ. ©2016-2017 Toshiba Electronic Devices & Storage Corporation 7 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 14. Electrical Characteristics 14.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Test Condition High-level input voltage VIH  Low-level input voltage VIL  High-level output voltage VOH Low-level output voltage VOL VIN = VIH or VIL Min Typ. Max Unit 2.0 1.50   V 3.0 to 5.5 VCC × 0.7   2.0   0.50 3.0 to 5.5   VCC × 0.3 2.0 1.9 2.0  3.0 2.9 3.0  4.5 4.4 4.5  IOH = -4 mA 3.0 2.58   IOH = -8 mA 4.5 3.94   IOL = 50 µA 2.0  0.0 0.1 3.0  0.0 0.1 4.5  0.0 0.1 3.0   0.36 IOH = -50 µA VIN = VIH or VIL VCC (V) IOL = 4 mA IOL = 8 mA V V V 4.5   0.36 Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5   ±0.1 µA RX/CX terminal OFF-state current IIN VIN = VCC or GND 5.5   ±0.25 µA Quiescent supply current ICC VIN = VCC or GND 5.5   4.0 µA ICC(opr) VIN = VCC or GND RX/CX = 0.5 VCC 3.0  160 250 µA 4.5  380 500 5.5  560 750 Active-state supply current (per circuit) 14.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics Symbol Test Condition High-level input voltage VIH  Low-level input voltage VIL  High-level output voltage VOH Low-level output voltage VOL VIN = VIH or VIL VIN = VIH or VIL VCC (V) Min Max Unit 2.0 1.50  V 3.0 to 5.5 VCC × 0.7  2.0  0.50 3.0 to 5.5  VCC × 0.3 2.0 1.9  3.0 2.9  4.5 4.4  IOH = -4 mA 3.0 2.48  IOH = -8 mA 4.5 3.80  IOL = 50 µA 2.0  0.1 3.0  0.1 4.5  0.1 3.0  0.44 IOH = -50 µA IOL = 4 mA IOL = 8 mA V V V 4.5  0.44 IIN VIN = 5.5 V or GND 0 to 5.5  ±1.0 µA RX/CX terminal OFF-state current IIN VIN = VCC or GND 5.5  ±2.5 µA Quiescent supply current ICC VIN = VCC or GND 5.5  40.0 µA ICC(opr) VIN = VCC or GND RX/CX = 0.5 VCC 3.0  280 µA 4.5  650 5.5  975 Input leakage current Active-state supply current (per circuit) ©2016-2017 Toshiba Electronic Devices & Storage Corporation 8 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 14.3. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Part Number Minimum pulse width Minimum pulse width (CLR) Minimum retrigger time Symbol Test Condition VCC (V) Typ. Limit Unit tw(L),tw(H)  3.3 ± 0.3  5.0 ns 5.0 ± 0.5  5.0 3.3 ± 0.3  5.0 5.0 ± 0.5  5.0 3.3 ± 0.3 60  5.0 ± 0.5 39  3.3 ± 0.3 1.5  5.0 ± 0.5 1.2  tw(L) TC74VHC123AF, TC74VHC123AFK  trr RX = 1 kΩ, CX = 100 pF RX = 1 kΩ, CX = 0.01 µF ns ns µs 14.4. Timing Requirements (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Minimum pulse width Minimum pulse width (CLR) Symbol Test Condition VCC (V) Limit Unit tw(L),tw(H)  3.3 ± 0.3 5.0 ns 5.0 ± 0.5 5.0 3.3 ± 0.3 5.0 5.0 ± 0.5 5.0 tw(L)  ns 14.5. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (A, B-Q, Q) Symbol Note Test Condition VCC (V) CL (pF) Min Typ. Max Unit  3.3 ± 0.3 15  13.4 20.6 ns 50  15.9 24.1 15  8.1 12.0 50  9.6 14.0 15  14.5 22.4 50  17.0 25.9 15  8.7 12.9 50  10.2 14.9 15  10.3 15.8 50  12.8 19.3 15  6.3 9.4 50  7.8 11.4 50  160 240  133 200 50 90 100 110 90 100 110 50 0.9 1.0 1.1 tPLH,tPHL 5.0 ± 0.5 Propagation delay time (CLR trigger-Q, Q) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR-Q, Q) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Output pulse width twOUT CX = 28 pF, RX = 2 kΩ 3.3 ± 0.3 CX = 0.01 µF, RX = 10 kΩ 3.3 ± 0.3 CX = 0.1 µF, RX = 10 kΩ 3.3 ± 0.3 5.0 ± 0.5 5.0 ± 0.5 ns ns µs ms 0.9 1.0 1.1 ∆twOUT   ±1  % Input capacitance CIN   4 10 pF Power dissipation capacitance CPD   73  pF Output pulse width error between circuits (in same package) (Note 1) 5.0 ± 0.5 ns Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation. ICC(opr) = CPD × VCC × fIN + ICC' × Duty/100 + ICC/2 (per circuit), (ICC': Active supply current), (Duty: %) ©2016-2017 Toshiba Electronic Devices & Storage Corporation 9 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 14.6. AC Characteristics (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (A, B-Q, Q) Symbol Test Condition VCC (V) CL (pF) Min Max Unit tPLH,tPHL  3.3 ± 0.3 15 1.0 24.0 ns 50 1.0 27.5 15 1.0 14.0 50 1.0 16.0 15 1.0 26.0 50 1.0 29.5 15 1.0 15.0 50 1.0 17.0 15 1.0 18.5 50 1.0 22.0 15 1.0 11.0 50 1.0 13.0 50  300  240 90 110 90 110 0.9 1.1 0.9 1.1  10 5.0 ± 0.5 Propagation delay time (CLR trigger-Q, Q) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR-Q, Q) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Output pulse width Input capacitance ©2016-2017 Toshiba Electronic Devices & Storage Corporation twOUT CX = 28 pF, RX = 2 kΩ 3.3 ± 0.3 CX = 0.01 µF, RX = 10 kΩ 3.3 ± 0.3 CX = 0.1 µF, RX = 10 kΩ 3.3 ± 0.3 CIN  10 5.0 ± 0.5 50 5.0 ± 0.5 5.0 ± 0.5 50 ns ns ns µs ms pF 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 15. Characteristics Curves (Note) Fig. 15.1 twOUT - CX (typ.) Fig. 15.2 trr - VCC (typ.) (TC74VHC123A) Fig. 15.3 Output Pulse Width Constant K - Supply Voltage (typ.) Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. ©2016-2017 Toshiba Electronic Devices & Storage Corporation 11 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK 16. Internal Equivalent Circuit ©2016-2017 Toshiba Electronic Devices & Storage Corporation 12 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK Package Dimensions Unit: mm TC74VHC123AF,TC74VHC221AF Weight: 0.18 g (typ.) Package Name(s) Nickname: SOP16 ©2016-2017 Toshiba Electronic Devices & Storage Corporation 13 2017-11-30 Rev.4.0 TC74VHC123AF/AFK,TC74VHC221AF/AFK Package Dimensions Unit: mm TC74VHC123AFK,TC74VHC221AFK Weight: 0.02 g (typ.) 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