TC74VHC161FK(EL,K)

TC74VHC161,163F/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC161F, TC74VHC161FK TC74VHC163F, TC74VHC163FK Synchronous Presettable 4-Bit Counter TC74VHC161F/FK Binary, Asynchronous Clear TC74VHC163F/FK Binary, Synchronous Clear The TC74VHC 161 and 163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. Presetting of each IC’s is synchronous to the rising edge of CK. The clear function of the TC74VHC163 is synchronous to CK, while the TC74VHC161 are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. TC74VHC161F, TC74VHC163F TC74VHC161FK, TC74VHC163FK Weight SOP16-P-300-1.27A VSSOP16-P-0030-0.50 : 0.18 g (typ.) : 0.02 g (typ.) Features  High speed: fmax = 185 MHz (typ.) at VCC = 5 V  Low power dissipation: ICC = 4 μA (max) at Ta = 25°C  High noise immunity: VNIH = VNIL = 28% VCC (min)  Power down protection is provided on all inputs.  Balanced propagation delays: tpLH ∼ − tpHL  Wide operating voltage range: VCC (opr) = 2 to 5.5 V  Low noise: VOLP = 0.8 V (max)  Pin and function compatible with 74ALS161/163 Start of commercial production 1991-11 © 2019 Toshiba Electronic Devices & Storage Corporation 1 2019-01-31 TC74VHC161,163F/FK Pin Assignment 1 16 VCC CK 2 15 CARRY OUTPUT A 3 14 QA B 4 13 QB C 5 12 QC D 6 11 QD ENP 7 10 ENT GND 8 9 (top view) IEC Logic Symbol (1) (9) ENT ENP CK A B C D (10) (7) (2) (3) (4) (5) (6) TC74VHC161 CTRDIV 16 CT = 0 M1 M2 3CT = 15 G3 G4 (1) (9) (15) CARRY OUTPUT ENT ENP CK C5/2, 3, 4+ 1, 5D (14) (13) (12) (11) [1] [2] [4] [8] TC74VHC163 CTRDIV 16 5CT = 0 M1 M2 3CT = 15 G3 G4 QA QB QC QD A B C D (10) (7) (2) (15) CARRY OUTPUT C5/2, 3, 4+ (3) (4) (5) (6) 1, 5D (14) (13) (12) (11) [1] [2] [4] [8] QA QB QC QD Truth Table (Note) TC74VHC161 TC74VHC163 Inputs Inputs Outputs CLR LD ENP ENT CK CLR LD ENP ENT L X X X X L X X H L X X H L H H X L H H H H L X H H L X No Change No Count H H H H H H H H Count Up Count H X X X X X X X No Change No Count Note: CK Function QA QB QC QD X L L L L Reset to “0” X X A B C D Preset Data X L No Change No Count X: Don’t care A, B, C, D: Logic level of data inputs Carry: CARRY = ENT･QA･QB･QC･QD © 2019 Toshiba Electronic Devices & Storage Corporation 2 2019-01-31 TC74VHC161,163F/FK Timing Chart A Data Inputs DON’T CARE UNTIL GOES LOW B C D CK ENP ENT QA QB Outputs QC QD CARRY 12 13 ASYNC SYNC PRESET CLEAR CLEAR (161) (163) © 2019 Toshiba Electronic Devices & Storage Corporation 14 15 0 COUNT 3 1 2 INHIBIT 2019-01-31 TC74VHC161,163F/FK System Diagram 1 7 ENP E 10 ENT 9 L 15 CARRY OUT 3 A (Note) L D R Q CK E 14 QA 4 B (Note) L D R Q E CK 13 QB 5 C (Note) L D R Q E CK 12 QC 6 D (Note) L D R Q E CK Note: CK 2 11 QD Truth table of internal F/F TC74VHC161 TC74VHC163 D CK R Q Q D X X H L H L L L H L H X L R Q Q X H L H H L L L H L H L H L X X No Change CK No Change X: Don’t care © 2019 Toshiba Electronic Devices & Storage Corporation 4 2019-01-31 TC74VHC161,163F/FK Absolute Maximum Ratings (Note) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to 7.0 V DC output voltage VOUT −0.5 to VCC + 0.5 V Input diode current IIK −20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±50 mA Power dissipation PD 180 mW Storage temperature Tstg −65 to 150 °C Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Operating Range (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2.0 to 5.5 V Input voltage VIN 0 to 5.5 V Output voltage VOUT 0 to VCC V Operating temperature Topr −40 to 85 °C Input rise and fall time dt/dv 0 to 100 (VCC = 3.3 ± 0.3 V) 0 to 20 (VCC = 5 ± 0.5 V) ns/V Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. © 2019 Toshiba Electronic Devices & Storage Corporation 5 2019-01-31 TC74VHC161,163F/FK Electrical Characteristics DC Characteristics Characteristics Test Condition Symbol High-level input voltage VIH ― Low-level input voltage VIL ― High-level output voltage Low-level output voltage VOH VOL VIN = VIH or VIL VIN = VIH or VIL Ta = −40 to 85°C Ta = 25°C VCC (V) Min Typ. Max Min Max 2.0 1.50 VCC × 0.7 ― ― ― ― ― 1.50 VCC × 0.7 0.50 VCC × 0.3 ― 0.50 VCC × 0.3 3.0 to 5.5 ― 2.0 ― ― 3.0 to 5.5 ― ― 2.0 3.0 4.5 1.9 2.9 4.4 2.0 3.0 4.5 ― ― ― 1.9 2.9 4.4 ― ― ― IOH = −4 mA IOH = −8 mA 3.0 4.5 2.58 3.94 ― ― ― ― 2.48 3.80 ― ― IOL = 50 μA 2.0 3.0 4.5 ― ― ― 0.0 0.0 0.0 0.1 0.1 0.1 ― ― ― 0.1 0.1 0.1 IOL = 4 mA IOL = 8 mA 3.0 4.5 ― ― ― ― 0.36 0.36 ― ― 0.44 0.44 IOH = −50 μA ― Unit V V V V Input leakage current IIN VIN = 5.5 or GND 0 to 5.5 ― ― ±0.1 ― ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 5.5 ― ― 4.0 ― 40.0 μA © 2019 Toshiba Electronic Devices & Storage Corporation 6 2019-01-31 TC74VHC161,163F/FK Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Minimum pulse width (CK) Ta = 25°C Ta = −40 to 85°C VCC (V) Limit Limit Test Condition Unit tw (L) tw (H) Figure 1 3.3 ± 0.3 5.0 ± 0.5 5.0 5.0 5.0 5.0 ns tw (L) Figure 4 3.3 ± 0.3 5.0 ± 0.5 5.0 5.0 5.0 5.0 ns Minimum set-up time (A, B, C, D) ts Figure 2 3.3 ± 0.3 5.0 ± 0.5 5.5 4.5 6.5 4.5 ns Minimum set-up time ( LOAD ) ts Figure 2 3.3 ± 0.3 5.0 ± 0.5 8.0 5.0 9.5 6.0 ns Minimum set-up time (ENT, ENP) ts Figure 3 3.3 ± 0.3 5.0 ± 0.5 7.5 5.0 9.0 6.0 ns ts Figure 5 3.3 ± 0.3 5.0 ± 0.5 4.0 3.5 4.0 3.5 ns th Figure 2, Figure 3 3.3 ± 0.3 5.0 ± 0.5 1.0 1.0 1.0 1.0 ns th Figure 5 3.3 ± 0.3 5.0 ± 0.5 1.0 1.5 1.0 1.5 ns trem Figure 4 3.3 ± 0.3 5.0 ± 0.5 2.5 1.5 2.5 1.5 ns Minimum pulse width ( CLR ) Minimum set-up time ( CLR ) (Note1) (Note 2) Minimum hold time Minimum hold time ( CLR ) (Note 2) Minimum removal time ( CLR ) (Note 1) Note 1: For TC74VHC161 only Note 2: For TC74VHC163 only © 2019 Toshiba Electronic Devices & Storage Corporation 7 2019-01-31 TC74VHC161,163F/FK AC Characteristics (input: tr = tf = 3 ns) Characteristics Propagation delay time (CK-Q) tpLH tpHL Propagation delay time (CK-CARRY, countmode) Propagation delay time (CK-CARRY, presetmode) Propagation delay time (ENT-CARRY) tpLH tpHL tpLH tpHL tpLH tpHL Propagation delay time (Note 2) ( CLR -Q) Propagation delay time ( CLR -CARRY) (Note 2) Test Condition Symbol VCC (V) Min Typ. Max Min Max 15 ― 8.3 12.8 1.0 15.0 50 ― 10.8 16.3 1.0 18.5 15 ― 4.9 8.1 1.0 9.5 50 ― 6.4 10.1 1.0 11.5 15 ― 8.7 13.6 1.0 16.0 50 ― 11.2 17.1 1.0 19.5 15 ― 4.9 8.1 1.0 9.5 50 ― 6.4 10.1 1.0 11.5 15 ― 11.0 17.2 1.0 20.0 50 ― 13.5 20.7 1.0 23.5 15 ― 6.2 10.3 1.0 12.0 50 ― 7.7 12.3 1.0 14.0 15 ― 7.5 12.3 1.0 14.5 50 ― 10.5 15.8 1.0 18.0 15 ― 4.9 8.1 1.0 9.5 50 ― 6.4 10.1 1.0 11.5 15 ― 8.9 13.6 1.0 16.0 50 ― 11.2 17.1 1.0 19.5 15 ― 5.5 9.0 1.0 10.5 50 ― 7.0 11.0 1.0 12.5 15 ― 8.4 13.2 1.0 15.5 50 ― 10.9 16.7 1.0 19.0 15 ― 5.0 8.6 1.0 10.0 50 ― 6.5 10.6 1.0 12.0 15 80 130 ― 70 ― 50 55 85 ― 50 ― 15 135 185 ― 115 ― 50 95 125 ― 85 ― ― 4 10 ― 10 pF ― 23 ― ― ― pF 3.3 ± 0.3 Figure 1, Figure 2 5.0 ± 0.5 3.3 ± 0.3 Figure 1 5.0 ± 0.5 3.3 ± 0.3 Figure 2 5.0 ± 0.5 3.3 ± 0.3 Figure 6 5.0 ± 0.5 Figure 4 5.0 ± 0.5 3.3 ± 0.3 tpHL Figure 4 5.0 ± 0.5 3.3 ± 0.3 Maximum clock frequency fmax ― 5.0 ± 0.5 Input capacitance CIN Power dissipation capacitance CPD Unit CL (pF) 3.3 ± 0.3 tpHL Ta = −40 to 85°C Ta = 25°C ― (Note 1) ns ns ns ns ns ns MHz Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ΔICC which is obtained from the following formula: C C C C C  ΔICC = fCK ⋅ VCC  QA + QB + QC + QD + CO  2 4 8 16 16   CQA to CQD and CCO are the capacitances at QA to QD and CARRY OUT, respectively. fCK is the input frequency of the CK. Note 2: For TC74VHC161 only © 2019 Toshiba Electronic Devices & Storage Corporation 8 2019-01-31 TC74VHC161,163F/FK Switching Characteristics Test Waveform VCC 50％ twH CK twL 50％ GND twL VCC 50％ VCC GND CK 50％ Q, CARR Y 50％ 50％ Q, CARRY VOL tpLH tpHL Figure 1 Count Mode GND trem VOH Figure 4 VOH 50％ tpHL VOL Clear Mode (TC74VHC161) VCC 50％ ts 50％ th ts GND th VCC A to D 50％ ts 50％ th ts 50％ GND th VCC CK 50％ CK GND VOH Q, CARRY VOL Preset Mode VOH Q, CARRY 50％ Figure 2 50％ GND tpLH, tpHL ENP ENT VCC 50％ Figure 5 VOL Clear Mode (TC74VHC163) VCC 50％ ts 50％ th ts th GND VCC CK 50％ 50％ VCC ENT 50％ 50％ GND GND VOH Q VOH CARRY tpLH VOL Figure 3 Figure 6 Count Enable Mode © 2019 Toshiba Electronic Devices & Storage Corporation 9 50％ 50％ tpHL VOL Cascade Mode (fix maximum count) 2019-01-31 TC74VHC161,163F/FK Noise Characteristics (input: tr = tf = 3 ns) Characteristics Test Condition Symbol Ta = 25°C VCC (V) Typ. Max Unit Quiet output maximum dynamic VOL VOLP CL = 50 pF 5.0 0.4 0.8 V Quiet output minimum dynamic VOL VOLV CL = 50 pF 5.0 −0.4 −0.8 V Minimum high level dynamic input voltage VIHD CL = 50 pF 5.0 ― 3.5 V Maximum low level dynamic input voltage VILD CL = 50 pF 5.0 ― 1.5 V Input Equivalent Circuit INPUT Typical Application Parallel Carry N-Bit Counter H: COUNT L: DISABLE H: COUNT L: DISABLE INPUTS LD A ENP ENT B C INPUTS D CARRY LD A ENP ENT B C INPUTS D CARRY LD A ENP ENT B C D CARRY CK CK CK CLR QA QB QC QD CLR QA QB QC QD CLR QA QB QC QD OUTPUTS OUTPUTS NEXT STAGE OUTPUTS CK © 2019 Toshiba Electronic Devices & Storage Corporation 10 2019-01-31 TC74VHC161,163F/FK Package Dimensions Weight: 0.18 g (typ.) © 2019 Toshiba Electronic Devices & Storage Corporation 11 2019-01-31 TC74VHC161,163F/FK Package Dimensions Weight: 0.02 g (typ.) © 2019 Toshiba Electronic Devices & Storage Corporation 12 2019-01-31 TC74VHC161,163F/FK RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. 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