TMP91CW60DFG

16 Bit Microcontroller TLCS-900/L1 Series TMP91CW60FG TMP91CW60DFG Revision 1.0 TOSHIBA CORPORATION The information contained herein is subject to change without notice. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. © 2007 TOSHIBA CORPORATION All Rights Reserved Revision History Date 2007/12/03 Revision 1.0 New release TMP91CW60 CMOS 16 Bit Microcontroller TMP91CW60FG/DFG Product No. TMP91CW60FG 128K bytes TMP91CW60DFG 8K bytes QFP100-P-1420-0.65A ROM (Flash ROM) RAM Package LQFP100-P-1414-0.50F 1.1 Features • High-speed 16-bit CPU (900/L1 CPU) - Instruction mnemonics are upward-compatible with TLCS-900,900/H,900/L - 16 Mbytes of linear address space - General-purpose registers and register banks - 16-bit multiplication and division instructions; bit transfer and arithmetic instructions - Micro DMA: 4 channels (800ns/2 bytes at 20MHz) • Minimum instruction execution time:200ns (at 20MHz) • Built-in memory - ROM:128K bytes (Flash ROM) - RAM:8K bytes • External memory expansion - Expandable up to 16 Mbytes (shared program/data area) - Can simultaneously support 8/16-bit width external data bus Dynamic data bus syzing • 8-bit timers: 6 channels • 16-bit timers: 5 channels • General-purpose serial interface: 5 channels - UART/Synchronous mode: 3 channels - I2C bus mode: 2 channels • 10-bit AD converter (Built-in Sample hold circuit): 16 channels • Special timer for CLOCK This product uses the Super Flash® technology under the licence of Silicon Storage Technology, Inc. Super Flash® is registered trademark of Silicon Storage Technology, Inc. 20070701-EN • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. Page 1 2007-12-03 TMP91CW60 • Watchdog timer • Program patch logic: 6 banks • Chip select/wait controller: 4 channels • Interrupts: 57 interrupts - 9 CPU interrupts: Software interrupt instruction and illegal instruction - 36 internal interrupts: 7 priority levels are selectable - 12 external interrupts: 7 priority levels are selectable (among 1 interrupts are selectable edge mode) • Input/output ports: 83 pins • Standby function: Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP • Clock controller - Clock gear function: Select a High-frequency clock fc/1 to fc/16 - Oscillator for CLOCK (fs = 32.768 kHz) • Operating voltage Flash read operation > Vcc=4.5 V - 5.5 V (fc max = 20MHz) • Package - LQFP100-P-1414-0.50F (TMP91CW60FG) - QFP100-P-1420-0.65A (TMP91CW60DFG) Page 2 2007-12-03 TMP91CW60 1.2 Pin Assignment Diagram P67/AN15 P66/AN14 P65/AN13 P64/AN12 P63/AN11 P62/AN10 P61/AN9 P60/AN8 P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 DVSS DVCC PB3/TB4OUT1 PB2/TB4OUT0 PB1/TB4IN1/INT10/SCL1 PB0/TB4IN0/INT9/SDA1 P33/TB3OUT1 P32/WAIT/TB3OUT0 P31/TB3IN1/INT4/SCL0 100 95 90 VREFH AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RXD1 P95/SCLK1/CTS1 AM0 DVCC 1 85 80 75 5 70 10 TMP91CW60FG LQFP100 65 15 TOPVIEW 60 20 55 25 P30/TB3IN0/INT3/SDA0 PZ3/R/W PZ2/HWR PZ1/WR PZ0/RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 DVCC NMI DVSS P21/A1/A17 P20/A0/A16 P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 30 35 X2 DVSS X1 AM1 RESET P96/XT1 P97/XT2 EMU0 EMU1 PA0/TB2IN0/INT1 PA1/TB2IN1/INT2 PA2/TB2OUT0 PA3/TB2OUT1 P40/CS0/SCOUT P41/CS1/TXD2 P42/CS2/RXD2 P43/CS3/SCLK2/CTS2 P44/ALE P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 Figure 1-1 Pin Assignment(TMP91CW60FG) 40 45 50 Page 3 2007-12-03 10 70 15 100 80 5 75 65 1 PB0/TB4IN0/INT9/SDA1 PB1/TB4IN1/INT10/SCL1 PB2/TB4OUT0 PB3/TB4OUT1 DVCC DVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/AN8 P61/AN9 P62/AN10 P63/AN11 P64/AN12 P65/AN13 95 90 85 TOPVIEW TMP91CW60DFG Figure 1-2 Pin Assignment(TMP91CW60DFG) Page 4 20 25 30 QFP100 60 P66/AN14 P67/AN15 VREFH AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RXD1 P95/SCLK1/CTS1 AM0 DVCC X2 DVSS X1 55 45 50 40 35 P33/TB3OUT1 P32/WAIT/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 PZ3/R/W PZ2/HWR PZ1/WR PZ0/RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 DVCC NMI DVSS P21/A1/A17 P20/A0/A16 P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 P06/AD6 P05/AD5 TMP91CW60 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P44/ALE P43/CS3/SCLK2/CTS2 P42/CS2/RXD2 P41/CS1/TXD2 P40/CS0/SCOUT PA3/TB2OUT1 PA2/TB2OUT0 PA1/TB2IN1/INT2 PA0/TB2IN0/INT1 EMU1 EMU0 P97/XT2 P96/XT1 RESET AM1 2007-12-03 TMP91CW60 1.3 Block Diagram Mask ROM 128KByte Figure 1-3 Block Diagram Page 5 2007-12-03 TMP91CW60 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/3) Input / Output IO IO IO IO O IO O O O O O O IO O IO O IO I I IO IO I I IO IO I O IO O IO O O IO O O IO O I IO O IO I IO O IO I Pin Name Pin Number Functions P00-P07 AD0-AD7 P10-P17 AD8-AD15 A8-A15 P20-P27 A0-A7 A16-A23 PZ0 RD PZ1 WR PZ2 HWR PZ3 R/W P30 TB3IN0 INT3 SDA0 P31 TB3IN1 INT4 SCL0 P32 WAIT TB3OUT0 P33 TB3OUT1 P40 CS0 SCOUT P41 CS1 TXD2 P42 CS2 RXD2 P43 CS3 SCLK2 CTS2 P44 ALE P50-57 AN0-AN7 8 Port 0: I/O port that allows I/O to be selected at the bit level Address data (Lower): 0 to 7 address/data bus Port1: I/O port that allows I/O to be selected at the bit level Address data (Upper): 8 to 15 of address/data bus Address: 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: 0 to 7 of address bus Address: 16 to 23 of address bus Port Z0: Output port Read:Strobe signal for reading external memory Port Z1: Output port Write: Strobe signal for writing data to pins AD0 to AD7 Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins AD8 to AD15 Port Z3: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. Port 30: I/O port 16-bit timer 3 input 0:Timer B3 count/capture trigger Input 0 Interrupt Request Pin 3: Interrupt request pin with programmable rising edge / falling edge. Serial bus interface data 0 in I2C bus Mode. Port 31: I/O port 16-bit timer 3 input 1:Timer B3 count/capture trigger Input 1 Interrupt Request Pin 4: Interrupt request on rising edge Serial bus interface clock 0 in I2C bus Mode. Port 32: I/O port Wait: Pin used to request CPU bus wait ((1 N) wait mode) 16-bit timer 3 output 0: Timer B3 Output 0 Port 33: I/O port 16-bit timer 3 output 1: Timer B3 Output 1 Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area System Clock Output: Outputs fSYS or fs clock. Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 when address is within specified address area Serial Send Data 2 Port 42: I/O port (with pull-up resistor) Chip Select 2: Outputs 0 when address is within specified address area Serial Receive Data 2 Port 43: I/O port (with pull-up resistor) Chip Select 3: Outputs 0 when address is within specified address area Serial Clock I/O 2 Serial Data Send Enable 2 (Clear to Send) Port 44: I/O port (with pull-up resistor) Address Latch Enable Port 5: I/O port Analog input: Pin used to input to AD converter 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 8 Page 6 2007-12-03 TMP91CW60 Table 1-1 Pin Names and Functions(2/3) Input / Output IO I IO I IO O IO O IO I IO O IO I IO I I IO I I IO O IO O IO I I IO I I IO O IO O IO O IO I IO IO I IO O IO I Pin Name Pin Number Functions P60-67 AN8-AN15 P70 TA0IN P71 TA1OUT P72 TA3OUT P73 TA4IN P74 TA5OUT P75 INT0 P80 TB0IN0 INT5 P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 P90 TXD0 P91 RXD0 P92 SCLK0 CTS0 P93 TXD1 P94 RXD1 8 Port 6: I/O port Analog input: Pin used to input to AD converter Port 70: I/O port 8-bit timer 0 input: Timer A0 Input Port 71: I/O port 8-bit timer 1 output:Timer A1 Output Port 72: I/O port 8-bit timer 3 output:Timer A3 Output Port 73: I/O port 8-bit timer 4 input: Timer A4 Input Port 74: I/O port 8-bit timer 5 output:Timer A5 Output Port 75: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge. Port 80: I/O port 16-bit timer 0 input 0:Timer B0 count/capture trigger Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. Port 81: I/O port 16-bit timer 0 input 1:Timer B0 count/capture trigger Input 1 Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port 16-bit timer 0 output 0: Timer B0 Output 0 Port 83: I/O port 16-bit timer 0 output 1: Timer B0 Output 1 Port 84: I/O port 16-bit timer 1 input 0:Timer B1 count/capture trigger Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. Port 85: I/O port 16-bit timer 1 input 1:Timer B1 count/capture trigger Input 1 Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port 16-bit timer 1 output 0: Timer B1 Output 0 Port 87: I/O port 16-bit timer 1 output 1: Timer B1 Output 1 Port 90: I/O port Serial Send Data 0 Port 91: I/O port Serial Receive Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 Port 94: I/O port Serial Receive Data 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Page 7 2007-12-03 TMP91CW60 Table 1-1 Pin Names and Functions(3/3) Input / Output IO IO I IO I IO O IO I I IO I I IO O IO O IO I I IO IO I I IO IO O IO O Port 95: I/O port Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port Low-frequency oscillator connection pin Port 97: I/O port Low-frequency oscillator connection pin Port A0: I/O port 16-bit timer 2 input 0:Timer B2 count/capture trigger Input 0 Interrupt Request Pin 1: Interrupt request pin with programmable rising edge / falling edge. Port A1: I/O port 16-bit timer 2 input 1:Timer B2 count/capture trigger Input 1 Interrupt Request Pin 2: Interrupt request on rising edge Port A2: I/O port 16-bit timer 2 output 0: Timer B2 Output 0 Port A3: I/O port 16-bit timer 2 output 1: Timer B2 Output 1 Port B0: I/O port 16-bit timer 4 input 0:Timer B4 count/capture trigger Input 0 Interrupt Request Pin 9: Interrupt request pin with programmable rising edge / falling edge. Serial bus interface data 1 in I2C bus Mode. Port B1: I/O port 16-bit timer 4 input 1:Timer B4 count/capture trigger Input 1 Interrupt Request Pin 10: Interrupt request on rising edge Serial bus interface clock 1 in I2C bus Mode. Port B2: I/O port 16-bit timer 4 output 0: Timer B4 Output 0 Port B3: I/O port 16-bit timer 4 output 1: Timer B4 Output 1 Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling edge or both edge. Operation mode:Fixed to AM1 "1", AM0 "1". Set to Open pins Reset: initializes TMP91CW60. (with pull-up resistor) Pin for reference voltage input to AD converter Power supply pin for AD converter GND pin for AD converter (0 V) IO High frequency oscillator connection pins Power supply pins (All DVCC pins should be connected with the power supply pin.) GND pins (0 V) (All DVSS pins should be connected with the GND (0V) pin.) Pin Name Pin Number Functions P95 SCLK1 CTS1 P96 XT1 P97 XT2 PA0 TB2IN0 INT1 PA1 TB2IN1 INT2 PA2 TB2OUT0 PA3 TB2OUT1 PB0 TB4IN0 INT9 SDA1 PB1 TB4IN1 INT10 SCL1 PB2 TB4OUT0 PB3 TB4OUT1 1 1 1 1 1 1 1 1 1 1 1 NMI 1 I AM0-1 EMU0-1 RESET VREFH AVCC AVSS X1/X2 DVCC DVSS 2 2 1 1 1 1 2 3 3 I O I I Note: All pins that have built-in pull-up resistors (other than the RESET pin) can be disconnected from the built-in pull-up resistor by software. Page 8 2007-12-03 TMP91CW60 2. CPU The TMP91CW60 incorporates a high-performance 16-bit CPU (The 900/L1-CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describe the unique function of the CPU used in the TMP91CW60; these functions are not covered in the TLCS-900/L1 CPU section. 2.1 RESET When resetting the TMP91CW60 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks (1us at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. It means that the system clock mode fSYS is set to fc/2. When the reset is accept, the CPU: 1. Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: - PC (7:0) - PC (15:8)