TMP93PW20A

TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93PW20A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to INT4, INTKEY and INTRTC), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (RUN and IDLE2 are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93PW20A Low Voltage/Low Power CMOS 16-Bit Microcontroller TMP93PW20AF 1. Outline and Device Characteristics The TMP93PW20A is OTP type MCU which includes 128 Kbytes one-time PROM. Using the adapter-socket, you can write and verify the data for the TMP93CS20 by general EPROM programmer. The TMP93PW20A has the same pin-assignment as the TMP93CS20 (Mask ROM type). Writing the program to built-in PROM, the TMP93PW20A operates as the same way as the TMP93CS20. There are differences in the memory mapping area and the memory capacity of the internal PROM and RAM between the TMP93PW20A and the TMP93CS20. The internal PROM of the TMP93PW20A is 128 Kbytes, and the internal RAM is 4 Kbytes. The internal ROM of the TMP93CS20 is 64 Kbytes, and the internal RAM is 2 Kbytes. Memory maps are described as follows. 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. 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Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 93PW20A-1 2004-02-10 TMP93PW20A 000000H 0000A0H Internal I/O (128 bytes) Internal RAM (4 Kbytes) 000000H 0000A0H Internal I/O (128 bytes) Internal RAM (2 Kbytes) 0008A0H 0010A0H FE0000H Internal PROM (128 Kbytes) FFFF00H Interrupt vector table area (256 bytes) FFFFFFH Memory map of TMP93PW20A FFFFFFH Memory map of TMP93CS20 FF0000H Internal ROM (64 Kbytes) FFFF00H Interrupt vector table area (256 bytes) Product No. TMP93PW20A ROM OTP 128 Kbytes RAM 4 Kbytes Package P-LQFP144-1616-0.40 Adapter Socket BM11141 93PW20A-2 2004-02-10 TMP93PW20A ADTRG (P37) AN0 to AN7 (P50 to P57) AVCC AVSS VREFH VREFL CPU (900/L) 10-bit 8 channel AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR P Serial I/O (Cannel 0) C F VCC [3] VSS [8] X1 X2 OSC1 Clock Gear SCK (P60) SO/SDA (P61) SI/SCL (P62) TXD0 (P63) RXD0 (P64) SCLK0/ CTS0 (P65) TXD1 (P80) RXD1 (P81) Serial bus interface OSC2 XT1 (P86) XT2 (P87) CLK ALE SCOUT (P73) EA RESET RD (P30) WR (P31) HWR (P32) WAIT (P84) Serial I/O (Channel 1) 4 Kbytes RAM TI0 (P66) 8-bit timer (Timer 0) TO1 (P67) 8-bit timer (Timer 1) Port 0 P00 to P07 (AD0 to AD7) P10 to P17 (AD8/A8 to AD15/A15) TI2 (P82) 8-bit timer (Timer 2) Port 1 TO3 (P83) 8-bit timer (Timer 3) 128 Kbytes ROM Port 2 P20 to P27 (A0/A16 to A7/A23) TI8/INT8 (P70) TI9/INT9 (P71) TO8 (P72) TIA/INTA (P74) TIB/INTB (P75) TOA (P76) TI4 (P40) TO4 (P41) 16-bit timer (Timer 4) 16-bit timer (Timer 8) TI6 (P42) TO6 (P43) 16-bit timer (Timer A) 16-bit timer (Timer 6) Interrupt controller KEY0 to KEY7 (P40 to P47) NMI (P77) INT0 to INT4 (P33 to P37) INT7 (P66) Key wakeup (KEY0 to KEY7) Watchdog timer V1 to V3 C0 to C1 SEG0 to SEG23 SEG24 to SEG39 (P90 to PA7) COM0 to COM3 LCD driver Real time counter Note: The item in parentheses ( ) are the initial setting after reset. Figure 1.1 TMP93PW20A Block Diagram 93PW20A-3 2004-02-10 TMP93PW20A 2. Pin Assignment and Functions The assignment of input/output pins for the TMP93PW20A their names and outline functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of the TMP93PW20AF. 108 109 (SEG34) PA2 (SEG35) PA3 (SEG36) PA4 (SEG37) PA5 (SEG38) PA6 (SEG39) PA7 ( RD ) P30 VSS ( WR ) P31 ( HWR ) P32 (INT0) P33 (INT1) P34 (INT2) P35 (INT3) P36 (INT4/ ADTRG ) P37 VREFH VREFL (AN7) P57 (AN6) P56 (AN5) P55 (AN4) P54 (AN3) P53 (AN2) P52 (AN1) P51 (AN0) P50 AVCC AVSS VSS VCC (AD0) P00 (AD1) P01 (AD2) P02 (AD3) P03 (AD4) P04 (AD5) P05 (AD6) P06 110 105 100 95 90 85 80 75 70 PA1 (SEG33) PA0 (SEG32) P97 (SEG31) P96 (SEG30) P95 (SEG29) P94 (SEG28) P93 (SEG27) P92 (SEG26) VSS P91 (SEG25) P90 (SEG24) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 VSS SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 73 72 COM3 COM2 COM1 COM0 C1 C0 V3 VCC VSS V2 V1 P47 (KEY7) P46 (KEY6) P45 (KEY5) P44 (KEY4) P43 (TO6/KEY3) P42 (TI6/KEY2) P41 (TO4/KEY1) P40 (TI4/KEY0) P85 P84 ( WAIT ) P83 (TO3) P82 (TI2) P81 (RXD1) P80 (TXD1) P77 ( NMI ) P76 (TOA) P75 (TIB/INTB) VSS P74 (TIA/INTA) P73 (SCOUT) P72 (TO8) P71 (TI9/INT9) P70 (TI8/INT8) P67 (TO1) P66 (TI0/INT7) 115 65 120 60 125 TMP93PW20AF LQFP144 Top view 55 130 50 135 45 140 5 144 1 (AD7) P07 (AD8/A8) P10 (AD9/A9) P11 (AD10/A10) P12 (AD11/A11) P13 (AD12/A12) P14 (AD13/A13) P15 VSS (AD14/A14) P16 (AD15/A15) P17 (A0/A16) P20 (A1/A17) P21 (A2/A18) P22 (A3/A19) P23 (A4/A20) P24 (A5/A21) P25 (A6/A22) P26 (A7/A23) P27 CLK ALE EA X1 X2 TEST1 TEST2 (XT1) P86 (XT2) P87 VSS VCC RESET 40 10 15 20 25 30 35 36 (SCK) P60 (SO/SDA) P61 (SI/SCL) P62 (TXD0) P63 (RXD0) P64 (SCLK0/CTS0) P65 37 Figure 2.1.1 Pin Assignment (144-pin LQFP) 93PW20A-4 2004-02-10 TMP93PW20A 2.2 Pin Names and Functions The TMP93PW20A has MCU mode and PROM mode. (1) Pin functions of TMP93PW20A in MCU mode. Table 2.2.1 Name and Function in MCU Mode (1/3) Functions Port 0: I/O port that allows I/O to be selected at the bit level. Address and data (lower): Bits 0 to 7 for address and data bus. Port 1: I/O port that allows I/O to be selected at the bit level. Address and data (Upper): Bits 8 to 15 for address and data bus. Address: Bits 8 to 15 for address bus. Port 2: I/O port that allows I/O to be selected at the bit level (with pull-up resistor). Address: Bits 0 to 7 for address bus. Address: Bits 16 to 23 for address bus. Port 30: Output port. Read: Strobe signal for reading external memory. (Read when reading internal memory at P3 = 0, P3FC = 1.) Port 31: Output port. Write: Strobe signal for writing data on pins AD0 to AD7. Port 32: I/O port (with pull-up resistor). High write: Strobe signal for writing data on pins AD8 to AD15. Port 33: I/O port (with pull-up resistor). Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge. Port 34: I/O port (with pull-up resistor). Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge. Port 35: I/O port (with pull-up resistor). Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge. Port 36: I/O port (with pull-up resistor). Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge. Port 37: I/O port (with pull-up resistor). Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge. ADTRG Input AD external trigger pin: External trigger pin to start AD conversion. Port 40: I/O port (with pull-up resistor). Timer input 4: 16-bit timer 4 input. Key input 0: Key-on wakeup pin 0. Port 41: I/O port (with pull-up resistor). Timer output 4: 16-bit timer 4 output. Key input 1: Key-on wakeup pin 1. Port 42: I/O port (with pull-up resistor). Timer input 6: 16-bit timer 6 input. Key input 2: Key-on wakeup pin 2. Port 43: I/O port (with pull-up resistor). Timer output 6: 16-bit timer 6 output. Key input 3: Key-on wakeup pin 3. Port 44 to 47: I/O port (with pull-up resistor). Key input 4 to 7: Key-on wakeup pin 4 to 7. Port 50 to 57: Pin used to input port. Analog input 0 to 7. Pin Names P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O I/O I/O I/O I/O Output I/O Output Output Output Output Output Output I/O Output I/O Input I/O Input I/O Input I/O Input I/O Input Input 8 1 P31 WR 1 1 1 P32 HWR P33 INT0 P34 INT1 P35 INT2 P36 INT3 P37 INT4 ADTRG 1 1 1 1 P40 TI4 KEY0 P41 TO4 KEY1 P42 TI6 KEY2 P43 TO6 KEY3 P44 to P47 KEY4 to KEY7 P50 to P57 AN0 to AN7 1 I/O Input Input I/O Output Input I/O Input Input I/O Output Input I/O Input Input Input 1 1 1 4 8 93PW20A-5 2004-02-10 TMP93PW20A Table 2.2.1 Pin Names P60 SCK P61 SO SDA P62 SI SCL P63 TXD0 P64 RXD0 P65 SCLK0 CTS0 Name and Function in MCU Mode (2/3) Functions Port 60: I/O port. Clock I/O pin in SIO mode of the serial bus interface. Port 61: I/O port (with programmable open drain). Data send channel in SIO mode of the serial bus interface. Data I/O pin in I2C bus mode of the serial bus interface. Port 62: I/O port (with programmable open drain). Data receive channel in SIO mode of the serial bus interface. Clock I/O pin in I2C bus mode of the serial bus interface. Port 63: I/O port (with programmable open drain). Serial send data 0. Port 64: I/O port. Serial receive data 0. Port 65: I/O port. Serial clock I/O 0. Serial data send enable 0 (Clear to send). Port 66: I/O port. Timer input 0: 8-bit timer 0 input. Interrupt request pin 7: Interrupt request pin with programmable rising/falling edge. Port 67: I/O port. Timer output1: 8-bit timer 0 or timer 1 output. Port 70: I/O port (with pull-up resistor). Timer input 8: 16-bit timer 8 input. Interrupt request pin 8: Interrupt request pin with programmable rising/falling edge. Port 71: I/O port (with pull-up resistor). Timer input 9: 16-bit timer 8 input. Interrupt request pin 9: Interrupt request pin with rising edge. Port 72: I/O port (with pull-up resistor). Timer output 8: 16-bit timer 8 output. Port 73: I/O port (with pull-up resistor). System clock output: System clock or double system clock output to be synchronized with the external circuit. Port 74: I/O port (with pull-up resistor). Timer input A: 16-bit timer A input. Interrupt request pin A: Interrupt request pin with programmable rising/falling edge. Port 75: I/O port (with pull-up resistor). Timer input B: 16-bit timer B input. Interrupt request pin B: Interrupt request pin with rising edge. Port 76: I/O port (with pull-up resistor). Timer output A: 16-bit timer A output. Port 77: I/O port (with pull-up resistor). Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge or both edges. Port 80: I/O port (with programmable open drain). Serial send data 1. Port 81: I/O port (with programmable open drain). Serial receive data 1. Port 82: I/O port (with programmable open drain). Timer input 2: 8-bit timer 2 input pin. Port 83: I/O port (with programmable open drain). Timer output 3: 8-bit timer 2, 3 output pin. Port 84: I/O port (with programmable open drain). Wait: Pin used to request CPU bus wait. Number of Pins 1 1 I/O I/O I/O I/O Output I/O I/O Input I/O I/O Output I/O Input I/O I/O Input I/O Input Input I/O Output I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Input I/O Output I/O Input I/O Input I/O Output I/O Input 1 1 1 1 P66 TI0 INT7 P67 TO1 P70 TI8 INT8 P71 TI9 INT9 P72 TO8 P73 SCOUT P74 TIA INTA P75 TIB INTB P76 TOA P77 NMI 1 1 1 1 1 1 1 1 1 1 P80 TXD1 P81 RXD1 P82 TI2 P83 TO3 P84 WAIT 1 1 1 1 1 93PW20A-6 2004-02-10 TMP93PW20A Table 2.2.1 Pin Names P85 P86 XT1 P87 XT2 P90 to P97 SEG24 to SEG31 PA0 to PA7 SEG32 to SEG39 SEG0 to SEG23 COM0 to COM3 AVCC AVSS VREFH VREFL X1 X2 RESET Name and Function in MCU Mode (3/3) Functions Port 85: I/O port (with programmable open drain). Port 86: I/O port (Open drain). Low-frequency oscillator connecting pin. Port 87: I/O port (Open drain). Low-frequency oscillator connecting pin. Port 90 to port 97: Output port (Open drain). Segment data output pin. Port A0 to A7: Output port, large current port (Open drain). LCD segment output pin. LCD segment output. LCD common output. Number of Pins 1 1 1 8 8 24 4 1 1 1 1 1 1 1 1 1 I/O I/O I/O Input I/O Output Output Output Output Output Output Output Power supply Power supply pin for AD converter. Power supply GND pin for AD converter (0 V). Input Input Input Output Input Output Output Pin for reference voltage input to AD converter (H). Pin for reference voltage input to AD converter (L). Oscillator connecting pin. Oscillator connecting pin. Reset: Initializes LSI. Address latch enable. Can be disabled for reducing noise. Clock output: Outputs “external input clock × 1 ÷ 4” clock. Pulled-up during reset. Can be disabled for reducing noise. The VCC pin should be connected. ALE CLK EA 1 3 8 2 5 Input VCC VSS TEST1 TEST2 C0, C1, V1 to V3 Power supply Power supply pin (All Vcc pins should be connected with the power supply pin). Power supply GND pin (0 V) (All Vss pins should be connected with GND (0 V)). Output Input LCD pin TEST1 should be connected with TEST2 pin. Do not connect to any other pins. LCD drive boosting pin. A condenser should be connected between C0 and C1, V1, V2, V3 and GND. Note: All pins that have built-in pull-up resistors can be disconnected from the built-in pull-up resistor by software. 93PW20A-7 2004-02-10 TMP93PW20A (2) Pin function of the TMP93PW20A in PROM mode Pin names and functions are shown in Table 2.2.2. Table 2.2.2 Pin Names A7 to A0 A15 to A8 A16 D7 to D0 CE OE PGM Pin Names and Function in PROM Mode Functions Memory address of program Memory data of program Chip enable Output control Program control 12.75 V/5 V (Power supply of program) 6.25 V/5 V 0V Number of Input/Output Pins 8 8 1 8 1 1 1 1 4 9 Input Input Input I/O Input Input Input Power supply Power supply Power supply Pin Names (in MCU mode) P27 to P20 P17 to P10 P67 P07 to P00 P32 P30 P31 EA VPP VCC VSS VCC, AVCC VSS, AVSS Pin Names P60 RESET Number of Input/Output Pins 1 1 1 1 1 1 6 2 Input Input Input Output Input Output Input Output Input Fix to low level (Security pin) Fix to low level (PROM mode) Open Self oscillation with resonator Fix to high level Pin State CLK ALE X1 X2 P66 to P61 TEST1 TEST2 P37 to P33 P47 to P40 P57 to P50 P77 to P70 P87 to P80 P97 to P90 PA7 to PA0 SEG23 to SEG0 VREFH VREFL C0, C1 COM3 to COM0 V3 to V1 TEST1 should be connected with TEST2 pin Do not connect to any other pins 88 I/O Open 93PW20A-8 2004-02-10 TMP93PW20A 3. Operation This section describes the functions and basic operational blocks of the TMP93PW20A. The TMP93PW20A has PROM in place of the mask ROM which is included in the TMP93CS20. The other configuration and functions are the same as the TMP93CS20. Regarding the function of the TMP93PW20A, which is not described herein, see the TMP93CS20. The TMP93PW20A has two operational modes: MCU mode and PROM mode. 3.1 MCU mode (1) Mode setting and function The MCU mode is set by releasing the CLK pin (Pin open). In the MCU mode, the operation is the same as TMP93CS20. (2) Memory map The memory map of TMP93PW20A differs from that of TMP93CS20. The memory map in MCU mode is show in Figure 3.1.1, and the memory map in PROM mode is shown in Figure 3.1.2. 000000H Internal I/O (160 bytes) 0000A0H Internal RAM (4 Kbytes) 0010A0H 00000H Internal PROM (128 Kbytes) FE0000H Internal PROM (128 Kbytes) FFFF00H FFFFFFH Interrupt vector table area (256 bytes) 1FFFFH =Internal area) ( Figure 3.1.1 Memory Map in MCU Mode Figure 3.1.2 Memory Map in PROM Mode 93PW20A-9 2004-02-10 TMP93PW20A (3) Note on setting of the wait controller The TMP93PW20A has a wide memory area compared as the TMP93CS20. For the addressing area of WAITC1, there is a difference between the TMP93PW20A and the TMP93CS20. When bits 1 and 0 < B1C1:0> in the chip select and wait control register 1 (WAITC1) is set to 00, the address area is specified as follows. TMP93PW20A 10A0H to 7FFFH TMP93CS20 8A0H to 7FFFH 3.2 PROM Mode (1) Mode setting and programming PROM mode is set by setting the RESET and CLK pins to the “Low” level. The programming and verification for the internal PROM is achieved by using a general PROM programmer with the adaptor socket. 1. 2. 3. OTP adaptor BM11141: TMP93PW20AF adaptor Setting OTP adaptor Set the switch (SW1) to N side. Setting PROM programmer i) Set PROM type to TC571000D. Size: 1 Mbits (128 K × 8 bits) VPP: 12.75 V tPW: 100 µs Electric signature function: None ii) Transferring the data (Copy) In TMP93PW20AF, PROM is placed on addresses 00000H to 1FFFFH in PROM mode, and addresses FE0000H to FFFFFFH in MCU mode. Therefore data should be transferred to addresses 00000H to 1FFFFH in PROM mode using the object converter (tuconv) or the block transfer mode. (See instruction manual of PROM programmer.) iii) Setting program address Start address: 00000H End address: 4. Programming Program/verify according to the procedures of PROM programmer. 1FFFFH 93PW20A-10 2004-02-10 TMP93PW20A VPP (12.75 V/5 V) EA VCC AVCC, VCC P30 P32 P31 P07 to P00 RESET OE CE PGM TEST1 TEST2 A16 to A0 P67 P17 to P10 P27 to P20 D7 to D0 * CLK VCC See “Pin Names and Function in PROM Mode” in Table 2.2.2 for other pin’s states. Use the 10 MHz resonator in case of programming and verification by a general EPROM programmer. X1 P65 to P61 X2 VSS AVSS P60 Security Figure 3.2.1 (2) Note on electric signature Pin Setting in PROM Mode The electric signature mode (Hereinafter referred to as “signature”) is not supported in the TMP93PW20A. Therefore using signature with PROM programmer applies voltage of 12 ± 0.5 V to pin 9 (A9) of the address, and the device is damaged. Do not use signature. (3) Program mode The TMP93PW20A is provided with all bits set to 1 (OFF). When programming it, write data 0 to necessary bit locations. Applying VPP = 12.5 V, OE = VIH CE = VIL enables writing data. The one-time PROM which is included in the TMP93PW20A can write data in any order. It is possible to write a special address. (4) Adapter socket (BM11141) The BM11141 is an adapter socket to write data to the one-time PROM in the TMP93PW20A using a general PROM programmer. (5) Program storage area in PROM mode The TMP93PW20A has a program area (FE0000H to FFFFFFH) of 128 Kbytes. In PROM mode, addresses 00000H to 1FFFFH correspond to addresses FE0000H to FFFFFFH in MCU mode. 93PW20A-11 2004-02-10 TMP93PW20A (6) How to program with a general PROM programmer The PROM programmer should be equivalent to TC571000D. 1. 2. 3. 4. 5. 6. Set a switch (SW1) of BM11141 to a program side (NOR). (BM11141 is hereinafter referred as an adapter.) (Note 1) Set a MCU to the adapter. (Note 2) Set the adapter to the PROM programmer. (Note 2) Specify TC571000D as a type of the PROM. Set a start address to 00000H and an end address to 1FFFFH to write the PROM. (Note 3) Write the one-time PROM and verify according to operational procedures of the PROM programmer. Note 1: If you write a data to the one-time PROM without setting the switch (SW1) to the program side, a device should be damaged. Note 2: 1 pin marked on the socket of the PROM programmer must be matched to the 1 pin of the adapter. If you set them in reverse, the MCU or the PROM programmer should be damaged. Note 3: When data 0 is written to an address over 1FFFFH, there is a possibility that the data is written to addresses 00000H to 1FFFFH and an original program is corrupted. (7) Programming flow chart The programming mode is set by applying 12.75 V (programming voltage) to the VPP pin when the following pins are set as follows, (VCC: 6.25 V, RESET : “Low” level, CLK: “Low” level). While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “Low” level pulse is applied to PGM pin to program the data. Then the data in the address is verified. If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address (25 times maximum). Subsequently, all data are programmed in all addresses. The verification for all data is done under the condition of VPP = VCC = 5 V after all data were written. Figure 3.2.2 shows the programming flowchart. 93PW20A-12 2004-02-10 TMP93PW20A High Speed Program Writing. Flowchart Start VCC = 6.25 V ± 0.25 V VPP = 12.75 V ± 0.25 V Address = Start address X=0 Program 0.1 ms pulse X=X+1 X > 25? No Error Address = Address + 1 No Verify OK Last address? Yes VCC = 5 V VPP = 5 V Yes Read all data OK Pass Error Failure Figure 3.2.2 Flowchart 93PW20A-13 2004-02-10 TMP93PW20A (8) Security bit The TMP93PW20A has a security bit. If the security bit is programmed to 0, the content of the PROM can not be read in PROM mode. (Outputs data FFH) (How to program the security bit) The difference from the programming procedures described in section 3.2 (1) are follows. 1. 2. Setting OTP adapter Set the switch (SW1) to S side. Setting PROM programmer i) ii) Transferring the data Setting programming address The security bit is in bit 0 of address 00000H. Set the start address 00000H and the end address 00000H. Set the data FEH at the address 00000H. 93PW20A-14 2004-02-10 TMP93PW20A 4. 4.1 Electrical Characteristics Maximum Rating (TMP93PW20A) “X” used in an expression shows a frequency for the clock fFPH selected by SYSCR1. The value of X changes according to whether a clock gear or a low speed oscillator is selected. An example value is calculated for fc, with gear = fc/1 (SYSCR1 = 0000). Parameter Power supply voltage Input voltage Output current (Per one pin), large current port Output current (Per one pin) Output current (Total of large current port) Output current (Total) Output current (Total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature Symbol VCC VIN IOL1 IOL2 ΣIOL1 ΣIOL ΣIOH PD TSOLDER TSTG TOPR EA pin Rating −0.5 to 6.5 Except EA pin −0.5 to VCC + 0.5 −0.5 to 14.0 20 2 80 120 −80 600 260 −65 to150 −40 to 85 Unit V mA mW °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) Ta = −40 to 85°C Parameter Power supply voltage AVCC = VCC AVSS = VSS = 0 V AD0 to AD15 Port Input low voltage KEY0 to KEY7, NMI, INT0 to INT4 EA Symbol VCC VIL VIL1 VIL1 VIL2 VIL3 VIL4 VIL5 VIH VIH VIH1 VIH2 VIH3 VIH4 VIH5 Condition fc = 4 to 20 MHz fs = 30 to fc = 4 to 12.5 MHz 34 kHz VCC ≥ 4.5 V VCC < 4.5 V Min 4.5 2.7 Typ. (Note) Max 5.5 0.8 0.6 0.3 VCC Unit V −0.3 VCC = 2.7 to 5.5 V 0.25 VCC 0.3 0.2 VCC 0.1 VCC X1 RESET AD0 to AD15 Port Input high KEY0 to KEY7, voltage NMI , INT0 to INT4 EA VCC ≥ 4.5 V VCC ≥ 4.5 V 2.2 2.0 0.7 VCC 0.75 VCC VCC + 0.3 V VCC = 2.7 to 5.5 V Vcc − 0.3 0.8 VCC 0.6 VCC X1 RESET Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. 93PW20A-15 2004-02-10 TMP93PW20A 4.2 DC Characteristics (2/2) Parameter Symbol VOL IOLA VOH1 Condition IOL = 1.6 mA (VCC = 2.7 to 5.5 V) VOL = 1.0 V (VCC = 5 V ± 10%) (VCC = 3 V ± 10%) Min Typ. (Note 1) Max 0.45 Unit V mA Output low voltage Output low current (PA0 to PA7) 16 7 2.4 Output high voltage VOH2 Darlington drive current (8 output pins max) Input leakage current Output leakage current Power down voltage (at stop, RAM backup) Pin capacitance Shumitt width KEYx, NMI , INT0 to INT4, RESET Programmable pull-up resistance NORMAL RUN IDLE2 IDLE1 NORMAL RUN IDLE2 IDLE1 SLOW RUN IDLE2 IDLE1 STOP ICC IDAR (Note 2) ILI ILO VSTOP CIO VTH RKH IOH = −400 µA (VCC = 3 V ± 10%) IOH = −400 µA (VCC = 5 V ± 10%) VEXT = 1.5 V REXT = 1.1 kΩ (VCC = 5 V ± 10% only) 0.0 ≤ VIN ≤ VCC 0.2 ≤ VIN ≤ VCC − 0.2 VIL2 = 0.2 VCC, VIH2 = 0.8 VCC fc = 1 MHz V 4.2 −1.0 0.02 0.05 2.0 −3.5 ±5 ±10 6.0 10 0.4 1.0 150 300 32 40 30 21 7 20 14 10 3 55 42 33 24 10 0.2 20 50 µA µA mA mA 24 17 4.5 14 10 7 2 40 30 20 10 mA µA V pF V kΩ VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% fc = 20 MHz 50 100 VCC = 3 V ± 10% fc = 12.5 MHz (Typ. VCC = 3.0 V) Vcc = 3 V ± 10% fs = 32.768 kHz (Typ. VCC = 3.0 V) at boosting frequency = 1 kHz Ta ≤ 50°C Ta ≤ 70°C Ta ≤ 85°C Note 1: Note 2: Note 3: Note 4: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. IDAR is guaranteed for up to eight ports. Segment or common output is not loaded. ICC measurement conditions (NORMAL, SLOW): Only CPU is operational; output pins are open and input pins are fixed. (e.g.) Diagram of IDAR REXT IDAR VEXT 93PW20A-16 2004-02-10 TMP93PW20A 4.3 AC Electrical Characteristics (1) VCC = 5 V ± 10% Variable Min 50 2x − 40 0.5x − 20 1.5x − 70 0.5x − 15 0.5x − 20 x − 40 0.5x − 25 0.5x − 20 x − 25 1.5x − 50 0.5x − 25 3.0x − 55 3.5x − 65 2.0x − 60 2.0x − 40 0 x − 15 2.0x − 40 2.0x − 55 0.5x − 15 3.5x − 90 3.0x − 80 2.0x + 0 2.5x − 120 2.5x + 50 200 206 200 125 36 175 200 85 0 48 85 70 16 129 108 100 5 No. 1 2 3 4 5 6 7 8 9 Parameter Osc. period (= x) CLK width A0 to A23 valid → CLK hold CLK valid → A0 to A23 hold A0 to A15 valid → ALE fall ALE fall → A0 to A15 hold ALE high width ALE fall → RD / WR fall RD / WR rise → ALE rise Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode 16 MHz Min 62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65 20 MHz Min 50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70 Max 31250 Max Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 15 16 17 18 19 21 RD fall → D0 to D15 input RD low pulse width RD rise → D0 to D15 hold RD rise → A0 to A15 output WR low pulse width WR rise → D0 to D15 hold 20 D0 to D15 valid → WR rise 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold tAWH tAWL tCW tAPH tAPH2 tCP 25 A0 to A23 valid → Port input 26 A0 to A23 valid → Port hold 27 WR rise → Port valid AC measuring conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However, CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (except AD0 to AD15) 93PW20A-17 2004-02-10 TMP93PW20A (2) VCC = 3 V ± 10% No. 1 2 3 4 5 6 7 8 9 Osc. period (= x) CLK width A0 to A23 valid → CLK hold CLK valid → A0 to A23 hold A0 to A15 valid → ALE fall ALE fall → A0 to A15 hold ALE high width ALE fall → RD / WR fall RD / WR rise → ALE rise Parameter Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode Variable Min 80 2x − 40 0.5x − 30 1.5x − 80 0.5x − 35 0.5x − 35 x − 60 0.5x − 35 0.5x − 40 x − 50 1.5x − 50 0.5x − 40 3.0x − 110 3.5x − 125 2.0x − 115 2.0x − 40 0 x − 25 2.0x − 40 2.0x − 120 0.5x − 40 3.5x − 130 3.0x − 100 2.0x + 0 2.5x − 120 2.5x + 50 200 12.5 MHz Min 80 120 10 40 5 5 20 5 0 30 70 0 130 155 45 120 0 55 120 40 0 150 140 160 80 250 200 Max 31250 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 15 16 17 18 19 21 RD fall → D0 to D15 input RD low pulse width RD rise → D0 to D15 hold RD rise → A0 to A15 output WR low pulse width WR rise → D0 to D15 hold 20 D0 to D15 valid → WR rise 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold tAWH tAWL tCW tAPH tAPH2 tCP 25 A0 to A23 valid → Port input 26 A0 to A23 valid → Port hold 27 WR rise → Port valid AC measuring conditions • • Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF Input level: High 0.9 × VCC/Low 0.1 × VCC 93PW20A-18 2004-02-10 TMP93PW20A (1) Read cycle tOSC X1/XT1 tCLK CLK tAK A0 to A23 tAWH tAWL WAIT tKA tCW tAPH tAPH2 Port input (Note) tADH tCA tRR RD tACH tACL tLC tRD tADL tHR D0 to D15 tCL tRAE AD0 to AD15 tAL A0 to A15 tLA ALE tLL Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW20A-19 2004-02-10 TMP93PW20A (2) Write cycle X1/XT1 CLK A0 to A23 WAIT Port output (Note) WR , HWR tWW tCP tDW AD0 to AD15 A0 to A15 D0 to D15 tWD ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW20A-20 2004-02-10 TMP93PW20A 4.4 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Symbol Min tSCY tOSS tOHS tHSR tSRD 16x tSCY/2 − 5x − 50 5x − 100 0 tSCY − 5x − 100 Variable Max 32.768 MHz (Note) 12.5 MHz Min 488 µs 91.5 µs 152 µs 0 336 µs Max Min 1.28 190 300 0 780 Max 20 MHz Min 0.8 100 150 0 450 Max µs ns ns ns ns Unit Parameter SCLK cycle Output data → SCLK rising edge or falling edge* SCLK rising edge or falling edge* → Output data hold SCLK rising edge or falling edge* → Input data hold SCLK rising edge or falling edge* → Effective data input Note: System clock is fs, or input clock to prescaler is divisor clock of fs. *) The rising edge is used in SCLK Rising mode. The falling edge is used in SCLK Falling mode. 2. SCLK output mode Symbol Min Variable Max 8192x 32.768 kHz (Note) Min 427 µs 60 µs 0 tSCY − 2x − 150 428 µs Max 12.5 MHz Min 970 80 0 970 Max 20 MHz Min 550 20 0 550 Max µs ns ns ns ns Unit Parameter SCLK cycle (Programmable) Output data → SCLK rising edge SCLK rising edge → Output data hold SCLK rising edge → Input data hold tSCY tOSS tOHS tHSR 16x tSCY − 2x − 150 2x − 80 0 488 µs 250 ms 1.28 655.36 0.8 409.6 SCLK rising edge t → Effective data hold SRD Note: System clock is fs, or input clock to prescaler is divisor clock of fs. SCLK SCLK output mode (Only rising edge is used) or SCLK input mode (SCLK rising edge mode) tSCY SCLK SCLK input mode (SCLK falling edge mode) tOSS 0 tOHS 1 tSRD tHSR 1 Valid 2 Valid 3 Valid 2 3 Output data TXD Input data RXD 0 Valid (2) UART mode (SCLK0 and SCLK1 external input) Parameter SCLK cycle SCLK low level pulse width SCLK high level pulse width Symbol Min tSCY tSCYL tSCYH 4x + 20 2x + 5 2x + 5 Variable Max 32.768 kHz (Note) Min 122 µs 6 µs 6 µs Max 12.5 MHz Min 340 165 165 Max 20 MHz Min 220 105 105 Max ns ns ns Unit Note: System clock is fs, or input clock to prescaler is divisor clock of fs. 93PW20A-21 2004-02-10 TMP93PW20A 4.5 AD Converter Characteristics (VSS = 0 V, AVCC = VCC, AVSS = VSS, Ta = −40 to 85°C) AVCC = VCC, AVSS = VSS Parameter Analog reference voltage (+) Analog reference voltage (−) Analog input voltage range Analog current for analog reference voltage = 1 = 0 Error (Not including quantizing errors) Symbol VREFH VREFL VAIN Condition VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% VCC = 3 V ± 10% Min VCC − 1.5 V VCC − 0.2 V Typ. VCC VCC VSS VSS Max VCC VCC Unit V VREFH VREFL VCC = 5 V ± 10% 1.6 1.0 0.02 ±1.0 ±1.0 2.0 1.5 5.0 ±3.0 ±5.0 mA µA LSB IREF = 3 V ± 10% V (VREFL = 0 V) CC VCC = 2.7~5.5 V − VCC = 5 V ± 10% VCC = 3 V ± 10% Note 1: 1LSB = (VREFH − VREFL)/210 [V] Note 2: Minimum operation frequency. The operation of the AD converter is guaranteed only when fc (High-frequency oscillator) is used. (It is not guaranteed when fs is used.) Additionally, it is guaranteed when the clock frequency which is selected by the clock gear is 4 MHz or more. Note 3: The value ICC includes the current which flows through the AVCC pin. 4.6 LCD Driver Characteristics Charge and Pump Characteristics Reference input voltage Output voltage V2 pin V3 pin External capacity C0, C1 V1 pin V2 pin V3 pin Symbol VL1 VL2 VL3 CPMP CVL1 CVL2 CVL3 Min 0.9 Typ. 2 × VL1 3 × VL1 Max 1.83 Unit V 0.1 0.1 0.1 0.1 1.0 1.0 1.0 1.0 µF Note: Output voltage and External capacity are not loaded. 93PW20A-22 2004-02-10 TMP93PW20A 4.7 Event Counter (TI0, TI2, TI4, TI6, TI8 to TIB) Parameter Clock cycle Low level clock pulse width High level clock pulse width Symbol tVCK tVCKL tVCKH Variable Min 8X + 100 4X + 40 4X + 40 12.5 MHz Min 740 360 360 20 MHz Min 500 240 240 Max Max Max Unit ns ns ns 4.8 Interrupt and Capture (1) NMI , INT0 to INT4 interrupts and INTKEY interrupt Parameter Low level pulse width High level pulse width Symbol tINTAL tINTAH Variable Min 4X 4X 12.5 MHz Min 320 320 20 MHz Min 200 200 Max Max Max Unit ns ns (2) INT7 to INTB interrupts and capture Parameter Low level pulse width High level pulse width Symbol tINTBL tINTBH Variable Min 4X + 100 4X + 100 12.5 MHz Min 420 420 20 MHz Min 300 300 Max Max Max Unit ns ns 4.9 SCOUT Pin AC Characteristics Parameter High level pulse width VCC = 5 V ± 10% High level pulse width VCC = 3 V ± 10% Low level pulse width VCC = 5 V ± 10% Low level pulse width VCC = 3 V ± 10% tSCL 0.5X − 20 20 − − tSCH 0.5X − 20 0.5X − 10 20 30 − 15 ns − Symbol Variable Min 0.5X − 10 12.5 MHz Min 30 20 MHz Min 15 Max Max Max Unit ns Measurement condition • Output level: High 2.2 V/Low 0.8 V, CL = 10 pF tSCH SCOUT tSCL 93PW20A-23 2004-02-10 TMP93PW20A 4.10 Timing Chart for Serial Bus Interface (1) I2C bus mode Parameter START instruction → SDA falling edge Start condition hold time SCL low level pulse width SCL high level pulse width Data hold time (Input) Data setup time (Input) Data hold time (Output) Data valid → SCL rising edge STOP instruction → SDA falling edge SDA falling edge → SCL rising edge Stop condition hold time Note: SBICR1 sets n. Symbol tGSTA tHD:STA tLOW tHIGH tHD:IDAT tSU:IDAT tHD:ODAT tODAT tFSDA tFDRC tSU:STO Variable Min 3X 2nX 2nX 2nX + 12X 0 250 7X 2nX − tHD:ODAT 3X 2nX 2nX + 16X 11X Typ. Max Unit s s s s ns ns s s s s s Start instruction SDA tGSTA SCL tHD:STA tHD:IDAT tHIGH tSU:IDAT tLOW tHD:ODAT tODAT Stop instruction tFSDA tFDRC tSU:STO 93PW20A-24 2004-02-10 TMP93PW20A (2) Clock-synchronous 8-bit SIO mode (Serial bus interface) clock 1. SCK input mode Parameter SCK cycle SCK falling edge → Output data hold Output data → SCK rising edge SCK rising edge → Input data hold Input data → SCK rising edge Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 6X tSCY2 − 6X 6X 0 Max Unit s s s ns ns 2. SCK output mode Parameter SCK cycle SCK falling edge → Output data hold Output data → SCK rising edge SCK rising edge → Input data hold Input data → SCK rising edge Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 2X tSCY2 − 2X 2X 0 Max 211X Unit s s s s ns tSCY2 SCK (Input/output mode) SO (Output mode) SI (Input mode) tOHS2 tOSS2 tISS2 tHSR2 93PW20A-25 2004-02-10 TMP93PW20A 4.11 Operation in PROM Mode (1) DC and AC characteristics in read operation Ta = 25 ± 5°C VCC = 5 V ± 10% Parameter VPP read voltage Input high voltage (A0 to A16, CE , OE , PGM ) Input low voltage (A0 to A16, CE , OE , PGM ) Address to output delay TCYC = 400 ns (10 MHz clock) α = 200 ns Symbol VPP VIH1 VIL1 tACC Condition − − − CL = 50 PF Min 4.5 2.2 −0.3 − Max 5.5 VCC + 0.3 0.8 2.25 TCYC + α Unit V ns A0 to A16 CE OE PGM D0 to D7 tACC Data output 93PW20A-26 2004-02-10 TMP93PW20A (2) DC and AC characteristics in programming Ta = 25 ± 5°C VCC = 6.25 V ± 0.25 V Parameter Programming supply voltage Input high voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Input low voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VCC supply current VPP supply current PGM program pulse width Symbol VPP VIH VIL ICC IPP tPW Condition − − − fc = 10 MHz VPP = 13.00 V CL = 50 PF Min 12.50 2.6 −0.3 − − 0.095 Typ. 12.75 Max 13.00 VCC + 0.3 0.8 50 50 Unit V mA ms 0.1 0.105 A0 to A16 CE OE D0 to D7 PGM Unknown Data in stable tPW Data out valid VPP Note 1: The power supply of VPP (12.75 V) must be turned on at the same time or the later time for a power supply of VCC and must be turned off at the same time or early time for a power supply of VCC. Note 2: The device suffers a damage taking out and putting in on the condition of VPP = 12.75 V. Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the programming. 93PW20A-27 2004-02-10 TMP93PW20A 5. Port Section Equivalent Circuit Diagram • Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. Stop: This signal becomes active 1 when the HALT mode setting register is set to the Stop mode and the CPU executes the HALT instruction. When the drive enable bit [DRVE] is set to 1, however, Stop remains at 0. • The input protection resistance ranges from several tens of ohms to several hundreds of ohms. ■ P0 (AD0 to AD7), P1 (AD8 to AD15, A8 to A15), and P67 (TO1) VCC Output data P-ch Output enable STOP N-ch Input data I/O Input enable ■ P30 ( RD ) and P31 ( WR ) VCC Output data Output STOP 93PW20A-28 2004-02-10 TMP93PW20A ■ P2 (A16 to A23, A0 to A7), P32 (HWR), P72 (TO8), P73 (SCOUT), and P76 (TOA) VCC Output data VCC Output enable STOP Programmable pull-up resistance Input data I/O Input enable ■ P70 (TI8/INT8), P71 (TI9/INT9), P74 (TIA/INTA), and P75 (TIB/INTB) VCC Output data VCC Output enable STOP Programmable pull-up resistance Input data I/O INT8 to INTB TI8 to TIB Input enable ■ P33 to P36 (INT0 to INT3) VCC Output data VCC Output enable STOP Programmable pull-up resistance Input data I/O INT0 to INT3 Input enable 93PW20A-29 2004-02-10 TMP93PW20A ■ P4 (TIx, TOx, KEYx) and P77 ( NMI ) VCC Output data VCC Output enable STOP Programmable pull-up resistance Input data I/O Input enable TI4, TI6 NMI , KEY0 to KEY7 ■ P37 (INT4/ ADTRG ) VCC Output data VCC Output enable STOP Programmable pull-up resistance Input data I/O Input enable AD trigger STOP INT4 ■ P5 (AN0 to AN7) Analog input channel select Analog data Input Input data Input enable 93PW20A-30 2004-02-10 TMP93PW20A ■ P63 (TXD0), P80 (TXD1), P83 (TO3), and P85 VCC Output data Open-drain output enable Output enable STOP Input data I/O Input enable ■ P60 (SCK), P64 (RXD0), P65 (SCLK0), and P66 (TI0/INT7) VCC Output P-ch Output enable STOP N-ch Input data I/O SCK RXD0 SCLK0 TI0 INT7 Input enable 93PW20A-31 2004-02-10 TMP93PW20A ■ P61 (SO/SDA), P62 (SI/SCL), P81 (RXD1), P82 (TI2), and P84 ( WAIT ) VCC Output data Open-drain output enable Output enable STOP Input data I/O SDA SI SCL RXD1 TI2 WAIT Input enable ■ P86 (XT1) and P87 (XT2) Input enable Input data Output data Output enable Input data Output data Output enable STOP Low-frequency oscillation enable P86 (XT1) Clock Oscillator P87 (XT2) Input enable 93PW20A-32 2004-02-10 TMP93PW20A ■ P90 to P97 (SEG24 to SEG31), PA0 to PA7 (SEG32 to SEG39) Segment output Output data Output enable STOP Output ■ CLK VCC VCC Output enable Internal CLK P-ch Output STOP N-ch Internal reset Test circuit ■ VREFH and VREFL VREFON P-ch VREFH String resistance VREFL 93PW20A-33 2004-02-10 TMP93PW20A ■ EA Input data Input ■ ALE VCC Internal ALE P-ch Output N-ch Output enable ■ RESET Reset WDTOUT Reset enable Schmitt Input ■ X1 and X2 Clock Oscillator X2 P-ch N-ch High-frequency o cillation enable X1 93PW20A-34 2004-02-10 TMP93PW20A 6. Package Dimensions P-LQFP144-1616-0.40 Unit: mm 93PW20A-35 2004-02-10 TMP93PW20A 93PW20A-36 2004-02-10