TMPR3912

32-Bit TX System RISC TX39 Family TMPR3911/3912 MIPS16, application Specific Extensions and R3000A are a trademark of MIPS Technologies, Inc. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. The products described in this document contain components made in the United States and subject to export control of the U.S. authorities. Diversion contrary to the U.S. law is prohibited. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. The Toshiba products listed in this document are intended for usage in general electronics applications ( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document shall be made at the customer’s own risk. The products described in this document may include products subject to the foreign exchange and foreign trade laws. © 2003 TOSHIBA CORPORATION All Rights Reserved Preface Thank you for choosing Toshiba semiconductor products. This is the 2000 edition of the databook for the TMPR3911/12 32-bit TX System RISC microprocessor. This databook is designed to be easily understood by engineers who are designing the Toshiba TMPR3911/12 RISC microprocessor into their products for the first time. No special knowledge of this device is assumed – the contents includes basic information about the microprocessor and the application fields in which it is used. In addition, complete technical specifications are given, facilitating incorporation of the device into any given user application. Toshiba are continually updating technical publications. Any comments and suggestions regarding any Toshiba document are most welcome and will be taken into account when subsequent editions are prepared. To receive updates to the information in this databook, or for additional information about the products described in it, please contact your nearest Toshiba office or authorized Toshiba dealer. August 2003 Table of Contents Table of Contents Handling Precautions TMPR3911/12 1. TMPR3911/12 Overview ........................................................................................................................................1-1 1.1 1.2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 3.1 3.2 3.2.1 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 Overview ........................................................................................................................................................1-1 References ....................................................................................................................................................1-11 Overview ........................................................................................................................................................2-1 Pins .................................................................................................................................................................2-2 Memory Pins ...........................................................................................................................................2-2 Bus Arbitration Pins ................................................................................................................................2-6 Clock Pins ...............................................................................................................................................2-6 CHI Pins ..................................................................................................................................................2-7 IO Pins.....................................................................................................................................................2-7 Magicbus Pins .........................................................................................................................................2-8 Reset Pins ................................................................................................................................................2-8 Power Module Pins .................................................................................................................................2-9 SIB Pins.................................................................................................................................................2-10 SPI Pins .................................................................................................................................................2-11 UART and IR Pins.................................................................................................................................2-11 Video Pins .............................................................................................................................................2-12 Endian Pin .............................................................................................................................................2-13 Test Pins ................................................................................................................................................2-13 Spare Pins..............................................................................................................................................2-13 Power Supply Pins ................................................................................................................................2-13 2. Pin Descriptions ......................................................................................................................................................2-1 Pin Mode ......................................................................................................................................................2-14 Pin Assignment.............................................................................................................................................2-20 Pin assignment (in case of TMPR3912AU-92 and TMPR3912XB-92)................................................2-20 Pin Assignment (in case of TMPR3911BU) .........................................................................................2-23 Pin Assignment (in case of TMPR3911BXB).......................................................................................2-25 TMPR3911BU Pin Assignment ............................................................................................................2-27 TMPR3912AU-92.................................................................................................................................2-28 TMPR3911BXB Ball Assignment ........................................................................................................2-29 TMPR3912XB-92 .................................................................................................................................2-30 Overview ........................................................................................................................................................3-1 CPU Core........................................................................................................................................................3-2 Description ..............................................................................................................................................3-2 CPU Interface .................................................................................................................................................3-3 Block Diagram ........................................................................................................................................3-3 Write Buffer ............................................................................................................................................3-4 Interface Controller .................................................................................................................................3-4 DMA Arbitration.....................................................................................................................................3-6 CPU Stop Mode ......................................................................................................................................3-6 TLB .........................................................................................................................................................3-7 3. CPU Module............................................................................................................................................................3-1 4. BIU Module.............................................................................................................................................................4-1 i Table of Contents 4.1 4.1.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.4.4 4.4.5 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.3.1 5.3.2 6.1 6.1.1 6.2 6.2.1 Overview ........................................................................................................................................................4-1 Block Diagram ........................................................................................................................................4-2 Address Decoder.............................................................................................................................................4-3 System Address Map...............................................................................................................................4-3 Address Generation .................................................................................................................................4-5 Address Re-Mapper Logic ......................................................................................................................4-6 Chip Select Controller ....................................................................................................................................4-7 Description ..............................................................................................................................................4-7 Access Mapping ......................................................................................................................................4-8 CS3-CS0 and MCS3-MCS0 Timing .....................................................................................................4-17 Card 2 and Card 1 .................................................................................................................................4-20 CS0 Size Configuration.........................................................................................................................4-23 DRAM and SDRAM Controller ...................................................................................................................4-24 Memory Chips Supported .....................................................................................................................4-24 DRAM and SDRAM Configurations ....................................................................................................4-25 DRAM...................................................................................................................................................4-26 SDRAM.................................................................................................................................................4-29 Arbitration ....................................................................................................................................................4-32 Refresh Controller .................................................................................................................................4-32 External Bus Master ..............................................................................................................................4-32 Watch Dog Timer ..................................................................................................................................4-33 Memory Power Down ...........................................................................................................................4-33 Memory Connections ...................................................................................................................................4-35 BIU Registers ...............................................................................................................................................4-44 Memory Configuration 0 Register ........................................................................................................4-44 Memory Configuration 1 Register ........................................................................................................4-47 Memory Configuration 2 Register ........................................................................................................4-48 Memory Configuration 3 Register ........................................................................................................4-49 Memory Configuration 4 Register ........................................................................................................4-51 Memory Configuration 5 Register ........................................................................................................4-53 Memory Configuration 6 Register ........................................................................................................4-54 Memory Configuration 7 Register ........................................................................................................4-54 Memory Configuration 8 Register ........................................................................................................4-54 Overview ........................................................................................................................................................5-1 Implementation...............................................................................................................................................5-2 Block Diagram ........................................................................................................................................5-2 DMA Controller Description...................................................................................................................5-3 Address Decoder Description..................................................................................................................5-4 Internal Function Registers .....................................................................................................................5-5 SIU Registers..................................................................................................................................................5-7 SIU Test Register ....................................................................................................................................5-7 TMPR3911/12 Revision Register............................................................................................................5-7 Overview ........................................................................................................................................................6-1 Related Pins.............................................................................................................................................6-2 Implementation...............................................................................................................................................6-3 Block Diagram ........................................................................................................................................6-3 5. SIU Module .............................................................................................................................................................5-1 6. Clock Module ..........................................................................................................................................................6-1 ii Table of Contents 6.2.2 6.3 6.3.1 7.1 7.1.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 Clock Module Description ......................................................................................................................6-5 Clock Registers...............................................................................................................................................6-6 Clock Control Register............................................................................................................................6-6 Overview ........................................................................................................................................................7-1 Related Pins.............................................................................................................................................7-1 Interface Requirements...................................................................................................................................7-2 Frame Structure and Serial Timing .........................................................................................................7-2 Configurations.........................................................................................................................................7-7 Implementation...............................................................................................................................................7-8 Block Diagram ........................................................................................................................................7-8 Transmitter ..............................................................................................................................................7-9 Receiver...................................................................................................................................................7-9 Clock and Control Generation...............................................................................................................7-10 DMA Address Generation.....................................................................................................................7-12 Related Interrupts ..................................................................................................................................7-14 CHI Registers ...............................................................................................................................................7-15 CHI Control Register ............................................................................................................................7-15 CHI Pointer Enable Register .................................................................................................................7-18 CHI Receive Pointer A Register ...........................................................................................................7-20 CHI Receive Pointer B Register............................................................................................................7-21 CHI Transmit Pointer A Register ..........................................................................................................7-22 CHI Transmit Pointer B Register ..........................................................................................................7-23 CHI Size Register..................................................................................................................................7-24 CHI RX Start Register...........................................................................................................................7-25 CHI TX Start Register...........................................................................................................................7-25 CHI TX Holding Register .....................................................................................................................7-26 CHI RX Holding Register .....................................................................................................................7-26 7. CHI Module.............................................................................................................................................................7-1 8. Interrupt Module......................................................................................................................................................8-1 Overview ........................................................................................................................................................8-1 Implementation...............................................................................................................................................8-2 Block Diagram ........................................................................................................................................8-2 Interrupt Logic Description .....................................................................................................................8-3 Interrupt Registers ..........................................................................................................................................8-5 Interrupt Status 1 Register.......................................................................................................................8-5 Interrupt Status 2 Register.......................................................................................................................8-8 Interrupt Status 3 Register.....................................................................................................................8-11 Interrupt Status 4 Register.....................................................................................................................8-11 Interrupt Status 5 Register.....................................................................................................................8-12 Interrupt Status 6 Register.....................................................................................................................8-15 Clear Interrupt 1 Register ......................................................................................................................8-16 Clear Interrupt 2 Register ......................................................................................................................8-16 Clear Interrupt 3 Register ......................................................................................................................8-16 Clear Interrupt 4 Register ......................................................................................................................8-16 Clear Interrupt 5 Register ......................................................................................................................8-16 Enable Interrupt 1 Register....................................................................................................................8-16 Enable Interrupt 2 Register....................................................................................................................8-17 Enable Interrupt 3 Register....................................................................................................................8-17 iii Table of Contents 8.3.15 8.3.16 8.3.17 9.1 9.1.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 10.1 10.2 Enable Interrupt 4 Register....................................................................................................................8-17 Enable Interrupt 5 Register....................................................................................................................8-17 Enable Interrupt 6 Register....................................................................................................................8-18 9. I/O Module ..............................................................................................................................................................9-1 Overview ........................................................................................................................................................9-1 Related Pins.............................................................................................................................................9-1 Implementation...............................................................................................................................................9-2 Block Diagram ........................................................................................................................................9-2 General Purpose I/O Ports.......................................................................................................................9-4 Multi-function I/O Ports..........................................................................................................................9-5 Related Interrupts ....................................................................................................................................9-8 I/O Registers ...................................................................................................................................................9-9 I/O Control Register ................................................................................................................................9-9 MFIO Data Output Register ..................................................................................................................9-10 MFIO Direction Register ......................................................................................................................9-10 MFIO Data Input Register.....................................................................................................................9-10 MFIO Select Register............................................................................................................................9-11 I/O Power-Down Register .....................................................................................................................9-11 MFIO Power-Down Register ................................................................................................................9-11 Overview ......................................................................................................................................................10-1 Related Pins...........................................................................................................................................10-1 Requirements.........................................................................................................................................10-2 Implementation .....................................................................................................................................10-2 Block Diagram ......................................................................................................................................10-2 Functional Description ..........................................................................................................................10-3 Related Interrupts ..................................................................................................................................10-3 Requirements.........................................................................................................................................10-4 Block Diagram ......................................................................................................................................10-5 Requirements.........................................................................................................................................10-6 Block Diagram ......................................................................................................................................10-6 Functional Description ..........................................................................................................................10-7 Related Interrupts ..................................................................................................................................10-7 IR Control 1 Register ............................................................................................................................10-8 IR Control 2 Register ............................................................................................................................10-9 IR Holding Register ............................................................................................................................10-10 Consumer IR.................................................................................................................................................10-2 10. IR Module .............................................................................................................................................................10-1 10.1.1 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.3 10.3.1 10.3.2 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.5.1 10.5.2 10.5.3 11.1 11.2 Two-Way Communication Via IR ................................................................................................................10-4 Carrier Detect State Machine........................................................................................................................10-6 IR Registers ..................................................................................................................................................10-8 11. Magicbus Module..................................................................................................................................................11-1 Overview ......................................................................................................................................................11-1 Related Pins...........................................................................................................................................11-1 Timing Requirements ............................................................................................................................11-2 Data Formats .........................................................................................................................................11-2 Command Words...................................................................................................................................11-3 Interface Requirements.................................................................................................................................11-2 11.1.1 11.2.1 11.2.2 11.2.3 11.3 Implementation.............................................................................................................................................11-4 iv Table of Contents 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 12.1 Block Diagram ......................................................................................................................................11-4 Transmitter ............................................................................................................................................11-5 Receiver.................................................................................................................................................11-6 Control Logic ........................................................................................................................................11-7 DMA Address Generation.....................................................................................................................11-9 Related Interrupts ................................................................................................................................11-10 Magicbus Control 1 Register...............................................................................................................11-11 Magicbus Control 2 Register...............................................................................................................11-13 Magicbus DMA Control 1 Register ....................................................................................................11-14 Magicbus DMA Control 2 Register ....................................................................................................11-14 Magicbus DMA Count ........................................................................................................................11-14 Magicbus Transmit Holding Register..................................................................................................11-15 Magicbus Receive Holding Register ...................................................................................................11-15 Magicbus Registers.....................................................................................................................................11-11 12. Power Module .......................................................................................................................................................12-1 Overview ......................................................................................................................................................12-1 System Power Control Overview ..........................................................................................................12-1 Power State Transition Diagram............................................................................................................12-2 Power Supply Lines in the System........................................................................................................12-3 Related Pins...........................................................................................................................................12-4 Power On Reset.....................................................................................................................................12-5 The 1st Power Up...................................................................................................................................12-6 Power Down..........................................................................................................................................12-7 Power Up...............................................................................................................................................12-8 Stop CPU...............................................................................................................................................12-9 Forced Shutdown.................................................................................................................................12-10 Memory Power Down .........................................................................................................................12-10 Stop Timer...........................................................................................................................................12-10 Power Module Interrupts.....................................................................................................................12-11 Power Control Register .......................................................................................................................12-12 12.1.1 12.1.2 12.1.3 12.1.4 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.2.8 12.2.9 12.3 12.3.1 13.1 13.2 Description ...................................................................................................................................................12-5 Power Registers ..........................................................................................................................................12-12 13. SIB Module ...........................................................................................................................................................13-1 Overview ......................................................................................................................................................13-1 Related Pins...........................................................................................................................................13-2 Holding and Shift Registers ..................................................................................................................13-4 Clock and Sync Generation...................................................................................................................13-4 Frame Structure .....................................................................................................................................13-6 Timing Requirements ............................................................................................................................13-6 Configurations.......................................................................................................................................13-7 Sample Rates.........................................................................................................................................13-8 Enable/Disable Sequencing.................................................................................................................13-10 Data Formats .......................................................................................................................................13-11 Subframe Formats ...............................................................................................................................13-12 Block Diagram..............................................................................................................................................13-3 13.1.1 13.2.1 13.2.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.4 13.5 Interface Requirements.................................................................................................................................13-6 DMA Address Generation ..........................................................................................................................13-15 Related Interrupts .......................................................................................................................................13-17 v Table of Contents 13.6 SIB Registers ..............................................................................................................................................13-19 SIB Size Register ................................................................................................................................13-19 SIB Sound RX Start Register ..............................................................................................................13-19 SIB Sound TX Start Register ..............................................................................................................13-20 SIB Telecom RX Start Register...........................................................................................................13-20 SIB Telecom TX Start Register...........................................................................................................13-20 SIB Control Register ...........................................................................................................................13-21 SIB Sound TX Holding Register.........................................................................................................13-25 SIB Sound RX Holding Register.........................................................................................................13-25 SIB Telecom TX Holding Register .....................................................................................................13-25 13.6.1 13.6.2 13.6.3 13.6.4 13.6.5 13.6.6 13.6.7 13.6.8 13.6.9 13.6.10 SIB Telecom RX Holding Register .....................................................................................................13-26 13.6.11 SIB Subframe 0 Control Register........................................................................................................13-26 13.6.12 SIB Subframe 1 Control Register........................................................................................................13-26 13.6.13 SIB Subframe 0 Status Register ..........................................................................................................13-27 13.6.14 SIB Subframe 1 Status Register ..........................................................................................................13-27 13.6.15 SIB DMA Control Register.................................................................................................................13-27 14. SPI Module............................................................................................................................................................14-1 14.1 14.2 Overview ......................................................................................................................................................14-1 Related Pins...........................................................................................................................................14-1 Block Diagram ......................................................................................................................................14-2 Baud Rate Generator .............................................................................................................................14-2 Transmitter/Receiver .............................................................................................................................14-3 CLKPOL/PHAPOL...............................................................................................................................14-4 Inter Character Delay Counter ..............................................................................................................14-5 SPI Interrupts ........................................................................................................................................14-5 SPI Control Register..............................................................................................................................14-6 SPI Transmitter Holding Register .........................................................................................................14-7 SPI Receiver Holding Register..............................................................................................................14-8 Description ...................................................................................................................................................14-2 14.1.1 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.2.6 14.3 14.3.1 14.3.2 14.3.3 15.1 15.2 SPI Registers.................................................................................................................................................14-6 15. Timer Module........................................................................................................................................................15-1 Overview ......................................................................................................................................................15-1 Related Pins...........................................................................................................................................15-1 RTC Block Diagram..............................................................................................................................15-2 RTC Description....................................................................................................................................15-3 RTC Interrupts.......................................................................................................................................15-3 Periodic Timer Block Diagram..............................................................................................................15-4 Periodic Timer Description ...................................................................................................................15-4 Periodic Timer Interrupts ......................................................................................................................15-4 RTC Register .........................................................................................................................................15-5 Alarm Register ......................................................................................................................................15-5 Timer Control Register..........................................................................................................................15-6 Periodic Timer Register.........................................................................................................................15-7 RTC ..............................................................................................................................................................15-2 15.1.1 15.2.1 15.2.2 15.2.3 15.3 15.3.1 15.3.2 15.3.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 16.1 Periodic Timer ..............................................................................................................................................15-4 Timer Registers.............................................................................................................................................15-5 16. UART Module.......................................................................................................................................................16-1 Overview ......................................................................................................................................................16-1 vi Table of Contents 16.1.1 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.5 16.5.1 16.5.2 16.5.3 16.5.4 16.5.5 16.5.6 16.5.7 17.1 17.2 Related Pins...........................................................................................................................................16-1 Power On/Off ........................................................................................................................................16-2 Baud Rate and Communication Parameters ..........................................................................................16-2 Interrupt Operation................................................................................................................................16-3 DMA Operation ....................................................................................................................................16-5 Internal Loopback .................................................................................................................................16-6 Transmitter Pulse Output Operation......................................................................................................16-8 Transmitter Disable Operation ..............................................................................................................16-8 Transmitter BREAK Operation .............................................................................................................16-8 Transmitter Overrun ..............................................................................................................................16-8 Receiver BREAK Operation ...............................................................................................................16-10 Receiver Frame Error Condition .........................................................................................................16-10 Receiver Overrun Condition ...............................................................................................................16-10 Receiver Parity Error Condition..........................................................................................................16-10 Receiver Pulse Operation ....................................................................................................................16-10 UART Control 1 Register....................................................................................................................16-11 UART Control 2 Register....................................................................................................................16-14 UART DMA Control 1 Register .........................................................................................................16-14 UART DMA Control 2 Register .........................................................................................................16-14 UART DMA Count .............................................................................................................................16-15 UART Transmit Holding Register.......................................................................................................16-15 UART Receiver Holding Register.......................................................................................................16-15 Overall Operation .........................................................................................................................................16-2 Transmitter Operation...................................................................................................................................16-7 Receiver Operation .......................................................................................................................................16-9 UART Registers..........................................................................................................................................16-11 17. Video Module........................................................................................................................................................17-1 Overview ......................................................................................................................................................17-1 Related Pins...........................................................................................................................................17-1 Display Types........................................................................................................................................17-2 Timing Requirements ............................................................................................................................17-5 Block Diagram ......................................................................................................................................17-8 Video State Machine .............................................................................................................................17-9 Horizontal Counter..............................................................................................................................17-10 Line Counter........................................................................................................................................17-11 DMA Address Generation...................................................................................................................17-11 Video FIFO..........................................................................................................................................17-13 Gray Scale LUT ..................................................................................................................................17-14 Color LUT...........................................................................................................................................17-15 Dithering .............................................................................................................................................17-17 Interface Requirements.................................................................................................................................17-2 17.1.1 17.2.1 17.2.2 17.3 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 17.3.6 17.3.7 17.3.8 17.3.9 17.4 Implementation.............................................................................................................................................17-8 17.3.10 Related Interrupts ................................................................................................................................17-18 Video Registers...........................................................................................................................................17-19 Video Control 1 Register.....................................................................................................................17-19 Video Control 2 Register.....................................................................................................................17-21 Video Control 3 Register.....................................................................................................................17-21 Video Control 4 Register.....................................................................................................................17-22 17.4.1 17.4.2 17.4.3 17.4.4 vii Table of Contents 17.4.5 17.4.6 17.4.7 17.4.8 17.4.9 Video Control 5 Register.....................................................................................................................17-23 Video Control 6 Register.....................................................................................................................17-23 Video Control 7 Register.....................................................................................................................17-24 Video Control 8 Register.....................................................................................................................17-24 Video Control 9 Register.....................................................................................................................17-25 17.4.10 Video Control 10 Register...................................................................................................................17-26 17.4.11 Video Control 11 Register ...................................................................................................................17-26 17.4.12 Video Control 12 Register...................................................................................................................17-27 17.4.13 Video Control 13 Register...................................................................................................................17-27 17.4.14 Video Control 14 Register...................................................................................................................17-28 18. Electrical Characteristics .......................................................................................................................................18-1 18.1 Electrical Characteristics of TMPR3911BU/BXB .......................................................................................18-1 Absolute maximum ratings (TMPR3911BU/BXB) ..............................................................................18-1 Recommended operating conditions (TMPR3911BU/BXB) ................................................................18-1 DC characteristics (TMPR3911BU/BXB) ............................................................................................18-2 Crystal oscillator characteristics (TMPR3911BU/BXB).......................................................................18-3 TMPR3911BU/BXB Timing.................................................................................................................18-4 AC characteristics (TMPR3911BU/BXB) ............................................................................................18-5 Absolute maximum ratings (TMPR3912AU-92/XB-92) ....................................................................18-27 Recommended operating conditions (TMPR3912AU-92/XB-92) ......................................................18-27 DC characteristics (TMPR3912AU-92/XB-92) ..................................................................................18-28 Crystal oscillator characteristics (TMPR3912AU-92/XB-92) ............................................................18-29 Definition of AC specification (TMPR3912AU-92/XB-92) ...............................................................18-30 AC characteristics (TMPR3912AU-92/XB-92) ..................................................................................18-31 18.1.1 18.1.2 18.1.3 18.1.4 18.1.5 18.1.6 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 19.1 19.2 19.3 19.4 Electrical Characteristics of TMPR3912AU-92/XB-92 .............................................................................18-27 19. Package Dimension ...............................................................................................................................................19-1 TMPR3911BU..............................................................................................................................................19-1 TMPR3912AU-92 ........................................................................................................................................19-2 TMPR3912XB-92 ........................................................................................................................................19-3 TMPR3911BXB ...........................................................................................................................................19-4 Appendix A Differences among TMPR3911/12..........................................................................................................A-1 Appendix B Access Timing Chart ............................................................................................................................... B-1 viii Handling Precautions 1 Using Toshiba Semiconductors Safely 1. Using Toshiba Semiconductors Safely TOSHIBA are continually working to improve the quality and the reliability of their products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 1-1 1 Using Toshiba Semiconductors Safely 1-2 2 Safety Precautions 2. Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions. [Explanation of labels] Indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which if not avoided, may result in minor injury or moderate injury. [Explanation of graphic symbol] Graphic symbol Meaning Indicates that caution is required (laser beam is dangerous to eyes). 2-1 2 Safety Precautions 2.1 General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. Do not insert devices in the wrong orientation. Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode and resulting in injury. When power to a device is on, do not touch the device’s heat sink. Heat sinks become hot, so you may burn your hand. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to the pins of the device under test before powering it on. Otherwise, you may receive an electric shock causing injury. Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it. Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock. Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes. 2-2 2 Safety Precautions 2.2 2.2.1 Precautions Specific to Each Product Group Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and in the worst case may cause blindness. If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate type of laser protective glasses as stipulated by IEC standard IEC825-1. Ensure that the current flowing in an LED device does not exceed the device’s maximum rated current. This is particularly important for resin-packaged LED devices, as excessive current may cause the package resin to blow up, scattering resin fragments and causing injury. When testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the photocoupler. If you detect a leakage current of more than 100 µA, use the testing equipment to shut off the photocoupler’s supply voltage; otherwise a large short-circuit current will flow continuously, and the device may break down or burst into flames, resulting in fire or injury. When incorporating a visible semiconductor laser into a design, use the device’s internal photodetector or a separate photodetector to stabilize the laser’s radiant power so as to ensure that laser beams exceeding the laser’s rated radiant power cannot be emitted. If this stabilizing mechanism does not work and the rated radiant power is exceeded, the device may break down or the excessively powerful laser beams may cause injury. 2.2.2 Power devices Never touch a power device while it is powered on. Also, after turning off a power device, do not touch it until it has thoroughly discharged all remaining electrical charge. Touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or serious injury. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to the device under test before powering it on. When you have finished, discharge any electrical charge remaining in the device. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. 2-3 2 Safety Precautions Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or explode, resulting in fire or injury. Use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs. If the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device to catch fire or explode, resulting in fire or injury. When designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device catching fire or exploding. Flying shrapnel can cause injury. When conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the device. Otherwise you may sustain injury caused by the device catching fire or exploding. Make sure that all metal casings in your design are grounded to earth. Even in modules where a device’s electrodes and metal casing are insulated, capacitance in the module may cause the electrostatic potential in the casing to rise. Dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching it. When designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the device’s forward and reverse losses into account. The leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is used in an extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur. This may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user. A design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate while electricity is conducted to control circuits, so that the main circuit will become inactive. Malfunction of the device may cause serious accidents or injuries. When conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has cooled properly before handling it. Devices become hot when they are operated. Even after the power has been turned off, the device will retain residual heat which may cause a burn to anyone touching it. 2.2.3 Bipolar ICs (for use in automobiles) If your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to prevent negative current from flowing in. The load current generated by powering the device on and off may cause it to function erratically or to break down, which could in turn cause injury. Ensure that the power supply to any device which incorporates protective functions is stable. If the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly. If protective functions fail, the device may break down causing injury to the user. 2-4 3 General Safety Precautions and Usage Considerations 3. General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 3.1.1 From Incoming to Shipping Electrostatic discharge (ESD) When handling individual devices (which are not yet mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects which come into direct contact with devices should be made of anti-static materials and should be grounded to earth via an 0.5- to 1.0-MΩ protective resistor. Please follow the precautions described below; this is particularly important for devices which are marked “Be careful of static.”. (1) Work environment • When humidity in the working environment decreases, the human body and other insulators can easily become charged with static electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment, while also taking into account the fact that moisture-proof-packed products may absorb moisture after unpacking. • Be sure that all equipment, jigs and tools in the working area are grounded to earth. • Place a conductive mat over the floor of the work area, or take other appropriate measures, so that the floor surface is protected against static electricity and is grounded to earth. The surface resistivity should be 104 to 108 Ω/sq and the resistance between surface and ground, 7.5 × 105 to 108 Ω 108 Ω/sq, for a resistance between surface and ground of 7.5 × 105 to 108 Ω) . The purpose of this is to disperse static electricity on the surface (through resistive components) and ground it to earth. Workbench surfaces must not be constructed of low-resistance metallic materials that allow rapid static discharge when a charged device touches them directly. • Cover the workbench surface also with a conductive mat (with a surface resistivity of 104 to • Pay attention to the following points when using automatic equipment in your workplace: (a) When picking up ICs with a vacuum unit, use a conductive rubber fitting on the end of the pick-up wand to protect against electrostatic charge. (b) Minimize friction on IC package surfaces. If some rubbing is unavoidable due to the device’s mechanical structure, minimize the friction plane or use material with a small friction coefficient and low electrical resistance. Also, consider the use of an ionizer. (c) In sections which come into contact with device lead terminals, use a material which dissipates static electricity. (d) Ensure that no statically charged bodies (such as work clothes or the human body) touch the devices. 3-1 3 General Safety Precautions and Usage Considerations (e) Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not touch devices. (g) In processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions. • Make sure that CRT displays in the working area are protected against static charge, for example by a VDT filter. As much as possible, avoid turning displays on and off. Doing so can cause electrostatic induction in devices. • Keep track of charged potential in the working area by taking periodic measurements. • Ensure that work chairs are protected by an anti-static textile cover and are grounded to the floor surface by a grounding chain. (Suggested resistance between the seat surface and grounding chain is 7.5 × 105 to 1012Ω.) Ω/sq; suggested resistance between surface and ground is 7.5 × 105 to 108 Ω.) • Install anti-static mats on storage shelf surfaces. (Suggested surface resistivity is 104 to 108 • For transport and temporary storage of devices, use containers (boxes, jigs or bags) that are made of anti-static materials or materials which dissipate electrostatic charge. • Make sure that cart surfaces which come into contact with device packaging are made of materials which will conduct static electricity, and verify that they are grounded to the floor surface via a grounding chain. • In any location where the level of static electricity is to be closely controlled, the ground resistance level should be Class 3 or above. Use different ground wires for all items of equipment which may come into physical contact with devices. (2) Operating environment • Operators must wear anti-static clothing and conductive shoes (or a leg or heel strap). • Operators must wear a wrist strap grounded to earth via a resistor of about 1 MΩ. (6 V to 24 V). • Soldering irons must be grounded from iron tip to earth, and must be used only at low voltages • If the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in particular avoid metallic tweezers. If a charged device touches a low-resistance tool, rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pat to the tip, and connect it to a dedicated ground used especially for anti-static purposes (suggested resistance value: 104 to 108 Ω). CRT). • Do not place devices or their containers near sources of strong electrical fields (such as above a 3-2 3 General Safety Precautions and Usage Considerations • When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another. • Ensure, if possible, that any articles (such as clipboards) which are brought to any location where the level of static electricity must be closely controlled are constructed of anti-static materials. • In cases where the human body comes into direct contact with a device, be sure to wear antistatic finger covers or gloves (suggested resistance value: 108 Ω or less). • Equipment safety covers installed near devices should have resistance ratings of 109 Ω or less. • If a wrist strap cannot be used for some reason, and there is a possibility of imparting friction to devices, use an ionizer. • The transport film used in TCP products is manufactured from materials in which static charges tend to build up. When using these products, install an ionizer to prevent the film from being charged with static electricity. Also, ensure that no static electricity will be applied to the product’s copper foils by taking measures to prevent static occuring in the peripheral equipment. 3.1.2 Vibration, impact and stress Handle devices and packaging materials with care. To avoid damage to devices, do not toss or drop packages. Ensure that devices are not subjected to mechanical vibration or shock during transportation. Ceramic package devices and devices in canister-type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends. Vibration Plastic molded devices, on the other hand, have a relatively high level of resistance to vibration and mechanical shock because their bonding wires are enveloped and fixed in resin. However, when any device or package type is installed in target equipment, it is to some extent susceptible to wiring disconnections and other damage from vibration, shock and stressed solder junctions. Therefore when devices are incorporated into the design of equipment which will be subject to vibration, the structural design of the equipment must be thought out carefully. If a device is subjected to especially strong vibration, mechanical shock or stress, the package or the chip itself may crack. In products such as CCDs which incorporate window glass, this could cause surface flaws in the glass or cause the connection between the glass and the ceramic to separate. Furthermore, it is known that stress applied to a semiconductor device through the package changes the resistance characteristics of the chip because of piezoelectric effects. In analog circuit design attention must be paid to the problem of package stress as well as to the dangers of vibration and shock as described above. 3-3 3 General Safety Precautions and Usage Considerations 3.2 3.2.1 Storage General storage • Avoid storage locations where devices will be exposed to moisture or direct sunlight. • Follow the instructions printed on the device cartons regarding transportation and storage. • The storage area temperature should be kept within a Humidity: Temperature: temperature range of 5°C to 35°C, and relative humidity should be maintained at between 45% and 75%. • Do not store devices in the presence of harmful (especially corrosive) gases, or in dusty conditions. • Use storage areas where there is minimal temperature fluctuation. Rapid temperature changes can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. As a result, the solderability of the leads will be degraded. • When repacking devices, use anti-static containers. • Do not allow external forces or loads to be applied to devices while they are in storage. • If devices have been stored for more than two years, their electrical characteristics should be tested and their leads should be tested for ease of soldering before they are used. 3.2.2 Moisture-proof packing Moisture-proof packing should be handled with care. The handling procedure specified for each packing type should be followed scrupulously. If the proper procedures are not followed, the quality and reliability of devices may be degraded. This section describes general precautions for handling moisture-proof packing. Since the details may differ from device to device, refer also to the relevant individual datasheets or databook. (1) General precautions Follow the instructions printed on the device cartons regarding transportation and storage. • Do not drop or toss device packing. The laminated aluminum material in it can be rendered ineffective by rough handling. • The storage area temperature should be kept within a temperature range of 5°C to 30°C, and relative humidity should be maintained at 90% (max). Use devices within 12 months of the date marked on the package seal. 3-4 3 General Safety Precautions and Usage Considerations • If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture. Please refer to the table below. After the pack has been opened, use the devices in a 5°C to 30°C. 60% RH environment and within the effective usage period listed on the moisture-proof package. If the effective usage period has expired, or if the packing has been stored in a high-humidity environment, bake the devices at high temperature. Packing Tray Tube Tape Moisture removal If the packing bears the “Heatproof” marking or indicates the maximum temperature which it can withstand, bake at 125°C for 20 hours. (Some devices require a different procedure.) Transfer devices to trays bearing the “Heatproof” marking or indicating the temperature which they can withstand, or to aluminum tubes before baking at 125°C for 20 hours. Deviced packed on tape cannot be baked and must be used within the effective usage period after unpacking, as specified on the packing. • When baking devices, protect the devices from static electricity. • Moisture indicators can detect the approximate humidity level at a standard temperature of 25°C. 6-point indicators and 3-point indicators are currently in use, but eventually all indicators will be 3-point indicators. HUMIDITY INDICATOR 60% 50% DANGER IF PINK CHANGE DESICCANT 40% HUMIDITY INDICATOR 30% 40 DANGER IF PINK 20% 30 10% READ AT LAVENDER BETWEEN PINK & BLUE (a) 6-point indicator 20 READ AT LAVENDER BETWEEN PINK & BLUE (b) 3-point indicator Figure 1 Humidity indicator 3-5 3 General Safety Precautions and Usage Considerations 3.3 Design Care must be exercised in the design of electronic equipment to achieve the desired reliability. It is important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions, it is also important to consider the overall environment in which equipment will be used, including factors such as the ambient temperature, transient noise and voltage and current surges, as well as mounting conditions which affect device reliability. This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature) will be exceeded. A device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Although absolute maximum ratings differ from product to product, they essentially concern the voltage and current at each pin, the allowable power dissipation, and the junction and storage temperatures. If the voltage or current on any pin exceeds the absolute maximum rating, the device’s internal circuitry can become degraded. In the worst case, heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down. If storage or operating temperatures exceed rated values, the package seal can deteriorate or the wires can become disconnected due to the differences between the thermal expansion coefficients of the materials from which the device is constructed. 3.3.2 Recommended operating conditions The recommended operating conditions for each device are those necessary to guarantee that the device will operate as specified in the datasheet. If greater reliability is required, derate the device’s absolute maximum ratings for voltage, current, power and temperature before using it. 3.3.3 Derating When incorporating a device into your design, reduce its rated absolute maximum voltage, current, power dissipation and operating temperature in order to ensure high reliability. Since derating differs from application to application, refer to the technical datasheets available for the various devices used in your design. 3.3.4 Unused pins If unused pins are left open, some devices can exhibit input instability problems, resulting in malfunctions such as abrupt increase in current flow. Similarly, if the unused output pins on a device are connected to the power supply pin, the ground pin or to other output pins, the IC may malfunction or break down. Since the details regarding the handling of unused pins differ from device to device and from pin 3-6 3 General Safety Precautions and Usage Considerations to pin, please follow the instructions given in the relevant individual datasheets or databook. CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted supply current to flow. Therefore, ensure that the unused input pins of a device are connected to the power supply (Vcc) pin or ground (GND) pin of the same device. For details of what to do with the pins of heat sinks, refer to the relevant technical datasheet and databook. 3.3.5 Latch-up Latch-up is an abnormal condition inherent in CMOS devices, in which Vcc gets shorted to ground. This happens when a parasitic PN-PN junction (thyristor structure) internal to the CMOS chip is turned on, causing a large current of the order of several hundred mA or more to flow between Vcc and GND, eventually causing the device to break down. Latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the internal chip, or when the voltage on the Vcc (Vdd) pin exceeds its rated value, forcing the internal chip into a breakdown condition. Once the chip falls into the latch-up state, even though the excess voltage may have been applied only for an instant, the large current continues to flow between Vcc (Vdd) and GND (Vss). This causes the device to heat up and, in extreme cases, to emit gas fumes as well. To avoid this problem, observe the following precautions: (1) Do not allow voltage levels on the input and output pins either to rise above Vcc (Vdd) or to fall below GND (Vss). Also, follow any prescribed power-on sequence, so that power is applied gradually or in steps rather than abruptly. (2) Do not allow any abnormal noise signals to be applied to the device. (3) Set the voltage levels of unused input pins to Vcc (Vdd) or GND (Vss). (4) Do not connect output pins to one another. 3.3.6 Input/Output protection Wired-AND configurations, in which outputs are connected together, cannot be used, since this short-circuits the outputs. Outputs should, of course, never be connected to Vcc (Vdd) or GND (Vss). Furthermore, ICs with tri-state outputs can undergo performance degradation if a shorted output current is allowed to flow for an extended period of time. Therefore, when designing circuits, make sure that tri-state outputs will not be enabled simultaneously. 3.3.7 Load capacitance Some devices display increased delay times if the load capacitance is large. Also, large charging and discharging currents will flow in the device, causing noise. Furthermore, since outputs are shorted for a relatively long time, wiring can become fused. Consult the technical information for the device being used to determine the recommended load capacitance. 3-7 3 General Safety Precautions and Usage Considerations 3.3.8 Thermal design The failure rate of semiconductor devices is greatly increased as operating temperatures increase. As shown in Figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due to power dissipation in the device. Therefore, to achieve optimum reliability, observe the following precautions concerning thermal design: (1) Keep the ambient temperature (Ta) as low as possible. (2) If the device’s dynamic power dissipation is relatively large, select the most appropriate circuit board material, and consider the use of heat sinks or of forced air cooling. Such measures will help lower the thermal resistance of the package. (3) Derate the device’s absolute maximum ratings to minimize thermal stress from power dissipation. θja = θjc + θca θja = (Tj–Ta) / P θjc = (Tj–Tc) / P θca = (Tc–Ta) / P in which θja = thermal resistance between junction and surrounding air (°C/W) θjc = thermal resistance between junction and package surface, or internal thermal resistance (°C/W) θca = thermal resistance between package surface and surrounding air, or external thermal resistance (°C/W) Tj = junction temperature or chip temperature (°C) Tc = package surface temperature or case temperature (°C) Ta = ambient temperature (°C) P = power dissipation (W) Ta θca Tc θjc Tj Figure 2 Thermal resistance of package 3.3.9 Interfacing When connecting inputs and outputs between devices, make sure input voltage (VIL/VIH) and output voltage (VOL/VOH) levels are matched. Otherwise, the devices may malfunction. When connecting devices operating at different supply voltages, such as in a dual-power-supply system, be aware that erroneous power-on and power-off sequences can result in device breakdown. For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor. 3-8 3 General Safety Precautions and Usage Considerations 3.3.10 Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 Ω to 100 Ω.) For this reason, the impedance of power supply lines with respect to high frequencies must be kept low. This can be accomplished by using thick and short wiring for the Vcc (Vdd) and GND (Vss) lines and by installing decoupling capacitors (of approximately 0.01 µF to 1 µF capacitance) as high-frequency filters between Vcc (Vdd) and GND (Vss) at strategic locations on the printed circuit board. For low-frequency filtering, it is a good idea to install a 10- to 100-µF capacitor on the printed circuit board (one capacitor will suffice). If the capacitance is excessively large, however, (e.g. several thousand µF) latch-up can be a problem. Be sure to choose an appropriate capacitance value. An important point about wiring is that, in the case of high-speed logic ICs, noise is caused mainly by reflection and crosstalk, or by the power supply impedance. Reflections cause increased signal delay, ringing, overshoot and undershoot, thereby reducing the device’s safety margins with respect to noise. To prevent reflections, reduce the wiring length by increasing the device mounting density so as to lower the inductance (L) and capacitance (C) in the wiring. Extreme care must be taken, however, when taking this corrective measure, since it tends to cause crosstalk between the wires. In practice, there must be a trade-off between these two factors. 3.3.11 External noise Printed circuit boards with long I/O or signal pattern lines are vulnerable to induced noise or surges from outside sources. Consequently, malfunctions or breakdowns can result from overcurrent or overvoltage, depending on the types of device used. To protect against noise, lower the impedance of the pattern line or insert a noise-canceling circuit. Protective measures must also be taken against surges. Input/Output Signals For details of the appropriate protective measures for a particular device, consult the relevant databook. 3.3.12 Electromagnetic interference Widespread use of electrical and electronic equipment in recent years has brought with it radio and TV reception problems due to electromagnetic interference. To use the radio spectrum effectively and to maintain radio communications quality, each country has formulated regulations limiting the amount of electromagnetic interference which can be generated by individual products. Electromagnetic interference includes conduction noise propagated through power supply and telephone lines, and noise from direct electromagnetic waves radiated by equipment. Different measurement methods and corrective measures are used to assess and counteract each specific type of noise. Difficulties in controlling electromagnetic interference derive from the fact that there is no method available which allows designers to calculate, at the design stage, the strength of the electromagnetic waves which will emanate from each component in a piece of equipment. For this reason, it is only after the prototype equipment has been completed that the designer can take measurements using a dedicated instrument to determine the strength of electromagnetic interference waves. Yet it is possible during system design to incorporate some measures for the 3-9 3 General Safety Precautions and Usage Considerations prevention of electromagnetic interference, which can facilitate taking corrective measures once the design has been completed. These include installing shields and noise filters, and increasing the thickness of the power supply wiring patterns on the printed circuit board. One effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed. 3.3.13 Peripheral circuits In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device’s specifications. The following factors must be taken into account. (1) Inappropriate voltages or currents applied to a device’s input pins may cause it to operate erratically. Some devices contain pull-up or pull-down resistors. When designing your system, remember to take the effect of this on the voltage and current levels into account. (2) The output pins on a device have a predetermined external circuit drive capability. If this drive capability is greater than that required, either incorporate a compensating circuit into your design or carefully select suitable components for use in external circuits. 3.3.14 Safety standards Each country has safety standards which must be observed. These safety standards include requirements for quality assurance systems and design of device insulation. Such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards. 3.3.15 Other precautions (1) When designing a system, be sure to incorporate fail-safe and other appropriate measures according to the intended purpose of your system. Also, be sure to debug your system under actual board-mounted conditions. (2) If a plastic-package device is placed in a strong electric field, surface leakage may occur due to the charge-up phenomenon, resulting in device malfunction. In such cases take appropriate measures to prevent this problem, for example by protecting the package surface with a conductive shield. (3) With some microcomputers and MOS memory devices, caution is required when powering on or resetting the device. To ensure that your design does not violate device specifications, consult the relevant databook for each constituent device. (4) Ensure that no conductive material or object (such as a metal pin) can drop onto and short the leads of a device mounted on a printed circuit board. 3.4 3.4.1 Inspection, Testing and Evaluation Grounding Ground all measuring instruments, jigs, tools and soldering irons to earth. Electrical leakage may cause a device to break down or may result in electric shock. 3-10 3 General Safety Precautions and Usage Considerations 3.4.2 Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user. When conducting any kind of evaluation, inspection or testing using AC power with a peak voltage of 42.4 V or DC power exceeding 60 V, be sure to connect the electrodes or probes of the testing equipment to the device under test before powering it on. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. (1) Apply voltage to the test jig only after inserting the device securely into it. When applying or removing power, observe the relevant precautions, if any. (2) Make sure that the voltage applied to the device is off before removing the device from the test jig. Otherwise, the device may undergo performance degradation or be destroyed. (3) Make sure that no surge voltages from the measuring equipment are applied to the device. (4) The chips housed in tape carrier packages (TCPs) are bare chips and are therefore exposed. During inspection take care not to crack the chip or cause any flaws in it. Electrical contact may also cause a chip to become faulty. Therefore make sure that nothing comes into electrical contact with the chip. 3.5 Mounting There are essentially two main types of semiconductor device package: lead insertion and surface mount. During mounting on printed circuit boards, devices can become contaminated by flux or damaged by thermal stress from the soldering process. With surface-mount devices in particular, the most significant problem is thermal stress from solder reflow, when the entire package is subjected to heat. This section describes a recommended temperature profile for each mounting method, as well as general precautions which you should take when mounting devices on printed circuit boards. Note, however, that even for devices with the same package type, the appropriate mounting method varies according to the size of the chip and the size and shape of the lead frame. Therefore, please consult the relevant technical datasheet and databook. 3.5.1 Lead forming Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. Semiconductor devices must undergo a process in which the leads are cut and formed before the devices can be mounted on a printed circuit board. If undue stress is applied to the interior of a device during this process, mechanical breakdown or performance degradation can result. This is attributable primarily to differences between the stress on the device’s external leads and the stress on the internal leads. If the relative difference is great enough, the device’s internal leads, adhesive properties or sealant can be damaged. Observe these precautions during the leadforming process (this does not apply to surface-mount devices): 3-11 3 General Safety Precautions and Usage Considerations (1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) For the minimum clearance specification between a device and a printed circuit board, refer to the relevant device’s datasheet and databook. If necessary, achieve the required clearance by forming the device’s leads appropriately. Do not use the spacers which are used to raise devices above the surface of the printed circuit board during soldering to achieve clearance. These spacers normally continue to expand due to heat, even after the solder has begun to solidify; this applies severe stress to the device. (4) Observe the following precautions when forming the leads of a device prior to mounting. • Use a tool or jig to secure the lead at its base (where the lead meets the device package) while bending so as to avoid mechanical stress to the device. Also avoid bending or stretching device leads repeatedly. • Be careful not to damage the lead during lead forming. • Follow any other precautions described in the individual datasheets and databooks for each device and package type. 3.5.2 Socket mounting (1) When socket mounting devices on a printed circuit board, use sockets which match the inserted device’s package. (2) Use sockets whose contacts have the appropriate contact pressure. If the contact pressure is insufficient, the socket may not make a perfect contact when the device is repeatedly inserted and removed; if the pressure is excessively high, the device leads may be bent or damaged when they are inserted into or removed from the socket. (3) When soldering sockets to the printed circuit board, use sockets whose construction prevents flux from penetrating into the contacts or which allows flux to be completely cleaned off. (4) Make sure the coating agent applied to the printed circuit board for moisture-proofing purposes does not stick to the socket contacts. (5) If the device leads are severely bent by a socket as it is inserted or removed and you wish to repair the leads so as to continue using the device, make sure that this lead correction is only performed once. Do not use devices whose leads have been corrected more than once. (6) If the printed circuit board with the devices mounted on it will be subjected to vibration from external sources, use sockets which have a strong contact pressure so as to prevent the sockets and devices from vibrating relative to one another. 3.5.3 Soldering temperature profile The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used. 3-12 3 General Safety Precautions and Usage Considerations (1) Using a soldering iron Complete soldering within ten seconds for lead temperatures of up to 260°C, or within three seconds for lead temperatures of up to 350°C. (2) Using medium infrared ray reflow • Heating top and bottom with long or medium infrared rays is recommended (see Figure 3). Medium infrared ray heater (reflow) Product flow Long infrared ray heater (preheating) Figure 3 Heating top and bottom with long or medium infrared rays • Complete the infrared ray reflow process within 30 seconds at a package surface temperature of between 210°C and 240°C. • Refer to Figure 4 for an example of a good temperature profile for infrared or hot air reflow. (°C) 240 Package surface temperature 210 160 140 60-120 s 30 s or less Time (s) Figure 4 Sample temperature profile for infrared or hot air reflow (3) Using hot air reflow • Complete hot air reflow within 30 seconds at a package surface temperature of between 210°C and 240°C. • For an example of a recommended temperature profile, refer to Figure 4 above. (4) Using solder flow • Apply preheating for 60 to 120 seconds at a temperature of 150°C. • For lead insertion-type packages, complete solder flow within 10 seconds with the temperature at the stopper (or, if there is no stopper, at a location more than 1.5 mm from the body) which does not exceed 260°C. • For surface-mount packages, complete soldering within 5 seconds at a temperature of 250°C or 3-13 3 General Safety Precautions and Usage Considerations less in order to prevent thermal stress in the device. • Figure 5 shows an example of a recommended temperature profile for surface-mount packages using solder flow. (°C) 250 Package surface temperature 160 140 60-120 s 5s or less Time (s) Figure 5 Sample temperature profile for solder flow 3.5.4 Flux cleaning and ultrasonic cleaning (1) When cleaning circuit boards to remove flux, make sure that no residual reactive ions such as Na or Cl remain. Note that organic solvents react with water to generate hydrogen chloride and other corrosive gases which can degrade device performance. (2) Washing devices with water will not cause any problems. However, make sure that no reactive ions such as sodium and chlorine are left as a residue. Also, be sure to dry devices sufficiently after washing. (3) Do not rub device markings with a brush or with your hand during cleaning or while the devices are still wet from the cleaning agent. Doing so can rub off the markings. (4) The dip cleaning, shower cleaning and steam cleaning processes all involve the chemical action of a solvent. Use only recommended solvents for these cleaning methods. When immersing devices in a solvent or steam bath, make sure that the temperature of the liquid is 50°C or below, and that the circuit board is removed from the bath within one minute. (5) Ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a leadless chip carrier (LCC), pin grid array (PGA) or charge-coupled device (CCD), because the bonding wires can become disconnected due to resonance during the cleaning process. Even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion between the mold resin and the frame material. The following ultrasonic cleaning conditions are recommended: Frequency: 27 kHz ∼ 29 kHz Ultrasonic output power: 300 W or less (0.25 W/cm2 or less) Cleaning time: 30 seconds or less Suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that the ultrasonic vibrator does not come into direct contact with the circuit board or the device. 3-14 3 General Safety Precautions and Usage Considerations 3.5.5 No cleaning If analog devices or high-speed devices are used without being cleaned, flux residues may cause minute amounts of leakage between pins. Similarly, dew condensation, which occurs in environments containing residual chlorine when power to the device is on, may cause betweenlead leakage or migration. Therefore, Toshiba recommends that these devices be cleaned. However, if the flux used contains only a small amount of halogen (0.05W% or less), the devices may be used without cleaning without any problems. 3.5.6 Mounting tape carrier packages (TCPs) (1) When tape carrier packages (TCPs) are mounted, measures must be taken to prevent electrostatic breakdown of the devices. (2) If devices are being picked up from tape, or outer lead bonding (OLB) mounting is being carried out, consult the manufacturer of the insertion machine which is being used, in order to establish the optimum mounting conditions in advance and to avoid any possible hazards. (3) The base film, which is made of polyimide, is hard and thin. Be careful not to cut or scratch your hands or any objects while handling the tape. (4) When punching tape, try not to scatter broken pieces of tape too much. (5) Treat the extra film, reels and spacers left after punching as industrial waste, taking care not to destroy or pollute the environment. (6) Chips housed in tape carrier packages (TCPs) are bare chips and therefore have their reverse side exposed. To ensure that the chip will not be cracked during mounting, ensure that no mechanical shock is applied to the reverse side of the chip. Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand. 3.5.7 Mounting chips Devices delivered in chip form tend to degrade or break under external forces much more easily than plastic-packaged devices. Therefore, caution is required when handling this type of device. (1) Mount devices in a properly prepared environment so that chip surfaces will not be exposed to polluted ambient air or other polluted substances. (2) When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). (3) Make sure that PCBs (or any other kind of circuit board) on which chips are being mounted do not have any chemical residues on them (such as the chemicals which were used for etching the PCBs). (4) When mounting chips on a board, use the method of assembly that is most suitable for maintaining the appropriate electrical, thermal and mechanical properties of the semiconductor devices used. * For details of devices in chip form, refer to the relevant device’s individual datasheets. 3-15 3 General Safety Precautions and Usage Considerations 3.5.8 Circuit board coating When devices are to be used in equipment requiring a high degree of reliability or in extreme environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for protection. However, before doing so, you must carefully consider the possible stress and contamination effects that may result and then choose the coating resin which results in the minimum level of stress to the device. 3.5.9 Heat sinks (1) When attaching a heat sink to a device, be careful not to apply excessive force to the device in the process. (2) When attaching a device to a heat sink by fixing it at two or more locations, evenly tighten all the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely tightened). Finally, fully tighten all the screws up to the specified torque. (3) Drill holes for screws in the heat sink exactly as specified. Smooth the surface by removing burrs and protrusions or indentations which might interfere with the installation of any part of the device. (4) A coating of silicone compound can be applied between the heat sink and the device to improve heat conductivity. Be sure to apply the coating thinly and evenly; do not use too much. Also, be sure to use a non-volatile compound, as volatile compounds can crack after a time, causing the heat radiation properties of the heat sink to deteriorate. (5) If the device is housed in a plastic package, use caution when selecting the type of silicone compound to be applied between the heat sink and the device. With some types, the base oil separates and penetrates the plastic package, significantly reducing the useful life of the device. Two recommended silicone compounds in which base oil separation is not a problem are YG6260 from Toshiba Silicone. (6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you may sustain a burn. 3.5.10 Tightening torque (1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch devices. 3.5.11 Repeated device mounting and usage Do not remount or re-use devices which fall into the categories listed below; these devices may cause significant problems relating to performance and reliability. (1) Devices which have been removed from the board after soldering (2) Devices which have been inserted in the wrong orientation or which have had reverse current applied (3) Devices which have undergone lead forming more than once 3-16 3 General Safety Precautions and Usage Considerations 3.6 3.6.1 Protecting Devices in the Field Temperature Semiconductor devices are generally more sensitive to temperature than are other electronic components. The various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. It is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design. Note also that if a device is used above its maximum temperature rating, device deterioration is more rapid and it will reach the end of its usable life sooner than expected. 3.6.2 Humidity Resin-molded devices are sometimes improperly sealed. When these devices are used for an extended period of time in a high-humidity environment, moisture can penetrate into the device and cause chip degradation or malfunction. Furthermore, when devices are mounted on a regular printed circuit board, the impedance between wiring components can decrease under highhumidity conditions. In systems which require a high signal-source impedance, circuit board leakage or leakage between device lead pins can cause malfunctions. The application of a moisture-proof treatment to the device surface should be considered in this case. On the other hand, operation under low-humidity conditions can damage a device due to the occurrence of electrostatic discharge. Unless damp-proofing measures have been specifically taken, use devices only in environments with appropriate ambient moisture levels (i.e. within a relative humidity range of 40% to 60%). 3.6.3 Corrosive gases Corrosive gases can cause chemical reactions in devices, degrading device characteristics. For example, sulphur-bearing corrosive gases emanating from rubber placed near a device (accompanied by condensation under high-humidity conditions) can corrode a device’s leads. The resulting chemical reaction between leads forms foreign particles which can cause electrical leakage. 3.6.4 Radioactive and cosmic rays Most industrial and consumer semiconductor devices are not designed with protection against radioactive and cosmic rays. Devices used in aerospace equipment or in radioactive environments must therefore be shielded. 3.6.5 Strong electrical and magnetic fields Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. Failures have been reported in LSIs mounted near malfunctioning deflection yokes in TV sets. In such cases the device’s installation location must be changed or the device must be shielded against the electrical or magnetic field. Shielding against magnetism is especially necessary for devices used in an alternating magnetic field because of the electromotive forces generated in this type of environment. 3-17 3 General Safety Precautions and Usage Considerations 3.6.6 Interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps) Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases the device can malfunction. This is especially true for devices in which the internal chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. This problem is not limited to optical semiconductors and EPROMs. All types of device can be affected by light. 3.6.7 Dust and oil Just like corrosive gases, dust and oil can cause chemical reactions in devices, which will adversely affect a device’s electrical characteristics. To avoid this problem, do not use devices in dusty or oily environments. This is especially important for optical devices because dust and oil can affect a device’s optical characteristics as well as its physical integrity and the electrical performance factors mentioned above. 3.6.8 Fire Semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently. When this happens, some devices may generate poisonous gases. Devices should therefore never be used in close proximity to an open flame or a heat-generating body, or near flammable or combustible materials. 3.7 Disposal of Devices and Packing Materials When discarding unused devices and packing materials, follow all procedures specified by local regulations in order to protect the environment against contamination. 3-18 4 Precautions and Usage Considerations 4. Precautions and Usage Considerations This section describes matters specific to each product group which need to be taken into consideration when using devices. If the same item is described in Sections 3 and 4, the description in Section 4 takes precedence. 4.1 4.1.1 Microcontrollers Design (1) Using resonators which are not specifically recommended for use Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application. (2) Undefined functions In some microcontrollers certain instruction code values do not constitute valid processor instructions. Also, it is possible that the values of bits in registers will become undefined. Take care in your applications not to use invalid instructions or to let register bit values become undefined. 4-1 4 Precautions and Usage Considerations 4-2 TMPR3911/3912 Chapter 1 TMPR3911/12 Overview 1. 1.1 TMPR3911/12 Overview Overview The TMPR3911/12 is the single-chip, integrated digital ASSP for the Personal Digital Assistants (PDA). Figure 1.1.1 shows a block diagram of the overall PDA system. The TMPR3911/12 consists of the PDA system support logic, integrated with an embedded TX39/H Processor core designed by TOSHIBA. The TMPR3911/12 consists of a TX39/H Processor core with 4 Kbytes of instruction cache memory and 1 Kbyte of data cache memory, plus integrated functions for interfacing to numerous system components and external I/O modules. The TX39/H Processor core is also augmented with a single-cycle multiply/accumulate module to allow integrated DSP functions, such as a software modem for highperformance standard data and fax protocols. The TMPR3911/12 also contains multiple DMA channels and a high-performance and flexible Bus Interface Unit (BIU) for providing an efficient means for transferring data between external system memory, cache memory, the Processor core, and external I/O modules. The types of external memory devices supported include dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), Flash memory, readonly memory (ROM), and expansion cards (PCMCIA and/or MagicCard). The TMPR3911/12 also contains a System Interface Module (SIM) containing integrated functions for interfacing to numerous external I/O modules such as liquid crystal displays (LCD’s), the TC35143 (which handles most of the analog functions of the system, including sound and telecom codecs and touchscreen ADC), ISDN/high-speed serial, infrared, wireless peripherals, Magicbus, etc. Lastly, The TMPR3911/12 contains support for implementation of power management for PDA system, whereby various TMPR3911/12 internal modules and external subsystems can be individually (under software control) powered up and down. The TMPR3911/12 contains the following overall features: • high level of integration on a single chip, small board space, low pin count, low power, and high performance • Plastic LQFP208-pin package (TMPR3912AU-92) FBGA 217-pin package (TMPR3912XB-92) Plastic LQFP176-pin package (TMPR3911BU) FBGA177-pin package (TMPR3911BXB) 32-bit TX39/H Processor core, cache memory, multiply-accumulate module, multi-channel DMA controller, bus interface unit and memory controller, power management, and other peripheral subsystems all on a single integrated chip minimal number of inter-chip connections Maximum operation frequency: 58 MHz (TMPR3911BU and TMPR3911BXB) 92 MHz (TMPR3912AU-92 and XB-92) • • • • low power consumption • • • • entire TMPR3911/12 operation is 3.3 V (in case of TMPR3911BU/BXB, I/O: 3.3 V, internal: 2.6 V) real-time clock based on 32.768 kHz reference Processor core clock stop state for low standby current power-down modes for individual internal peripheral modules 1-1 Chapter 1 TMPR3911/12 Overview 1-2 PCMCIA Slots 32 kHz TMPR3911/12 Timers Real-time Clock Memory Protection PCMCIA/ ROM I/F (future option) MagicCard(s) DRAM/SDRAM Interface SYSCLK TX39/H Processor core I-Cache/RAM 1 to 64 Mbytes ROM 32-bit bus Serial I/F and Magicbus LCD Interface D-Cache/ RAM 1 to 16 (32) Mbytes (S)DRAM ID ROM LCD Power Supply AC Adapter Main Thermistor T Backup (Lithium) MagicBus Jack IR ISDN or other peripherals High speed serial port TC35143F (Analog Front End) 64-pin QFP 3.3 V Phone Jack Touchscreen (Resistive) DAA or RF Xceiver Figure 1.1.1 PDA Block Diagram 1-2 Chapter 1 TMPR3911/12 Overview Figure 1.1.2 shows a block diagram of the TMPR3911/12. The key functions and features for each TMPR3911/12 module are itemized below. Processor core Module • TX39/H Processor core • • • • • • full 32-bit operation (registers, instructions, addresses, etc.) 32 general purpose 32-bit registers; 32-bit program counter MIPS RISC Instruction Set Architecture (ISA) supported Translation Look-aside Buffer (TLB) (4K Page size, 32 entries) on-chip cache 4 Kbyte instruction cache (I-cache) • • • • • • • • • • • physical address tag and valid bit per cache line programmable burst size instruction streaming mode supported direct-mapped 1 Kbyte data cache (D-cache) physical address tag and valid bit per cache line programmable burst size write-through two-way set associative cache address snoop mode supported for DMA 4-level deep write buffer • high-speed multiplier/accumulator • • • on-chip hardware multiplier supports 32 × 32 multiplier operations, with 64-bit accumulator existing multiply instructions are enhanced and new multiply and add instructions are added to the R3000A instruction set to improve the performance of DSP applications • Processor core interface • handles data bus, address bus, and control interface between Processor core and rest of the TMPR3911/12 logic 1-3 Chapter 1 TMPR3911/12 Overview Bus Interface (BIU) Module (S) DRAM/PCMCIA/ROM I Cache 4 Kbyte Addr Tag Data Data Data to Memory Addr TX39/H Processor Core with TLB MAC Addr Control TX39/H Processor core D Cache 1 Kbyte System Interface Unit (SIU) Module Arbitration/DMA/Addr Decode Data to TC35143F SIB Module CHI Module Addr to high speed serial to IR to LCD Video Module IR Module to Magicbus Magicbus Module UART Module to UART (dual UART) to general purpose I/O IO Module SPI Module Timer Module (+RTC) Clock Module Interrupt Module System Interface Module (SIM) to power supply 32 kHz Power Module SYSCLK Figure 1.1.2 TMPR3911/12 Block Diagram 1-4 Chapter 1 TMPR3911/12 Overview BIU Module • system memory and the TMPR3911/12 Bus Interface Unit (BIU) • • • • supports up to 2 banks of physical memory supports self-refreshing DRAM and SDRAM programmable parameters for each bank of DRAM or SDRAM (row/column address configuration, refresh, burst modes, etc.) programmable chip select memory access • 4 programmable (size, wait states, burst mode control) memory device and general purpose chip selects • • • • • available for system ROM, SRAM, Flash available for external port expansion registers 4 programmable (wait states, burst mode control) MagicCard or general purpose chip selects the TMPR3911/12 provides the chip select and card detect signals supports card insertion/removal timeouts • supports up to 2 identical PCMCIA ports • • the TMPR3911/12 and the TC35143 provide the control signals and accepts the status signals appropriate connector keying and level-shifting buffers required for 3.3 V versus 5 V PCMCIA interface implementations SIU Module • • • multi-channel 32-bit DMA controller and System Interface Unit (SIU) independent DMA channels for video, Magicbus, SIB to/from TC35143 audio/telecom codecs, highspeed serial port, IR UART, and general purpose UART address decoding for submodules within System Interface Module (SIM) 1-5 Chapter 1 TMPR3911/12 Overview Clock Module • • • the TMPR3911/12 supports system-wide single crystal configuration, besides the 32 kHz RTC XTAL (reduces cost, power, and board space) common crystal rate divided to generate clock for CPU, video, sound, telecom, UARTs, etc. independent enabling or disabling of individual clocks under software control, for power management CHI Module • • • • • high-speed serial Concentration Highway Interface (CHI) contains logic for interfacing to external fullduplex serial time-division-multiplexed (TDM) communication peripherals supports ISDN line interface chips and other PCM/TDM serial devices CHI interface is programmable (number of channels, frame rate, bit rate, etc.) to provide support for a variety of formats supports data rates up to 4.096 Mbps independent DMA support for CHI receive and transmit Interrupt Module • • contains logic for individually enabling, reading, and clearing all TMPR3911/12 interrupt sources interrupts generated from internal TMPR3911/12 modules or from edge transitions on external signal pins 1-6 Chapter 1 TMPR3911/12 Overview I/O Module • • • contains support for reading and writing the 7 bi-directional general purpose I/O pins and the 32 bidirectional multi-function I/O pins each I/O port can generate a separate positive and negative edge interrupt independently configurable I/O ports allow the TMPR3911/12 to support a flexible and wide range of system applications and configurations IR Module • IR consumer mode • • • • • • • • • • • • • • allows control of consumer electronic devices such as stereos, TVs, VCRs, etc. programmable pulse parameters external analog LED circuitry IRDA communication mode allows communication with other IRDA devices such as FAX machines, copiers, printers, etc. supported by the UART module within the TMPR3911/12 external analog receiver preamplifier and LED circuitry data rate = up to 115 kbps at 1 meter supported by the UART module within the TMPR3911/12 external analog IR chip(s) perform frequency modulation to generate the desired IR communication mode protocol data rate = up to 36000 bps at 3 meters periodically enables IR receiver to check if a valid carrier is present IR FSK communication mode carrier detect state machine 1-7 Chapter 1 TMPR3911/12 Overview Magicbus Module • • • • synchronous, serial 2-wire (clock and data), half-duplex communications protocol supports low-cost, low-power peripherals supports maximum data rate of 14.75 Mbps DMA support for Magicbus receive and transmit Power Module • • • power-down modes for individual internal peripheral modules serial (SPI port) power supply control interface supported power management state machine has 3 states: RUNNING, DOZING and SLEEP SIB Module • • • • • • • • • • the TMPR3911/12 contains holding and shift registers to support the serial interface to the TC35143 ASIC and/or other optional codec devices interface compatible with slave mode 3 of the Crystal CS4216 codec synchronous, frame-based protocol the TMPR3911/12 always master source of clock and frame frequency and phase ; programmable clock frequency each SIB frame consists of 128 clock cycles, further divided into 2 subframes or words of 64 bits each (supports up to 2 devices simultaneously) independent DMA support for audio receive and transmit, telecom receive and transmit supports 8-bit or 16-bit mono telecom formats supports 8-bit or 16-bit mono or stereo audio formats independently programmable audio and telecom sample rates CPU read/write registers for subframe control and status 1-8 Chapter 1 TMPR3911/12 Overview SPI Module • • • • • provides interface to SPI peripherals and devices full-duplex, synchronous serial data transfers (data in, data out, and clock signals) the TMPR3911/12 supplies dedicated chip select and interrupt for an SPI interface serial power supply 8-bit or 16-bit data word lengths for the SPI interface programmable SPI baud rate Timer Module • • • • • Real Time Clock (RTC) and Timer 40-bit counter (30.517 µs granularity); maximum uninterrupted time = 388.36 days 40-bit alarm register (30.517 µs granularity) 16-bit periodic timer (0.868 µs granularity at SYSCLK = 75 MHz); maximum timeout = 56.8 ms interrupts on alarm, timer, and prior to RTC roll-over 1-9 Chapter 1 TMPR3911/12 Overview UART Module • • • • • 2 independent full-duplex UARTs programmable baud rate generator UARTB port used for serial control interface to external IR module UARTA port used for general purpose serial control interface UARTA and UARTB DMA support for receive and transmit Video Module • • • • • • • bit-mapped graphics supports monochrome, gray scale, or color modes time-based dithering algorithm for gray scale and color modes supports multiple screen sizes supports split and non-split displays variable size and relocatable video buffer DMA support for fetching image data from video buffer 1-10 Chapter 1 TMPR3911/12 Overview 1.2 References (1) MIPS RISC Architecture, Gerry Kane and Joe Heinrich, Prentice Hall, 1992 This book is a comprehensive reference for the MIPS RISC Instruction Set Architecture (ISA). This book also describes implementation-specific architectural features for each of the MIPS RISC processor families. This book includes descriptions of CPU architecture, memory management, cache architecture, instruction set summary, exception processing, floating-point unit, and assembly language programming. (2) PC Card Standard, Release 2.01, Personal Computer Memory Card International Association, November 1992 This document provides a description of the standard for PC Card interchangeability. This includes card and socket physical and mechanical specifications, connector pin description and electrical interface specifications, card data formats and header organization, and execute in place specifications. This is not a General Magic document, and availability of this document is controlled by the Personal Computer Memory Card International Association. (3) TX39 Family Users Manual, TOSHIBA (4) Computer Architecture: A Quantitative Approach Second Edition John L Hennessy & David A Patterson Morgan Kaufmann Publishers, Inc. ISBN 1-55860-329-8 (5) See MIPS Run Dominic Sweetman Morgan Kaufmann Publishers, Inc. ISBN 1-55860-410-3 (6) MIPS Technologies Inc. Publications http://www.mips.com/publications/ (7) SGI Document Archive ftp://sgigate.sgi.com/pub/doc/ 1-11 Chapter 1 TMPR3911/12 Overview 1-12 Chapter 2 Pin Descriptions 2. 2.1 Pin Descriptions Overview The TMPR3912 contains 208 pins (LQFP) or 217 pins (FBGA) consisting of input, output, bi-directional, and power and ground pins. The TMPR3911 contains 176 pins (LQFP) or 177 pins (FBGA) consisting of input, output, bi-directional, and power and ground pins. The only difference between TMPR3911 and TMPR3912 is pin counts of power and ground pins. These pins are used to support various functions. The following sections describe the function of each pin including any special power-down considerations for each pin. 2-1 Chapter 2 Pin Descriptions 2.2 Pins The TMPR3912 contains 137 signal pins, 3 spare pins, 34 power pins, and 34 ground pins. The TMPR3911 contains 137 signal pins, 3 spare pins, 19 power pins and 17 ground pins. Of the 137 signal pins, 32 of them are multi-function and can be independently programmed either as IO ports or for an alternate standard/normal function. As an IO port, any of these pins can be programmed as an input or output port, with the capability of generating a separate positive and negative edge interrupt. See Section 2.3 for a summary of the multi-function IO ports versus their standard functions. 2.2.1 Memory Pins D[31:0]: INPUT/OUTPUT These pins are the data bus signals for the system. These pins are normally outputs and only become inputs during reads, thus no resistors are required since the bus will only float for a short period of time during bus turn-around. For more information, See Section 4.3.2. A[12:0]: OUTPUT These pins are the address bus signals for the system. The address lines are multiplexed and can be connected directly to SDRAM and DRAM devices. To generate the full 26-bit address for static devices, an external latch must be used to latch the signals using the ALE signal. For static devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly connected from the TMPR3911/12’s address bus) are held afterward by the TMPR3911/12 for the remainder of the address bus cycle. ALE: OUTPUT This pin is used as the address latch enable signal to latch A[12:0] using an external latch, for generating the upper address bits 25:13. RD*: OUTPUT This pin is used as the read signal for static devices. This signal is asserted for reads from MCS3-0*, CS3-0*, CARD2CS* and CARD1CS* for memory and attribute space. 2-2 Chapter 2 Pin Descriptions WE*: OUTPUT This pin is used as the write signal for the system. This signal is asserted for writes to MCS3-0*, CS3-0*, CARD2CS* and CARD1CS* for memory and attribute space, and for writes to DRAM and SDRAM. CAS0* (WE0*): OUTPUT This pin is used as the CAS signal for SDRAMs, the CAS signal for D[7:0] for DRAMs, and the write enable signal for D[7:0] for static devices. CAS1* (WE1*): OUTPUT This pin is used as the CAS signal for D[15:8] for DRAMs and the write enable signal for D[15:8] for static devices. CAS2* (WE2*): OUTPUT This pin is used as the CAS signal for D[23:16] for DRAMs and the write enable signal for D[23:16] for static devices. Also used as the bank select signal for SDRAM (applies only to TMPR3912XB-92/AU-92) CAS3* (WE3*): OUTPUT This pin is used as the CAS signal for D[31:24] for DRAMs and the write enable signal for D[31:24] for static devices. RAS0*: OUTPUT This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs. RAS1* (DCS1*): OUTPUT This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1 DRAMs. DCS0*: OUTPUT This pin is used as the chip select signal for Bank0 SDRAMs. DCKE: OUTPUT This pin is used as the clock enable for SDRAMs. 2-3 Chapter 2 Pin Descriptions DCLKIN: INPUT This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data input when reading from SDRAM and DRAM devices. DCLKOUT: OUTPUT This pin is the clock for the SDRAMs. DQMH: OUTPUT This pin is the upper data mask for a 16-bit SDRAM configuration. DQML: OUTPUT This pin is the lower data mask for a 16-bit SDRAM or 8-bit SDRAM configuration. CS3-0*: OUTPUT These pins are the Chip Select 3 through 0 signals. They can be configured to support either 32bit or 16-bit ports. MCS3-0*: OUTPUT These pins are the MagicCard Chip Select 3 through 0 signals. They only support 16-bit ports. CARD2CSH*, L*: OUTPUT These pins are the Chip Select signals for PCMCIA card slot 2. CARD1CSH*, L*: OUTPUT These pins are the Chip Select signals for PCMCIA card slot 1. CARDREG*: OUTPUT This pin is the REG* signal for the PCMCIA cards. CARDIORD*: OUTPUT This pin is the IORD* signal for the PCMCIA IO cards. 2-4 Chapter 2 Pin Descriptions CARDIOWR*: OUTPUT This pin is the IOWR* signal for the PCMCIA IO cards. CARDDIR*: OUTPUT This pin is used to provide the direction control for bi-directional data buffers used for the PCMCIA slot(s). This signal will assert whenever CARD2CSH* or CARD2CSL* or CARD1CSH* or CARD1CSL* is asserted and a read transaction takes place. CARD2WAIT*: INPUT This pin is the card wait signal from PCMCIA card slot 2. CARD1WAIT*: INPUT This pin is the card wait signal from PCMCIA card slot 1. 2-5 Chapter 2 Pin Descriptions 2.2.2 Bus Arbitration Pins DREQ*: INPUT This pin is used to request external arbitration. The TMPR3911/12 memory transactions are halted and certain memory signals will be tri-stated when DGRNT* is asserted in order to allow an external master to access memory. DGRNT*: OUTPUT This pin is asserted in response to DREQ* to inform the external test logic or bus master that it can now begin to drive signals. 2.2.3 Clock Pins SYSCLKIN: INPUT This pin should be connected along with SYSCLKOUT to an external crystal which is the main TMPR3911/12 clock source. SYSCLKOUT: OUTPUT This pin should be connected along with SYSCLKIN to an external crystal which is the main TMPR3911/12 clock source. C32KIN: INPUT This pin along with C32KOUT should be connected to a 32.768 kHz crystal. C32KOUT: OUTPUT This pin along with C32KIN should be connected to a 32.768 kHz crystal. BC32K: OUTPUT This pin is a buffered output of the 32.768 kHz clock. 2-6 Chapter 2 Pin Descriptions 2.2.4 CHI Pins CHIFS: INPUT/OUTPUT This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes. As an output, this pin allows the TMPR3911/12 to be the master CHI sync source. As an input, this pin allows an external peripheral to be the master CHI sync source and the TMPR3911/12 CHI module will slave to this external sync. CHICLK: INPUT/OUTPUT This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output, this pin allows the TMPR3911/12 to be the master CHI clock source. As an input, this pin allows an external peripheral to be the master CHI clock source and the TMPR3911/12 CHI module will slave to this external clock. CHIDOUT: OUTPUT This pin is the CHI serial data output signal. CHIDIN: INPUT This pin is the CHI serial data input signal. 2.2.5 IO Pins IO[6:0]: INPUT/OUTPUT These pins are general purpose input/output ports. Each port can be independently programmed as an input or output port. Each port can generate a separate positive and negative edge interrupt. Each port can also be independently programmed to use a 16 to 24 ms debouncer. MFIO[1:0]: INPUT/OUTPUT These pins are multi-function input/output ports. Each port can be independently programmed as an input or output port, or can be programmed for multi-function use to support test signals (for debugging purposes only). Each port can generate a separate positive and negative edge interrupt. Note that 30 other multi-function pins are available for usage as multi-function input/output ports. These pins are named after their respective standard/normal function and are not listed here. 2-7 Chapter 2 Pin Descriptions 2.2.6 Magicbus Pins MBUSCLK: INPUT/OUTPUT This pin is the bi-directional Magicbus clock signal. MBUSCLK is an input signal whenever the TMPR3911/12 is in the slave mode and is an output signal whenever the TMPR3911/12 is in the master mode. MBUSDATA: INPUT/OUTPUT This pin is the bi-directional Magicbus data signal. MBUSDATA is an input signal whenever the TMPR3911/12 is in the slave mode and is an output signal whenever the TMPR3911/12 is in the master mode. MBUSINT: INPUT This pin is the Magicbus interrupt signal. This signal is used to interrupt the TMPR3911/12 whenever a peripheral has been attached to or detached from the bus, or whenever a peripheral has initiated an interrupt event. 2.2.7 Reset Pins CPURES*: INPUT This pin is used to reset the Processor core. This pin should be connected to a switch for initiating a reset in the event that a software problem might hang the Processor core. The pin should also be pulled up to VSTANDBY (external signal) through an external pull-up resistor. PON*: INPUT This pin serves as the Power On Reset signal for the TMPR3911/12. This signal must remain low when VSTANDBY (external signal) is asserted until VSTANDBY is stable. Once VSTANDBY is asserted, this signal should never go low unless all power is lost in the system. 2-8 Chapter 2 Pin Descriptions 2.2.8 Power Module Pins ONBUTN: INPUT Asserting this signal will cause PWRCS to be asserted if the PWROK signal is high. PWRCS: OUTPUT This signal is asserted automatically if the ONBUTN signal is asserted when the PWROK signal is high. Clearing the PWRCS bit in the Power Control Register by software deasserts this signal. PWROK: INPUT This pin should be asserted when the source of power is stable. When the PWROKNMI bit in the Interrupt Status 6 Register is set, the deassertion of the PWROK signal causes the NMI (Non Maskable Interrupt). PWRINT: INPUT The rising edge and falling edge of signal to this pin causes PWRINT interrupt request. VCC3: INPUT This pin should be asserted when the source of power for external circuit is stable. Asserting this pin starts oscillating the internal clock. For more details of these pins, see chapter 12. 2-9 Chapter 2 Pin Descriptions 2.2.9 SIB Pins SIBDIN: INPUT This pin is used for serial input to the SIB module. SIBDOUT: OUTPUT This pin is used for serial output from the SIB module. SIBSCLK: OUTPUT This pin is the clock for SIB interface. SIBSYNC: OUTPUT This pin is the frame synchronization signal for SIB interface. This frame sync is asserted for one clock cycle immediately before each frame starts and all devices connected to the SIB monitor SIBSYNC to determine when they should transmit or receive data. SIBIRQ: INPUT The rising edge and falling edge of signal to this pin causes SIBIRQ interrupt request. SIBMCLK: INPUT/OUTPUT This pin is the master clock source for the SIB module. 2-10 Chapter 2 Pin Descriptions 2.2.10 SPI Pins SPICLK: OUTPUT This pin is used to clock data in and out of the SPI slave device. SPIOUT: OUTPUT This pin contains the data that is shifted into the SPI slave device. SPIIN: INPUT This pin contains the data that is shifted out of the SPI slave device. 2.2.11 UART and IR Pins TXD: OUTPUT This pin is the UART transmit signal from the UARTA module. RXD: INPUT This pin is the UART receive signal to the UARTA module. IROUT: OUTPUT This pin is the UART transmit signal from the UARTB module or the Consumer IR output signal if Consumer IR mode is enabled. IRIN: INPUT This pin is the UART receive signal to the UARTB module. RXPWR: OUTPUT This pin is the receiver power output control signal to the external communication IR analog circuitry. CARDET: INPUT This pin is the carrier detect input signal from the external communication IR analog circuitry. 2-11 Chapter 2 Pin Descriptions 2.2.12 Video Pins FRAME: OUTPUT This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to return its pointers to the top of the display. The Video Module asserts FRAME after all the lines of the LCD have been shifted and transferred, producing a full frame of display. DF: OUTPUT This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected to a DC voltage, the DF signal is used by the LCD to alternate the polarity of the row and column voltages used to turn the pixels on and off. The DF signal can be configured to toggle on every frame or can be configured to toggle every programmable number of LOAD signals. LOAD: OUTPUT This pin is the line synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to transfer the contents of its horizontal line shift register to the LCD panel for display. The Video Module asserts LOAD after an entire horizontal line of data has been shifted into the LCD. CP: OUTPUT This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of CP and sampled by the LCD on the falling edge of CP. VDAT[3:0]: OUTPUT These pins are the data for the LCD. These signals are directly connected to the LCD for 4-bit non-split displays. For 4-bit split and 8-bit non-split displays, an external register is required to demultiplex the 4-bit data into the desired 8 parallel data lines needed for the LCD. DISPON: OUTPUT This pin is the display-on enable signal for the LCD. VIDDONE: OUTPUT This pin is used to externally synchronize events to periods when the video is not shifting. 2-12 Chapter 2 Pin Descriptions 2.2.13 Endian Pin ENDIAN: INPUT This pin is used to select the endianness. The high level input sets the endianness to the big endian. The low level input sets the endianness to the little endian. 2.2.14 Test Pins TESTAIU: INPUT If this pin is set to low during reset, ROM data bus width will be 16 bits wide. If this pin is set to high during reset, ROM data bus width will be 32 bits wide. When the DREQ* signal is asserted to request external arbitration, this pin must be set to low. TESTCPU: Connect to GND. TESTIN: Connect to GND. INPUT INPUT 2.2.15 Spare Pins NC3-1: NO CONNECT These pins are reserved for future use and should be left unconnected. 2.2.16 Power Supply Pins VDD: +3.3 V These pins are the power pins. (In case of TMRP3912AU-92 and TMRP3912XB-92) VSS: GND These pins are the ground pins for the TMPR3911/12. VDDH: +3.3 V These pins are the power pins for I/O. (In case of TMPR3911BU and TMPR3911BXB) VDDL: +2.6 V These pins are the power pins for internal logic. (In case of TMPR3911BU and TMPR3911BXB) VDD (PLL): +2.6 V These pins are the power pins for PLL. (In case of TMPR3911BU and TMPR3911BXB) VSS (PLL): GND These pins are the ground pins for PLL. (In case of TMPR3911BU and TMPR3911BXB) 2-13 Chapter 2 Pin Descriptions 2.3 Pin Mode This section contains tables summarizing various aspects of the pin usage for the TMPR3911/12. Table 2.3.1 lists the standard versus multi-function usage for each TMPR3911/12 pin, if applicable. The column showing the multi-function select indicates the corresponding bit in the MIOSEL register, as well as the default configuration of each multi-function pin during reset. The “Bus Arb State” column shows which pins are tri-stated whenever the DGRNT* signal is asserted in response to a DREQ* (external bus arbitration request). Table 2.3.1 TMPR3911/12 Standard and Multi-Function Pin Mode (1/3) standard function (I = input, O = output) D[31:0] (I/O) A[12:0] (I/O) ALE (O) RD* (O) WE* (O) CAS0* (O) CAS1* (O) CAS2* (O) CAS3* (O) RAS0* (O) RAS1* (O) DCS0* (O) DCKE (O) DCLKIN (I) DCLKOUT (O) DQMH (O) DQML (O) DREQ* (I) DGRNT* (O) SYSCLKIN (I) SYSCLKOUT (O) C32KIN (I) C32KOUT (O) BC32K (O) VDAT[3] (O) VDAT[2] (O) VDAT[1] (O) VDAT[0] (O) CP (O) LOAD (O) DF (O) FRAME (O) DISPON (O) PWRCS (O) PWRINT (I) TMPR3911/12 pin multi-function multi-function select 1 = multi-function mode 0 = standard function mode MIOSEL reset state – – – – – – – – – – – – – – – – – 0 0 – – – – 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – MIOSEL[27] MIOSEL[26] – – – – MIOSEL[25] – – – – – – – – – – – Bus Arb State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z – Hi-Z Hi-Z Hi-Z – – – – – – – – – – – – – – – – – – D[31:0] A[12:0] ALE RD* WE* CAS0* (WE0*) CAS1* (WE1*) CAS2* (WE2*) CAS3* (WE3*) RAS0* RAS1* (DCS1)* DCS0* DCKE DCLKIN DCLKOUT DQMH DQML DREQ* DGRNT* SYSCLKIN SYSCLKOUT C32KIN C32KOUT BC32K VDAT[3] VDAT[2] VDAT[1] VDAT[0] CP LOAD DF FRAME DISPON PWRCS PWRINT – – – – – – – – – – – – – – – – – MIO[27] MIO[26] – – – – MIO[25] – – – – – – – – – – – 2-14 Chapter 2 Pin Descriptions Table 2.3.2 TMPR3911/12 Standard and Multi-Function Pin Mode (2/3) standard function (I = input, O = output) PWROK (I) ONBUTN (I) CPURES* (I) PON* (I) MBUSCLK (I/O) MBUSDATA (I/O) MBUSINT (I) TXD (O) RXD (I) CS0* (O) CS1* (O) CS2* (O) CS3* (O) MCS0* (O) MCS1* (O) MCS2* (O) MCS3* (O) CHIFS (I/O) CHICLK (I/O) CHIDOUT (O) CHIDIN (I) VCC3 (I) IO6 (I/O) IO5 (I/O) IO4 (I/O) IO3 (I/O) IO2 (I/O) IO1 (I/O) IO0 (I/O) SPICLK (O) SPIOUT (O) SPIIN (I) SIBSYNC (O) SIBDOUT (O) SIBDIN (I) SIBMCLK (I/O) SIBSCLK (O) SIBIRQ (I) RXPWR (O) CARDET (I) IROUT (O) IRIN (I) TESTAIU (I) TESTCPU (I) TESTIN (I) VIDDONE (O) TMPR3911/12 pin multi-function multi-function select 1 = multi-function mode 0 = standard function mode MIOSEL reset state – – – – – – – 0 0 0 0 0 1 1 1 1 1 1 1 1 – – – – – – – – 0 0 0 – – – 0 – – – – – – – – – – – – – – – – – MIOSEL[24] MIOSEL[23] – MIOSEL[22] MIOSEL[21] MIOSEL[20] MIOSEL[19] MIOSEL[18] MIOSEL[17] MIOSEL[16] MIOSEL[31] MIOSEL[30] MIOSEL[29] MIOSEL[28] – – – – – – – – MIOSEL[15] MIOSEL[14] MIOSEL[13] – – – MIOSEL[12] – – – – – – – – – – Bus Arb State – – – – – – – – – Hi-Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – PWROK ONBUTN CPURES* PON* MBUSCLK MBUSDATA MBUSINT TXD RXD CS0* CS1* CS2* CS3* MCS0* MCS1* MCS2* MCS3* CHIFS CHICLK CHIDOUT CHIDIN VCC3 IO6 IO5 IO4 IO3 IO2 IO1 IO0 SPICLK SPIOUT SPIIN SIBSYNC SIBDOUT SIBDIN SIBMCLK SIBSCLK SIBIRQ RXPWR CARDET IROUT IRIN TESTAIU TESTCPU TESTIN VIDDONE – – – – – – – MIO[24] MIO[23] – MIO[22] MIO[21] MIO[20] MIO[19] MIO[18] MIO[17] MIO[16] MIO[31] MIO[30] MIO[29] MIO[28] – – – – – – – – MIO[15] MIO[14] MIO[13] – – – MIO[12] – – – – – – – – – – 2-15 Chapter 2 Pin Descriptions Table 2.3.3 TMPR3911/12 Standard and Multi-Function Pin Mode (3/3) standard function (I = input, O = output) CARDREG* (O) (SHOWDINO CS*) CARDIOWR* (O) CARDIORD* (O) CARD1CSL* (O) CARD1CSH* (O) CARD2CSL* (O) CARD2CSH* (O) CARD1WAIT* (I) CARD2WAIT* (I) CARDDIR* (O) reserved reserved ENDIAN (I) SPARE +3.3 V (*1) GND +3.3 V (*2) +2.6 V (*2) TMPR3911/12 pin multi-function multi-function select 1 = multi-function mode 0 = standard function mode MIOSEL reset state 1 1 1 1 1 1 1 1 1 1 1 1 – – – – – – Bus Arb State CARDREG* CARDIOWR* CARDIORD* CARD1CSL* CARD1CSH CARD2CSL* CARD2CSH* CARD1WAIT* CARD2WAIT* CARDDIR* MFIO[1] MFIO[0] ENDIAN NC[3:1] VDD VSS VDDH VDDL MIO[11] MIO[10] MIO[9] MIO[8] MIO[7] MIO[6] MIO[5] MIO[4] MIO[3] MIO[2] MIO[1] MIO[0] – – – – – – MIOSEL[11] MIOSEL[10] MIOSEL[9] MIOSEL[8] MIOSEL[7] MIOSEL[6] MIOSEL[5] MIOSEL[4] MIOSEL[3] MIOSEL[2] MIOSEL[1] MIOSEL[0] – – – – – – – – – – – – – – – – – – – – – – – – *1) In case of TMPR3912AU-92 and TMPR3912XB-92 *2) In case of TMPR3911BU and MTPR3911BXB 2-16 Chapter 2 Pin Descriptions Table 2.3.4 lists various power-down states and conditions for each TMPR3911/12 pin. The “Power-Down Control” column shows the conditions which trigger a power-down for each respective pin. This column also shows the reset state for each of these conditions. The “PON* state” column defines the state of each pin at power-on reset (PON*). This condition is defined as initial power up of the TMPR3911/12. This state is entered after power is applied for the very first time (VSTANDBY is turned on but VCC3 is still turned off). See figure 12.2.2. The “1st-time power-up state” column defines the state of each pin after power-up. This mode is defined as VCC3 applied to the entire system and is initiated by the user pressing the ONBUTN while in the poweron reset (PON*) state. See figure 12.2.2. The “power-down state” column defines the state of each pin during power-down mode. Table 2.3.4 TMPR3911/12 Power-Down Pin Mode (1/3) TMPR3911/12 pin D[31:0] A[12:0] ALE RD* WE* CAS0* (WE0*) CAS1* (WE1*) CAS2* (WE2*) CAS3* (WE3*) RAS0* RAS1* (DCS1*) DCS0* DCKE DCLKIN* DCLKOUT DQMH DQML DREQ DGRNT* SYSCLKIN SYSCLKOUT C32KIN C32KOUT BC32K VDAT[3] VDAT[2] VDAT[1] VDAT[0] PON* state LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW IN LOW LOW LOW PULL-DOWN LOW OSC OFF OSC OFF OSC ON OSC ON PULL-DOWN LOW LOW LOW LOW 1st time power-up state LOW LOW LOW HI LOW LOW LOW LOW LOW LOW LOW LOW LOW IN LOW LOW LOW IN HI OSC ON OSC ON OSC ON OSC ON IN LOW LOW LOW LOW power-down state LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW IN LOW LOW LOW SELECTABLE SELECTABLE OSC OFF OSC OFF OSC ON OSC ON SELECTABLE LOW LOW LOW LOW Power-Down Control MEMPOWERDOWN MEMPOWERDOWN X POWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN X MEMPOWERDOWN MEMPOWERDOWN MEMPOWERDOWN POWERDOWN & MIOPD[27] POWERDOWN & MIOPD[26] POWERDOWN POWERDOWN X X POWERDOWN & MIOPD[25] video module disabled video module disabled video module disabled video module disabled POWERDOWN = (VCCON & VCC3)* VCCON: a bit in the Power Control Register. VCC3: an input signal. MEMPOWERDOWN: a bit in the Memory Configration 4 Register. SELECTABLE: See Table 9.2.2 and 9.2.3. 2-17 Chapter 2 Pin Descriptions Table 2.3.5 TMPR3911/12 Power-Down Pin Mode (2/3) TMPR3911/12 pin CP LOAD DF FRAME DISPON PWRCS PWRINT PWROK ONBUTN CPURES* PON* MBUSCLK MBUSDATA MBUSINT TXD RXD CS0* CS1* CS2* CS3* MCS0* MCS1* MCS2* MCS3* CHIFS CHICLK CHIDOUT CHIDIN VCC3 IO6 IO5 IO4 IO3 IO2 IO1 IO0 SPICLK SPIOUT SPIIN SIBYNC SIBDOUT SIBDIN SIBMCLK SIBSCLK SIBIRQ PON* state LOW LOW LOW LOW LOW LOW IN IN IN IN IN LOW LOW IN LOW PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN LOW LOW PULL-DOWN LOW LOW PULL-DOWN PULL-DOWN LOW PULL-DOWN 1st time power-up state LOW LOW LOW LOW LOW HI IN IN IN IN IN LOW LOW IN LOW IN HI HI HI HI IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN LOW LOW IN LOW LOW IN IN LOW IN power-down state LOW LOW LOW LOW LOW LOW IN IN IN IN IN LOW LOW IN SELECTABLE SELECTABLE PULL-DOWN SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE PULL-DOWN SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE LOW LOW PULL-DOWN SELECTABLE LOW PULL-DOWN Power-Down Control video module disabled video module disabled video module disabled video module disabled video module disabled X X X X X X magicbus module disabled magicbus module disabled X POWERDOWN & MIOPD[24] POWERDOWN & MIOPD[23] POWERDOWN POWERDOWN & MIOPD[22] POWERDOWN & MIOPD[21] POWERDOWN & MIOPD[20] POWERDOWN & MIOPD[19] POWERDOWN & MIOPD[18] POWERDOWN & MIOPD[17] POWERDOWN & MIOPD[16] POWERDOWN & MIOPD[31] POWERDOWN & MIOPD[30] POWERDOWN & MIOPD[29] POWERDOWN & MIOPD[28] POWERDOWN POWERDOWN & IOPD[6] POWERDOWN & IOPD[5] POWERDOWN & IOPD[4] POWERDOWN & IOPD[3] POWERDOWN & IOPD[2] POWERDOWN & IOPD[1] POWERDOWN & IOPD[0] POWERDOWN & MIOPD[15] POWERDOWN & MIOPD[14] POWERDOWN & MIOPD[13] POWERDOWN POWERDOWN POWERDOWN POWERDOWN & MIOPD[12] POWERDOWN POWERDOWN POWERDOWN = (VCCON & VCC3)* VCCON: a bit in the Power Control Register. VCC3: an input signal. MEMPOWERDOWN: a bit in the Memory Configration 4 Register. SELECTABLE: See Table 9.2.2 and 9.2.3. 2-18 Chapter 2 Pin Descriptions Table 2.3.6 TMPR3911/12 Power-Down Pin Mode (3/3) TMPR3911/12 pin RXPWR CARDET IROUT IRIN TESTAIU TESTCPU TESTIN VIDDONE CARDREG* CARDIOWR* CARDIORD* CARD1CSL* CARD1CSH* CARD2CSL* CARD2CSH* CARD1WAIT* CARD2WAIT* CARDDIR* MFIO[1] MFIO[0] ENDIAN NC[3:1] VDD 19EACH/34EACH VSS 17EACH/34EACH PON* state LOW PULL-DOWN LOW PULL-DOWN IN IN IN LOW PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN IN IN IN X X X 1st time power-up state LOW IN LOW IN IN IN IN LOW IN IN IN IN IN IN IN IN IN IN IN IN IN X X X power-down state LOW PULL-DOWN LOW PULL-DOWN IN IN IN LOW SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE SELECTABLE IN X X X Power-Down Control POWERDOWN POWERDOWN POWERDOWN POWERDOWN X X X X POWERDOWN & MIOPD[11] POWERDOWN & MIOPD[10] POWERDOWN & MIOPD[9] POWERDOWN & MIOPD[8] POWERDOWN & MIOPD[7] POWERDOWN & MIOPD[6] POWERDOWN & MIOPD[5] POWERDOWN & MIOPD[4] POWERDOWN & MIOPD[3] POWERDOWN & MIOPD[2] POWERDOWN & MIOPD[1] POWERDOWN & MIOPD[0] X X X X POWERDOWN = (VCCON & VCC3)* VCCON: a bit in the Power Control Register. VCC3: an input signal. MEMPOWERDOWN: a bit in the Memory Configration 4 Register. SELECTABLE: See Table 9.2.2 and 9.2.3. 2-19 Chapter 2 Pin Descriptions 2.4 Pin Assignment Pin assignment (in case of TMPR3912AU-92 and TMPR3912XB-92) Table 2.4.1 Pin Assignment (1/3) LQFP NO. FBGA (TMPR3912) NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 A1 C3 E5 B1 C2 E4 C1 D3 D2 F5 D1 E3 E2 F4 E1 F3 F2 G5 F1 G4 G3 G2 G1 G6 H6 H3 H1 H2 H4 J6 J1 J2 J3 J4 J5 K1 K2 K3 K4 L1 L2 L3 K5 M1 2.4.1 I/O  I/O  I/O I/O  I/O  I/O  I/O I/O  I/O  I/O  I/O I/O  I/O  I/O I/O  I/O I/O  I I/O I I/O  I/O   O  O O I O  I Signal Name VDD D[0] (D[24]) VSS D[1] (D[25]) D[2] (D[26]) VDD D[3] (D[27]) VSS D[4] (D[28]) VDD D[5] (D[29]) D[6] (D[30]) VSS D[7] (D[31]) VSS D[8] (D[16]) VDD D[9] (D[17]) D[10] (D[18]) VSS D[11] (D[19]) VDD D[12] (D[20]) D[13] (D[21]) VSS D[14] (D[22]) D[15] (D[23]) VDD ENDIAN MIOX[1] MBUSINT MBUSDATA VSS MBUSCLK VDD VDD SIBMCLK VSS SIBSCLK SIBSYNC SIBDIN SIBDOUT VDD SIBIRQ LQFP NO. FBGA (TMPR3912) NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 M9 L9 R10 M5 R3 N4 P4 L6 R4 N5 P5 M6 R5 N6 P6 L7 R6 M7 N7 P7 R7 K7 L8 N8 R8 P8 M8 K9 R9 P9 M2 M3 L4 N1 N2 M4 P2 P1 R1 N3 L5 R2 I/O I/O I/O I/O  I/O I/O I O  I O I/O  I O   I O I/O I/O  O I O  I I O I  I O  I O  O I I  I I I Signal Name MIOX[0] IO[6] IO[5] VSS CHICLK CHIFS CHIDIN CHIDOUT VDD RXD TXD IO[4] NC IRIN IROUT VSS VDD CARDET RXPWR IO[3] IO[2] VSS SPICLK SPIIN SPIOUT VDD TESTCPU TESTIN VIDDONE TESTAIU VSS VCC3 BC32K VDD C32KlN C32KOUT VSS PWRCS PWRlNT PWROK NC ONBUTN PON* CPURES* (1) * Active-low signal (2) (3) ( ) indicates the signal name in the little endian mode The signal name change regarding DQMH/L is applied only to TMPR3912AU-92. 2-20 Chapter 2 Pin Descriptions Table 2.4.2 Pin Assignment (2/3) LQFP NO. FBGA (TMPR3912) NO. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 P10 N10 M10 R11 P11 N11 L10 R12 P12 N12 M11 R13 P13 M12 P14 R14 R15 N13 L11 P15 N14 L12 N15 M13 M14 K11 M15 L13 L14 K12 L15 K13 K14 J11 K15 J12 J13 J14 J15 J10 H11 H13 H15 H14 H12 G10 G15 G14 I/O Signal Name  O O  O O O   O O O O  I/O  I O O I/O  O O O I  O  O O  O O O O O O O  I O    I/O I/O  I/O VDD DISPON FRAME VSS DF LOAD CP VSS VDD VDAT[0] VDAT[1] VDAT[2] VDAT[3] VSS IO[1] VDD CARD2WAIT* CARD2CSH* CARD2CSL* IO[0] VSS (PLL) CARDIORD* CARDIOWR* CARDREG* CARD1WAIT* VDD (PLL) CARDDIR* VDD CARD1CSL* CARD1CSH* VSS MCS3* MCS2* MCS1* MCS0* CS3* CS2* CS1* VDD SYSCLKIN SYSCLKOUT VSS VSS VDD D[31] (D[7]) D[30] (D[6]) VSS D[29] (D[5]) LQFP NO. FBGA (TMPR3912) NO. 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 D11 A13 C12 B12 E10 A12 C11 B11 D10 A11 C10 B10 E9 A10 D9 C9 B9 A9 F9 E8 C8 A8 B8 G13 (G12) (G11) F15 F14 F13 F12 E15 E14 E13 F11 D15 D14 D13 E12 C15 C14 D12 B14 B15 A15 C13 E11 A14 I/O  I/O I/O  I/O  I/O  I/O I/O  I/O  I/O  I/O I/O  I/O  I/O  I/O   O O   O I O O  I/O I/O  I/O I/O  I/O I/O  I/O I/O  I/O  Signal Name VDD D[28] (D[4]) D[27] (D[3]) VSS D[26] (D[2]) VSS D[25] (D[1]) VDD D[24] (D[0]) D[23] (D[15]) VDD D[22] (D[14]) VSS D[21] (D[13]) VDD D[20] (D[12]) D[19] (D[11]) VSS D[18] (D[10]) VDD D[17] (D[9]) VSS D[16] (D[8]) VDD NC CS0* RD* VSS VDD DGRNT* DREQ* ALE WE* VDD A[12] A[11] VSS A[10] A[9] VDD A[8] A[7] VSS A[6] A[5] VDD A[4] VSS (1) * Active-low signal (2) (3) ( ) indicates the signal name in the little endian mode The signal name change regarding DQMH/L is applied only to TMPR3912AU-92. 2-21 Chapter 2 Pin Descriptions Table 2.4.3 Pin Assignment (3/3) LQFP NO. FBGA (TMPR3912) NO. 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 D8 F7 A7 B7 C7 D7 E7 A6 B6 C6 D6 A5 B5 C5 E6 A4 B4 C4 I/O I/O I/O  I/O I/O   O O O O  O O O   O Signal Name A[3] A[2] VDD A[1] A[0] VSS VSS DCS0* RAS1* RAS0* CAS3* (CAS0*) VDD CAS2* (CAS1*) CAS1* (CAS2*) CAS0* (CAS3*) VSS VDD DCKE LQFP NO. FBGA (TMPR3912) NO. 203 204 205 206 207 208             D5 A3 B3 D4 B2 A2 B13 F6 F8 F10 G7 H5 H10 K6 K8 K10 N9 P3 I/O  I O  O O             Signal Name VSS DCLKIN DCLKOUT VDD DQMH (DQML) DQML (DQMH) NC NC NC NC NC NC NC NC NC NC NC NC (1) * Active-low signal (2) (3) ( ) indicates the signal name in the little endian mode The signal name change regarding DQMH/L is applied only to TMPR3912AU-92. 2-22 Chapter 2 Pin Descriptions 2.4.2 Pin Assignment (in case of TMPR3911BU) Table 2.4.4 Pin Assignment (1/2) NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I I/O I I/O  I/O   O  O O I O  I I/O I/O I/O I/O  I/O I/O I/O I/O  I/O  I/O I/O I/O I/O I/O I/O  I/O I/O I/O I/O I/O Signal Name VDDH D[0] (D [24]) D[1] (D [25]) D[2] (D [26]) D[3] (D [27]) VSS D[4] (D [28]) VDDL D[5] (D [29]) D[6] (D [30]) D[7] (D [31]) D[8] (D [16]) D[9] (D [17]) D[10] (D [18]) VSS D[11] (D [19]) D[12] (D [20]) D[13] (D [21]) D[14] (D [22]) D[15] (D [23]) VDDH ENDIAN MIOX[1] MBUSINT MBUSDATA VSS MBUSCLK VDDH VDDL SIBMCLK VSS SIBSCLK SIBSYNC SIBDIN SIBDOUT NC SIBIRQ MIOX[0] IO[6] IO[5] NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O I/O I/O I O I O I/O I O   I O I/O I/O O I O I I O I I O  I O  O I I I I I  O O O O O Signal Name CHICLK CHIFS CHIDIN CHIDOUT RXD TXD IO[4] IRIN IROUT VSS VDDL CARDET RXPWR IO[3] IO[2] SPICLK SPIIN SPIOUT TESTCPU TESTIN VIDDONE TESTAIU VCC3 BC32K VDDH C32KlN C32KOUT VSS PWRCS PWRlNT PWROK ONBUTN PON* CPURES* VDDL DISPON FRAME DF LOAD CP NO. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 I/O  O O O O  I/O  I O O I/O  O O O I  O O O O O O O O O O  I O   I/O I/O I/O I/O I/O  I/O Signal Name VSS VDAT[0] VDAT[1] VDAT[2] VDAT[3] VSS IO[1] VDDH CARD2WAIT* CARD2CSH* CARD2CSL* IO[0] VSS (PLL) CARDIORD* CARDIOWR* CARDREG* CARD1WAIT* VDD (PLL) CARDDIR* CARD1CSL* CARD1CSH* MCS3* MCS2* MCS1* MCS0* CS3* CS2* CS1* VDDH SYSCLKIN SYSCLKOUT VSS VDDL D[31] (D [7]) D[30] (D [6]) D[29] (D [5]) D[28] (D [4]) D[27] (D [3]) VSS D[26] (D [2]) (1) * Active-low signal (2) ( ) indicates the signal name in the little endian mode 2-23 Chapter 2 Pin Descriptions Table 2.4.5 Pin Assignment (2/2) NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 I/O I/O  I/O I/O I/O  I/O I/O I/O  I/O  I/O   I/O  O O   O I O O I/O I/O I/O I/O  I/O I/O  I/O I/O I/O I/O I/O  I/O Signal Name D[25] (D [1]) VDDH D[24] (D [0]) D[23] (D [15]) D[22] (D [14]) VSS D[21] (D [13]) D[20] (D [12]) D[19] (D [11]) VSS D[18] (D [10]) VDDL D[17] (D [9]) VSS NC D[16] (D [8]) VDDH CS0* RD* VSS VDDL DGRNT* DREQ* ALE WE* A[12] A[11] A[10] A[9] VDDH A[8] A[7] VSS A[6] A[5] A[4] A[3] A[2] VDDL A[1] NO. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 I/O I/O  O O O O O O O  O I O  O O Signal Name A[0] VSS DCS0* RAS1* RAS0* CAS3* (CAS0*) CAS2* (CAS1*) CAS1* (CAS2*) CAS0* (CAS3*) VDDH DCKE DCLKIN DCLKOUT NC DQMH(DQML) DQML(DQMH) NO. I/O Signal Name (1) * Active-low signal (2) ( ) indicates the signal name in the little endian mode 2-24 Chapter 2 Pin Descriptions 2.4.3 Pin Assignment (in case of TMPR3911BXB) Table 2.4.6 Pin Assignment (1/2) NO. A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 I/O I/O  I/O I/O I/O I/O I/O   O I I/O I O I/O O  I/O I/O I/O I/O I I   O I/O I/O I/O I O I O I/O I/O  I/O I/O I/O O Signal Name D[1] (D[25]) VDDH D[0] (D[24]) D[3] (D[27]) D[5] (D[29]) D[9] (D[17]) D[12] (D[20]) VDDH VDDH SIBSYNC SIBIRQ IO[5] CHIDIN CHIDOUT IO[4] DQML (DQMH) NC D[2] (D[26]) D[6] (D[30]) D[8] (D[16]) D[11] (D[19]) ENDIAN MBUSINT VSS VSS SIBDOUT MIOX[0] CHICLK CHIFS RXD DQMH (DQML) DCLKIN DCKE D[4] (D[28]) D[7] (D[31]) VSS D[15] (D[23]) D[13] (D[21]) MBUSCLK SIBMCLK NO. L3 M3 N3 P3 R3 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 A5 B5 C5 D5 E5 M5 N5 P5 R5 A6 B6 C6 D6 M6 N6 P6 R6 A7 B7 C7 I/O I  I/O I O O  O   I/O I/O I/O I/O  O  I I/O O O O O O   I/O O O O O  I/O O I I I I/O I/O  Signal Name SIBDIN NC IO[6] IRIN TXD DCLKOUT VDDH CAS1* (CAS2*) VSS VDDL D[10] (D[18]) D[14] (D[22]) MIOX[1] MBUSDATA VDDL SIBSCLK VSS CARDET IO[3] IROUT CAS0* (CAS3*) CAS2* (CAS1*) CAS3* (CAS0*) RAS1* NC VDDL IO[2] SPICLK RXPWR RAS0* DCS0* VSS A[0] SPIOUT TESTCPU TESTIN SPIIN A[1] A[2] VDDL NO. D7 M7 N7 P7 R7 A8 B8 C8 D8 M8 N8 P8 R8 A9 B9 C9 D9 M9 N9 P9 R9 A10 B10 C10 D10 M10 N10 P10 R10 A11 B11 C11 D11 M11 N11 P11 R11 A12 B12 C12 I/O I/O I O I O  I/O I/O I/O O I   I/O I/O I/O  O I I I O I/O I/O I/O  I I O  O I O O O O    O Signal Name A[3] VCC3 BC32K C32KIN VIDDONE VSS A[4] A[6] A[5] C32KOUT TESTAIU VSS VDDH A[9] A[7] A[8] VDDH PWRCS PWROK PWRINT ONBUTN WE* A[10] A[11] A[12] VDDL PON* CPURES* DISPON VDDL ALE DREQ* DGRNT* FRAME LOAD DF VSS VDDH VSS RD* (1) * Active-low signal (2) ( ) indicates the signal name in the little endian mode 2-25 Chapter 2 Pin Descriptions Table 2.4.7 Pin Assignment (2/2) NO. D12 E12 F12 G12 H12 J12 K12 L12 M12 N12 P12 R12 A13 B13 C13 D13 E13 F13 G13 H13 J13 K13 L13 M13 N13 P13 R13 A14 B14 C14 D14 E14 F14 G14 H14 J14 K14 L14 M14 N14 I/O O I/O I/O  O O O  O O O O  I/O I/O I/O  I/O I/O O O O O O O O I/O I/O  I/O  I/O  I/O  I O O O I/O Signal Name CS0* D[26] (D[2]) D[29] (D[5]) VDDL SYSCLKOUT CS2* MCS3* VDD (PLL) CARDIORD* CP VDAT[0] VDAT[3] VSS D[16] (D[8]) D[21] (D[13]) D[23] (D[15]) VDDH D[27] (D[3]) D[30] (D[6]) CS3* CS1* MCS2* CARDDIR* CARDIOWR* VDAT[1] VDAT[2] IO[1] D[17] (D[9]) VSS D[20] (D[12]) VSS D[24] (D[0]) VSS D[31] (D[7]) VSS SYSCLKIN MCS1* CARD1CSL* CARDREG* IO[0] NO. P14 R14 A15 B15 C15 D15 E15 F15 G15 H15 J15 K15 L15 M15 N15 P15 R15 I/O     I/O I/O I/O I/O I/O  O O I  O I O Signal Name VSS VDDH NC VDDL D[18] (D[10]) D[19] (D[11]) D[22] (D[14]) D[25] (D[1]) D[28] (D[4]) VDDH MCS0* CARD1CSH* CARD1WAIT* VSS (PLL) CARD2CSH* CARD2WAIT* CARD2CSL* NO. I/O Signal Name (1) * Active-low signal (2) ( ) indicates the signal name in the little endian mode 2-26 D[17] (D[9]) VSS N.C. D[16] (D[8]) VDDH CS0* RD* VSS VDDL DGRNT* DREQ* ALE WE* A[12] A[11] A[10] A[9] VDDH A[8] A[7] VSS A[6] A[5] A[4] A[3] A[2] VDDL A[1] A[0] VSS DCS0* RAS1* RAS0* CAS3* (CAS0*) CAS2* (CAS1*) CAS1* (CAS2*) CAS0* (CAS3*) VDDH DCKE DCLKIN DCLKOUT N.C. DQMH (DQML) DQML (DQMH) 2.4.4 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 P-LQFP176-2424-0.50A TMPR3911BU Pin Assignment 1 132 VDDL 2-27 VDDH D[0] (D[24]) D[1] (D[25]) D[2] (D[26]) D[3] (D[27]) VSS D[4] (D[28]) VDDL D[5] (D[29]) D[6] (D[30]) D[7] (D[31]) D[8] (D[16]) D[9] (D[17]) D[10] (D[18]) VSS D[11] (D[19]) D[12] (D[20]) D[13] (D[21]) D[14] (D[22]) D[15] (D[23]) VDDH ENDIAN MIOX[1] MBUSINT MBUSDATA VSS MBUSCLK VDDH VDDL SIBMCLK VSS SIBSCLK SIBSYNC SIBDIN SIBDOUT N.C. SIBIRQ MIOX[0] IO[6] IO[5] CHICLK CHIFS CHIDIN CHIDOUT 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 D[18] (D[10]) VSS D[19] (D[11]) D[20] (D[12]) D[21] (D[13]) VSS D[22] (D[14]) D[23] (D[15]) D[24] (D[0]) VDDH D[25] (D[1]) D[26] (D[2]) VSS D[27] (D[3]) D[28] (D[4]) D[29] (D[5]) D[30] (D[6]) D[31] (D[7]) VDDL VSS SYSCLKOUT SYSCLKIN VDDH CS1* CS2* CS3* MCS0* MCS1* MCS2* MCS3* CARD1CSH* CARD1CSL* CARDDIR* VDD (PLL) CARD1WAIT* CARDREG* CARDIOWR* CARDIORD* VSS (PLL) IO[0] CARD2CSL* CARD2CSH* CARD2WAIT* 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Chapter 2 Pin Descriptions 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 VDDH IO[1] VSS VDAT[3] VDAT[2] VDAT[1] VDAT[0] VSS CP LOAD DF FRAME DISPON VDDL CPURES* PON* ONBUTN PWROK PWRlNT PWRCS VSS C32KOUT C32KlN VDDH BC32K VCC3 TESTAIU VIDDONE TESTIN TESTCPU SPIOUT SPIIN SPICLK IO[2] IO[3] RXPWR CARDET VDDL VSS IROUT IRIN IO[4] TXD RXD D[17] (D[9]) VSS D[16] (D[8]) VDD NC CS0* RD* VSS VDD DGRNT* DREQ* ALE WE* VDD A[12] A[11] VSS A[10] A[9] VDD A[8] A[7] VSS A[6] A[5] VDD A[4] VSS A[3] A[2] VDD A[1] A[0] VSS VSS DCS0* RAS1* RAS0* CAS3* (CAS0*) VDD CAS2* (CAS1*) CAS1* (CAS2*) CAS0* (CAS3*) VSS VDD DCKE VSS DCLKIN DCLKOUT VDD DQMH (DQML) DQML (DQMH) 2.4.5 P-LQFP208-2828-0.50A 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 TMPR3912AU-92 2-28 VDD D[0] (D[24]) VSS D[1] (D[25]) D[2] (D[26]) VDD D[3] (D[27]) VSS D[4] (D[28]) VDD D[5] (D[29]) D[6] (D[30]) VSS D[7] (D[31]) VSS D[8] (D[16]) VDD D[9] (D[17]) D[10] (D[18]) VSS D[11] (D[19]) VDD D[12] (D[20]) D[13] (D[21]) VSS D[14] (D[22]) D[15] (D[23]) VDD ENDIAN MIOX[1] MBUSINT MBUSDATA VSS MBUSCLK VDD VDD SIBMCLK VSS SIBSCLK SIBSYNC SIBDIN SIBDOUT VDD SIBIRQ MIOX[0] IO[6] IO[5] VSS CHICLK CHIFS CHIDIN CHIDOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VDD D[18] (D[10]) VSS D[19] (D[11]) D[20] (D[12]) VDD D[21] (D[13]) VSS D[22] (D[14]) VDDss D[23] (D[15]) D[24] (D[0]) VDD D[25] (D[1]) VSS D[26] (D[2]) VSS D[27] (D[3]) D[28] (D[4]) VDD D[29] (D[5]) VSS D[30] (D[6]) D[31] (D[7]) VDD VSS VSS SYSCLKOUT SYSCLKIN VDD CS1* CS2* CS3* MCS0* MCS1* MCS2* MCS3* VSS CARD1CSH* CARD1CSL* VDD CARDDIR* VDD (PLL) CARD1WAIT* CARDREG* CARDIOWR* CARDIORD* VSS (PLL) IO[0] CARD2CSL* CARD2CSH* CARD2WAIT* Chapter 2 Pin Descriptions 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VDD IO[1] VSS VDAT[3] VDAT[2] VDAT[1] VDAT[0] VDD VSS CP LOAD DF VSS FRAME DISPON VDD CPURES* PON* ONBUTN NC PWROK PWRlNT PWRCS VSS C32KOUT C32KlN VDD BC32K VCC3 VSS TESTAIU VIDDONE TESTIN TESTCPU VDD SPIOUT SPIIN SPICLK VSS IO[2] IO[3] RXPWR CARDET VDD VSS IROUT IRIN NC IO[4] TXD RXD VDD Chapter 2 Pin Descriptions 2.4.6 TMPR3911BXB Ball Assignment P-FBGA177-1313-0.80C4 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B C 2 D[0] (D[24]) 4 D[2] (D[26]) 171 DCKE D 5 D[3] (D[27]) 10 D[6] (D[30]) 7 D[4] (D[28]) 6 VSS 164 RAS1* 161 A[0] 157 A[3] 155 A[5] 150 VDDH 146 A[12] E 9 D[5] (D[29]) 12 D[8] (D[16]) 11 D[7] (D[31]) 8 VDDL F 13 D[9] (D[17]) 16 D[11] (D[19]) 15 VSS 14 D[10] (D[18]) G H J 28 VDDH 26 VSS K 33 SIBSYNC 31 VSS L 37 SIBIRQ* 35 SIBDOUT 34 SIBDIN 32 SIBSCLK M 40 IO[5] 38 MIOX[0] 36 N.C. 50 VSS 51 VDDL 58 SPIOUT 63 VCC3 N 43 CHIDIN 41 CHICLK 39 IO[6] 52 CARDET 55 IO[2] 59 TESTCPU 64 BC32K 62 TESTAIU 71 PWROK 73 PON* 79 LOAD 80 CP 83 VDAT[1] 92 IO[0] 90 P 44 CHIDOUT 42 CHIFS 48 IRIN 54 IO[3] 56 SPICLK 60 TESTIN 66 C32KIN 68 VSS 70 PWRINT 74 CPURES* 78 DF 82 VDAT[0] 84 VDAT[2] 86 VSS 89 R 47 IO[4] 45 RXD 46 TXD 49 IROUT 53 RXPWR 57 SPIIN 61 VIDDONE 65 VDDH 72 ONBUTN 76 DISPON 81 VSS 85 VDAT[3] 87 IO[1] 88 VDDH 91 3 1 D[1] VDDH (D[25]) 176 174 DQML N.C. (DQMH) 175 172 DQMH DCLKIN (DQML) 173 170 DCLKOUT VDDH 17 21 D[12] VDDH (D[20]) 22 24 ENDIAN MBUSINT 20 D[15] (D[23]) 19 D[14] (D[22]) 18 D[13] (D[21]) 23 MIOX[1] 27 30 MBUSCLK SIBMCLK 25 MBUSDATA 168 CAS1* (CAS2*) 169 167 166 CAS0* CAS2* CAS3* (CAS3*) (CAS1*) (CAS0*) 165 163 162 VSS RAS0* DCS0* 160 A[1] 153 VSS 149 A[9] 145 WE* 141 VDDL 137 VDDH 134 VSS 133 D[17] (D[9]) 135 N.C. 158 A[2] 156 A[4] 152 A[7] 148 A[10] 144 ALE 140 VSS 136 D[16] (D[8]) 130 VSS 132 VDDL 159 VDDL 154 A[6] 151 A[8] 147 A[11] 29 VDDL N.C. Bottom View 67 C32KOUT 69 PWRCS 75 VDDL 77 FRAME 143 142 DREQ* DGRNT* 139 RD* 127 D[21] (D[13]) 128 D[20] (D[12]) 131 D[18] (D[10]) 138 CS0* 124 D[23] (D[15]) 126 VSS 129 D[19] (D[11]) 120 D[26] (D[2]) 122 VDDH 123 D[24] (D[0]) 125 D[22] (D[14]) 116 D[25] (D[5]) 118 D[27] (D[3]) 119 VSS 121 D[25] (D[1]) 113 VDDL 115 D[30] (D[6]) 114 D[31] (D[7]) 117 D[28] (D[4]) 111 SYSCLKOUT 107 CS2* 108 CS1* 110 SYSCLKIN 105 MCS0* 102 MCS3* 103 MCS2* 104 MCS1* 101 98 VDD-PLL 94 CARDIORD* 106 CS3* 112 VSS 109 VDDH 99 95 CARDDIR* CARDIOWR* 100 96 CARD1CSL* CARDREG* 97 93 VSS-PLL CARD1CSH* CARD1WAIT* CARD2CSH* CARD2WAIT* CARD2CSL* YY