POWER DRIVER FOR STEPPER MOTORS
INTEGRATED CIRCUITS
TMC5072 DATASHEET
Dual controller/driver for up to two 2-phase bipolar stepper motors. No-noise stepper operation.
Integrated motion controller and encoder counter. SPI, UART (single wire) and Step/Dir.
APPLICATIONS
CCTV, Security
Office Automation
Antenna Positioning
Heliostat Controller
Battery powered applications
ATM, Cash recycler, POS
Lab Automation
Liquid Handling
Medical
Printer and Scanner
Pumps and Valves
FEATURES
AND
BENEFITS
Two 2-phase stepper motors
Drive Capability up to 2x 1.1A coil current (2x 1.5A peak)
Parallel Option for one motor at 2.2A (3A peak)
Motion Controller with sixPoint™ ramp
Voltage Range 4.75… 26V DC
SPI & Single Wire UART
Dual Encoder Interface and 2x Ref.-Switch input per axis
Highest Resolution up to 256 microsteps per full step
stealthChop™ for extremely quiet operation and smooth motion
spreadCycle™ highly dynamic motor control chopper
dcStep™ load dependent speed control
stallGuard2™ high precision sensorless motor load detection
coolStep™ current control for energy savings up to 75%
Passive Braking and freewheeling mode
Full Protection & Diagnostics
Compact Size 7x7mm2 QFN48 package
BLOCK DIAGRAM
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
DESCRIPTION
The TMC5072 is a dual high performance
stepper motor controller and driver IC
with serial communication interfaces. It
combines flexible ramp generators for
automatic
target
positioning
with
industries’ most advanced stepper motor
drivers.
Based
on
TRINAMICs
sophisticated stealthChop chopper, the
driver ensures absolutely noiseless
operation combined with maximum
efficiency and best motor torque. High
integration, high energy efficiency and a
small form factor enable miniaturized
and scalable systems for cost effective
solutions. The complete solution reduces
learning curve to a minimum while
giving best performance in class.
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
2
APPLICATION EXAMPLES: HIGH FLEXIBILITY – MULTIPURPOSE USE
The TMC5072 scores with power density, complete motion controlling features and integrated power
stages. It offers a versatility that covers a wide spectrum of applications from battery systems up to
embedded applications with 1.5A motor current per coil. The small form factor keeps costs down and
allows for miniaturized layouts. Extensive support at the chip, board, and software levels enables rapid
design cycles and fast time-to-market with competitive products. High energy efficiency and reliability
deliver cost savings in related systems such as power supplies and cooling.
MINIATURIZED DESIGN
FOR ONE
STEPPER MOTOR
Ref.
Switches
High-Level
Interface
SPI
CPU
TMC5072
M
The stepper motor driver
outputs are switched in
parallel. A dual ABN encoder
interface and two reference
switch inputs are used.
Encoder
COMPACT DESIGN
FOR UP TO
510 STEPPER MOTORS
Motor 1
High-Level
Interface
CPU
UART
M
TMC5072
M
Motor 2
Motor 3
M
TMC5072
M
Motor 4
Up to 255 TMC5072
can be addressed.
An application for up to 510
stepper motors is shown.
The UART single wire differential interface allows for a
decentralized
distributed
system with a minimized
number of components.
Additionally,
an
ABN
encoder and up to two
reference switches can be
used for each motor. A
single CPU can control the
whole system. The CPUboard and controller / driver
boards are highly economical and space saving.
TMC5072-EVAL EVALUATION BOARD
EVALUATION & DEVELOPMENT PLATFORM
The TMC5072-EVAL is part of TRINAMICs universal
Layout for Evaluation
evaluation board system which provides a
convenient handling of the hardware as well as a
user-friendly software tool for evaluation. The
TMC5072 evaluation board system consists of three
parts: STARTRAMPE (base board), ESELSBRÜCKE
(connector board including several test points), and
TMC5072-EVAL.
ORDER CODES
Order code
TMC5072-LA
TMC5072-EVAL
TMC5072-BOB
LANDUNGSBRÜCKE
ESELSBRÜCKE
www.trinamic.com
PN
00-0139
40-0075
40-0122
40-0167
40-0098
Description
Dual axis stealthChop controller/driver, QFN-48
Evaluation board for TMC5072
Breakout board for simple prototyping
Baseboard for TMC5072-EVAL and further evaluation boards
Connector board for plug-in evaluation board system
Size [mm2]
7x7
85 x 55
25 x 36
85 x 55
61 x 38
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
3
TABLE OF CONTENTS
1
PRINCIPLES OF OPERATION
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
KEY CONCEPTS
5
CONTROL INTERFACES
6
SOFTWARE
6
MOVING AND CONTROLLING THE MOTOR
7
STEALTHCHOP DRIVER WITH PROGRAMMABLE
MICROSTEPPING WAVE
7
STALLGUARD2 – MECHANICAL LOAD SENSING 7
COOLSTEP – LOAD ADAPTIVE CURRENT CONTROL 8
DCSTEP – LOAD DEPENDENT SPEED CONTROL
8
ENCODER INTERFACES
8
PIN ASSIGNMENTS
2.1
2.2
3
PACKAGE OUTLINE
SIGNAL DESCRIPTIONS
SAMPLE CIRCUITS
3.1
3.2
3.3
3.4
3.5
3.6
4
STANDARD APPLICATION CIRCUIT
5 V ONLY SUPPLY
ONE MOTOR WITH HIGH CURRENT
EXTERNAL 5V POWER SUPPLY
OPTIMIZING ANALOG PRECISION
DRIVER PROTECTION AND EME CIRCUITRY
SPI INTERFACE
4.1
4.2
4.3
5
5.1
5.2
5.3
5.4
5.5
6
7
7.1
8
8.5
8.6
9
9
12
12
13
14
14
16
16
18
18
19
20
UART SINGLE WIRE INTERFACE
21
DATAGRAM STRUCTURE
CRC CALCULATION
UART SIGNALS
ADDRESSING MULTIPLE SLAVES
RING MODE
GENERAL CONFIGURATION REGISTERS
RAMP GENERATOR REGISTERS
ENCODER REGISTERS
MICROSTEP TABLE REGISTERS
MOTOR DRIVER REGISTERS
VOLTAGE PWM MODE STEALTHCHOP
21
23
23
24
26
28
31
37
39
41
46
47
SENSE RESISTORS
48
49
TWO MODES FOR CURRENT REGULATION
49
AUTOMATIC SCALING
50
FIXED SCALING
52
COMBINING STEALTHCHOP WITH OTHER CHOPPER
MODES
54
FLAGS IN STEALTHCHOP
55
FREEWHEELING AND PASSIVE MOTOR BRAKING 56
www.trinamic.com
9
SPREADCYCLE AND CLASSIC CHOPPER
9.1
9.2
9.3
10
SPREADCYCLE
CHOPPER
CLASSIC CONSTANT OFF TIME CHOPPER
RANDOM OFF TIME
DRIVER DIAGNOSTIC FLAGS
10.1
10.2
10.3
11
11.1
11.2
11.3
11.4
11.5
12
TUNING STALLGUARD2 THRESHOLD SGT
STALLGUARD2 UPDATE RATE AND FILTER
DETECTING A MOTOR STALL
HOMING WITH STALLGUARD
LIMITS OF STALLGUARD2 OPERATION
COOLSTEP OPERATION
USER BENEFITS
SETTING UP FOR COOLSTEP
TUNING COOLSTEP
DCSTEP
64
71
73
73
73
73
74
74
74
76
77
USER BENEFITS
77
DESIGNING-IN DCSTEP
77
ENABLING DCSTEP
78
STALL DETECTION IN DCSTEP MODE
78
MEASURING ACTUAL MOTOR VELOCITY IN DCSTEP
OPERATION
79
SINE-WAVE LOOK-UP TABLE
USER BENEFITS
MICROSTEP TABLE
STEP/DIR INTERFACE
16.1
16.2
16.3
17
63
63
63
70
15.1
15.2
16
63
STALLGUARD2 LOAD MEASUREMENT
14.1
14.2
14.3
14.4
14.5
15
58
61
62
64
65
67
67
68
13.1
13.2
13.3
14
57
REAL WORLD UNIT CONVERSION
MOTION PROFILES
INTERRUPT HANDLING
VELOCITY THRESHOLDS
REFERENCE SWITCHES
12.1
12.2
12.3
12.4
12.5
13
TEMPERATURE MEASUREMENT
SHORT TO GND PROTECTION
OPEN LOAD DIAGNOSTICS
RAMP GENERATOR
27
CURRENT SETTING
STEALTHCHOP™
8.1
8.2
8.3
8.4
9
SPI DATAGRAM STRUCTURE
SPI SIGNALS
TIMING
REGISTER MAPPING
6.1
6.2
6.3
6.4
6.5
6.6
5
80
80
80
82
TIMING
82
CHANGING RESOLUTION
83
MICROPLYER STEP INTERPOLATOR AND STAND
STILL DETECTION
83
ABN INCREMENTAL ENCODER INTERFACE 85
17.1
17.2
17.3
ENCODER TIMING
SETTING THE ENCODER TO MATCH MOTOR
RESOLUTION
CLOSING THE LOOP
86
86
87
18
QUICK CONFIGURATION GUIDE
88
19
GETTING STARTED
93
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
19.1
INITIALIZATION EXAMPLES
4
93
20
EXTERNAL RESET
95
21
CLOCK OSCILLATOR AND CLOCK INPUT
95
21.1
21.2
21.3
USING THE INTERNAL CLOCK
USING AN EXTERNAL CLOCK
CONSIDERATIONS ON THE FREQUENCY
95
95
96
22
ABSOLUTE MAXIMUM RATINGS
97
23
ELECTRICAL CHARACTERISTICS
97
23.1
23.2
23.3
24
OPERATIONAL RANGE
DC CHARACTERISTICS AND TIMING
CHARACTERISTICS
THERMAL CHARACTERISTICS
LAYOUT CONSIDERATIONS
24.1
24.2
EXPOSED DIE PAD
WIRING GND
www.trinamic.com
97
98
101
102
102
102
24.3
24.4
24.5
25
SUPPLY FILTERING
SINGLE DRIVER CONNECTION
LAYOUT EXAMPLE
PACKAGE MECHANICAL DATA
25.1
25.2
DIMENSIONAL DRAWINGS
PACKAGE CODES
102
102
103
104
104
104
26
DESIGN PHILOSOPHY
105
27
DISCLAIMER
105
28
ESD SENSITIVE DEVICE
105
29
TABLE OF FIGURES
106
30
REVISION HISTORY
107
31
REFERENCES
107
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
1
5
Principles of Operation
+VM
F
otor
ep m
t
S
l
o
co
r
drive
F
reference switch
processing
step multiplier
VCP
CPI
100n
charge pump
CPO
VSA
5V Voltage
regulator
5VOUT
100n
VCC
4.7µ
CSN/IO0
SCK/IO1
SDI/IO2
SDO/RING
SPI™
interface
selection
single wire
UART
F
SWIOP
F
SWION
F
ENC1A/INT
F
ENC1B/PP
F
INT & position
pulse output
O1A2
S
M
N
O1B1
2 phase
stepper
motor
O1B2
BR1A / B
Dual
Encoder
unit
ENC1A
ENC1B
IO0/SWIOP/REFL1
2A
2B
2N
REFR1
REFR2
IO1/SWION/REFL2
RSENSE
RSENSE
GNDP
stallGuard2™
2 x current
comparator
2 x DAC
dcStep™
RSENSE=0R25 allows for
maximum coil current
temperature
measurement
dcStep™
ol
contr
otion
2x linear 6 point
RAMP generator
reference switch
processing
2 x current
comparator
CLK oscillator/
selector
2 x DAC
GNDP
stallGuard2™
RSENSE
coolStep™
SINGLEDRV
DRV2:=DRV1
programmable
sine table
4*256 entry
x
step multiplier
O2A2
Half Bridge 1
Half Bridge 1
S
N
O2A1
VS
F = 60ns spike filter
100n
+VM
2 phase
stepper
motor
Stepper
#2
DRV_ENN
GND
GNDA
ref. / stop switches or
step & dir (motor 2)
O2B2
O2B1
spreadCycle &
stealthChop
Chopper
otor
tep m
S
l
o
o
c
r
drive
RSENSE
BR2A / B
Half Bridge 2
Half Bridge 2
Step &
Direction pulse
generation
DIE PAD
F
REFR2/DIR2
TST_MODE
F
REFL2/STEP2
100n
O1A1
coolStep™
1A
1B
1N
CLK_IN
VCC_IO
Half Bridge 1
Half Bridge 1
spreadCycle &
stealthChop
Chopper
x
Stepper
#1
+VM
VS
Half Bridge 2
Half Bridge 2
SINGLEDRV
Stepper driver
Protection
& diagnostics
interface
Diff. Tranceiver
encoder or
interrupt out
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
Control register
set
ce
terfa
InSingle
wire
SW_SEL
NEXTADDR
trol
n co n
o
i
t
o
M
SPI interface
programmable
sine table
4*256 entry
Step &
Direction pulse
generation
2x linear 6 point
RAMP generator
22n
100n
DRV_ENN
TMC5072
Dual stepper motor
driver / controller
REFR1/DIR1
REFL1/STEP1
ref. / stop switches or
step & dir (motor 1)
opt. driver enable
Figure 1.1 Basic application and block diagram
The TMC5072 motion controller and driver chip is an intelligent power component interfacing between
the CPU and one or two stepper motors. All stepper motor logic is completely within the TMC5072. No
software is required to control the motor – just provide target positions. The TMC5072 offers a
number of unique enhancements which are enabled by the system-on-chip integration of driver and
controller. The sixPoint ramp generator of the TMC5072 uses stealthChop, dcStep, coolStep, and
stallGuard2 automatically to optimize every motor movement. The clear concept and the
comprehensive solution save design time.
1.1 Key Concepts
The TMC5072 implements several advanced features which are exclusive to TRINAMIC products. These
features contribute toward greater precision, greater energy efficiency, higher reliability, smoother
motion, and cooler operation in many stepper motor applications.
stealthChop™
No-noise, high-precision chopper algorithm for inaudible motion and inaudible
standstill of the motor.
dcStep™
Load dependent speed control. The motor moves as fast as possible and never loses
a step.
stallGuard2™
High-precision load measurement using the back EMF on the motor coils.
coolStep™
Load-adaptive current control which reduces energy consumption by as much as
75%.
spreadCycle™
High-precision chopper algorithm available as an alternative to the traditional
constant off-time algorithm.
sixPoint™
Fast and precise positioning using a hardware ramp generator with a set of four
acceleration / deceleration settings. Quickest response due to dedicated hardware.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
6
In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect
and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage
conditions for enhancing safety and recovery from equipment malfunctions.
1.2 Control Interfaces
The TMC5072 supports both, an SPI and a UART based single wire interface with CRC checking.
Selection of the actual interface is done via the configuration pin SW_SEL, which can be hardwired to
GND or VCC_IO depending on the desired interface.
1.2.1
SPI Interface
The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus
master to the bus slave another bit is sent simultaneously from the slave to the master.
Communication between an SPI master and the TMC5072 slave always consists of sending one 40-bit
command word and receiving one 40-bit status word.
The SPI command rate typically is a few commands per complete motor motion.
1.2.2
UART Interface
The single wire interface allows differential operation similar to RS485 (using SWIOP and SWION) or
single wire interfacing (leaving open SWION). It can be driven by any standard UART. No baud rate
configuration is required. An optional ring mode allows chaining of slaves to optimize interfacing for
applications with regularly distributed drives.
1.3 Software
From a software point of view the TMC5072 is a peripheral with a number of control and status
registers. Most of them can either be written only or read only. Some of the registers allow both read
and write access. In case read-modify-write access is desired for a write only register, a shadow
register can be realized in master software.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
7
1.4 Moving and Controlling the Motor
1.4.1
Integrated Motion Controller
The integrated 32 bit motion controller automatically drives the motor to target positions, or
accelerates to target velocities. All motion parameters can be changed on the fly. The motion
controller recalculates immediately. A minimum set of configuration data consists of acceleration and
deceleration values and the maximum motion velocity. A start and stop velocity is supported as well
as a second acceleration and deceleration setting. The integrated motion controller supports
immediate reaction to mechanical reference switches and to the sensorless stall detection stallGuard2.
Benefits are:
Flexible ramp programming
Efficient use of motor torque for acceleration and deceleration allows higher machine throughput
Immediate reaction to stop and stall conditions
1.4.2
STEP/DIR Interface
One or both motors can optionally be controlled by a step and direction input. In this case, the
respective motion controller remains unused. Active edges on the STEP input can be rising edges or
both rising and falling edges as controlled by another mode bit (DEDGE). Using both edges cuts the
toggle rate of the STEP signal in half, which is useful for communication over slow interfaces such as
optically isolated interfaces. On each active edge, the state sampled from the DIR input determines
whether to step forward or back. Each step can be a fullstep or a microstep, in which there are 2, 4, 8,
16, 32, 64, 128, or 256 microsteps per fullstep. During microstepping, a step impulse with a low state
on DIR increases the microstep counter and a high decreases the counter by an amount controlled by
the microstep resolution. An internal table translates the counter value into the sine and cosine
values which control the motor current for microstepping.
1.5 stealthChop Driver with Programmable Microstepping
Wave
Current into the motor coils is controlled using a cycle-by-cycle chopper mode. Up to three chopper
modes are available: a traditional constant off-time mode and the spreadCycle mode as well as the
unique stealthChop. The constant off-time mode provides higher torque at highest velocity, while
spreadCycle mode offers smoother operation and greater power efficiency over a wide range of speed
and load. The spreadCycle chopper scheme automatically integrates a fast decay cycle and guarantees
smooth zero crossing performance. In contrast to the other chopper modes, stealthChop is a voltage
chopper based principle. It guarantees that the motor is absolutely quiet in standstill and in slow
motion, except for noise generated by ball bearings. The extremely smooth motion is beneficial for
many applications.
Programmable microstep shapes allow optimizing the motor performance.
Benefits of using stealthChop:
- Significantly improved microstepping with low cost motors
- Motor runs smooth and quiet
- Absolutely no standby noise
- Reduced mechanical resonances yields improved torque
1.6 stallGuard2 – Mechanical Load Sensing
stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall
detection as well as other uses at loads below those which stall the motor, such as coolStep loadadaptive current reduction. This gives more information on the drive allowing functions like
sensorless homing and diagnostics of the drive mechanics.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
8
1.7 coolStep – Load Adaptive Current Control
coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement
information to adjust the motor current to the minimum amount required in the actual load situation.
This saves energy and keeps the components cool.
Benefits are:
- Energy efficiency
- Motor generates less heat
- Less or no cooling
- Use of smaller motor
power consumption decreased up to 75%
improved mechanical precision
improved reliability
less torque reserve required → cheaper motor does the job
Figure 1.2 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to
standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example.
0,9
Efficiency with coolStep
0,8
Efficiency with 50% torque reserve
0,7
0,6
0,5
Efficiency
0,4
0,3
0,2
0,1
0
0
50
100
150
200
250
300
350
Velocity [RPM]
Figure 1.2 Energy efficiency with coolStep (example)
1.8 dcStep – Load Dependent Speed Control
dcStep allows the motor to run near its load limit and at its velocity limit without losing a step. If the
mechanical load on the motor increases to the stalling load, the motor automatically decreases
velocity so that it can still drive the load. With this feature, the motor will never stall. In addition to
the increased torque at a lower velocity, dynamic inertia will allow the motor to overcome
mechanical overloads by decelerating. dcStep directly integrates with the ramp generator, so that the
target position will be reached, even if the motor velocity needs to be decreased due to increased
mechanical load. A dynamic range of up to factor 10 or more can be covered by dcStep without any
step loss. By optimizing the motion velocity in high load situations, this feature further enhances
overall system efficiency.
Benefits are:
- Motor does not loose steps in overload conditions
- Application works as fast as possible
- Highest possible acceleration automatically
- Highest energy efficiency at speed limit
- Highest possible motor torque using fullstep drive
- Cheaper motor does the job
1.9 Encoder Interfaces
The TMC5072 provides two encoder interfaces for external incremental encoders. The encoders can be
used for homing of the motion controllers (alternatively to reference switches) and for consistency
checks on-the-fly between encoder position and ramp generator position. A programmable prescaler
allows the adaptation of the encoder resolution to the motor resolution. 32 bit encoder counters are
provided.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
2
9
Pin Assignments
TST_MODE
O1A1
BR1A
O1A2
VS
GNDP
VS
O1B1
BR1B
O1B2
-
VCP
48
47
46
45
44
43
42
41
40
39
38
37
2.1 Package Outline
ENC1A/INT
1
36
CPI
ENC1B/PP
2
35
CSN/IO0
3
34
CPO
GND
SCK/IO1
4
33
VCC
SDI/IO2
5
32
5VOUT
GND
6
31
GNDA
VCC_IO
7
30
VSA
SDO/RING
8
29
DRV_ENN
SWIOP
9
28
REFL1
SWION
10
27
REFR1
CLK
11
26
REFL2
SWSEL
12
25
REFR2
17
18
19
20
21
22
23
24
VS
GNDP
VS
O2B1
BR2B
O2B2
-
NEXTADDR
15
BR2A
O2A2
14
O2A1
16
13
-
TMC 5072-LA
B. Dwersteg,
TRINAMIC
2012
QFN48
7mm
x 7mm
0.5 pitch
Figure 2.1 TMC5072 pin assignments.
2.2 Signal Descriptions
Pin
GND
VCC_IO
VSA
Number
6, 34
7
30
Type
GND
GNDA
5VOUT
31
32
GND
www.trinamic.com
Function
Digital ground pin for IO pins and digital circuitry.
3.3V or 5V I/O supply voltage pin for all digital pins.
Analog supply voltage for 5V regulator – typically supplied with
driver supply voltage. An additional 100nF capacitor to GND (GND
plane) is recommended for best performance.
Analog GND. Tie to GND plane.
Output of internal 5V regulator. Attach 2.2μF or larger ceramic
capacitor to GNDA near to pin for best performance. May be used to
supply VCC of chip.
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
Pin
VCC
Number
33
Type
DIE_PAD
-
GND
10
Function
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). May be supplied by
5VOUT. A 2.2Ω resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT or VCC_IO, whichever comes up
later!
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
Table 2.1 Low voltage digital and analog power supply pins
Pin
CPO
Number
35
Type
O(VCC)
CPI
36
I(VCP)
VCP
37
Function
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
Charge pump capacitor input: Provide external 22nF or 33nF / 50 V
capacitor to CPO.
Output of charge pump. Provide external 100nF capacitor to VS.
Table 2.2 Charge pump pins
Pin
ENC1A/INT
Number
1
Type
I/O
ENC1B/PP
2
I/O
CSN/IO0
SCK/IO1
SDI/IO2
SDO/RING
3
4
5
8
I/O
I/O
I/O
I/O
SWIOP
(ENC1N)
SWION
(ENC2N)
9
I/O
10
I/O
CLK
11
I
SWSEL
12
I
NEXTADDR
24
I
REFR2/DIR2
(ENC2B)
REFL2/STEP2
25
I
26
I
REFR1/DIR1
(ENC2A)
REFL1/STEP1
27
I
28
I
DRV_ENN
29
I
TST_MODE
48
I
www.trinamic.com
Function
Input A for incremental encoder 1. Can be programmed to provide
positive active interrupt output based on ramp generator flags
RAMP_STAT bits 4, 5, 6 & 7 and encoder null event status
ENC_STATUS bit 0 (poscmp_enable=1).
Input B for incremental encoder 1. Can be programmed to provide
position compare output for motor 1 (poscmp_enable=1).
Chip select input of SPI interface, programmable IO in UART mode
Serial clock input of SPI interface, programmable IO in UART mode
Data input of SPI interface, programmable IO in UART mode
Data output of SPI interface (Tristate, enabled with CSN=0), mode
configuration input in UART mode (0 = Normal mode, 1 = Single wire
ring mode – SWIO_P is input, SWIO_N is output)
Single wire I/O (positive). Serial input in ring mode. Multi-purpose
input in SPI mode or encoder 1 N input.
Single wire I/O (negative) for differential mode. Leave open in nondifferential mode when operating at 5V IO voltage or tie to desired
threshold voltage. Serial output in ring mode. Multi-purpose input in
SPI mode or encoder 2 N input.
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
Interface selection input. Tie to GND for SPI mode, tie to VCC_IO for
single wire (UART) interface mode.
Address increment (if tied high) for single wire (UART) mode. General
purpose input in SPI mode
Right reference switch input for motor 2, optional DIR input for
STEP/DIR operation of motor 2 or encoder 2 B input
Left reference switch input for motor 2, optional STEP input for
STEP/DIR operation of motor 2
Right reference switch input for motor 1, optional DIR input for
STEP/DIR operation of motor 1 or encoder 2 A input
Left reference switch input for motor 1, optional STEP input for
STEP/DIR operation of motor 1
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
Test mode input. Tie to GND using short wire.
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
Pin
-
Number Type
13, 23, 38 N.C.
11
Function
Unused pins – no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)
Pin
O2A1
BR2A
Number
14
15
Type
O (VS)
O2A2
VS
16
17, 19
O (VS)
GNDP
O2B1
BR2B
18
20
21
GND
O (VS)
O2B2
O1B2
BR1B
22
39
40
O (VS)
O (VS)
O1B1
VS
41
42, 44
O (VS)
GNDP
O1A2
BR1A
43
45
46
GND
O (VS)
O1A1
47
O (VS)
Table 2.4 Power driver pins
www.trinamic.com
Function
Motor 2 coil A output 1
Sense resistor connection for motor 2 coil A. Place sense resistor to
GND near pin.
Motor 2 coil A output 2
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 2 coil B output 1
Sense resistor connection for motor 2 coil B. Place sense resistor to
GND near pin.
Motor 2 coil B output 2
Motor 1 coil B output 2
Sense resistor connection for motor 1 coil B. Place sense resistor to
GND near pin.
Motor 1 coil B output 1
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 1 coil A output 2
Sense resistor connection for motor 1 coil A. Place sense resistor to
GND near pin.
Motor 1 coil A output 1
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
3
12
Sample Circuits
The sample circuits show the connection of the external components in different operation and
supply modes. The connection of the bus interface and further digital signals is left out for clarity.
REFR1/DIR1
+VM
VS
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
4.7µ
reference switch
processing
100n
DRV_ENN
Optional use lower
voltage down to 6V
REFL1/STEP1
CPI
22n
CPO
3.1 Standard Application Circuit
O1A1
Full Bridge A
5V Voltage
regulator
O1A2
Controller 1
2R2
Driver 1
Full Bridge B
470n
+VIO
stepper
motor #1
N
stepper
motor #2
O1B2
R1A
BR1B
SPI interface
R1B
TMC5072
VS
Single wire
interface
+VM
SWIOP
N
BR1A
NEXTADDR
SWION
S
O1B1
VCC
CSN/IO0
SCK/IO1
SDI/IO2
SDO/RING
100µF
100n
O2A1
Full Bridge A
SW_SEL
ENC1A/INT
ENC1B/PP
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
O2A2
Controller 2
Driver 2
S
O2B1
INT & position
pulse output
Full Bridge B
O2B2
CLK_IN
BR2A
reference switch
processing
VCC_IO
R2A
BR2B
R2B
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
REFR2/DIR2
REFL2/STEP2
TST_MODE
Figure 3.1 Standard application circuit
The standard application circuit uses a minimum set of additional components in order to operate the
motor. Use low ESR capacitors for filtering the power supply which are capable to cope with the
current ripple. The current ripple often depends on the power supply and cable length. The VCC_IO
voltage can be supplied from 5VOUT, or from an external source, e.g. a low drop 3.3V regulator. In
order to minimize linear voltage regulator power dissipation of the internal 5V voltage regulator in
applications where VM is high, a different (lower) supply voltage can be used for VSA, if available. For
example, many applications provide a 12V supply in addition to a higher supply voltage like 24V.
Using the 12V supply for VSA will reduce the power dissipation of the internal 5V regulator to about
37% of the dissipation caused by supply with the full motor voltage. For best motor chopper
performance, an optional R/C-filter de-couples 5VOUT from digital noise cause by power drawn from
VCC.
Basic layout hints
Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid
common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor
directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are
recommended for VS filtering.
Attention
In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by
more than one diode drop, especially also upon power up or power down.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
13
REFR1/DIR1
REFL1/STEP1
CPI
22n
CPO
3.2 5 V Only Supply
+5V
VS
+5V
100n
O1A1
Full Bridge A
5V Voltage
regulator
5VOUT
4.7µ
O1A2
Controller 1
Driver 1
Full Bridge B
BR1A
BR1B
SPI interface
SWIOP
VS
Single wire
interface
stepper
motor #2
O2A1
Full Bridge A
SW_SEL
ENC1B/PP
O2A2
Controller 2
Driver 2
O2B1
INT & position
pulse output
Full Bridge B
O2B2
CLK_IN
BR2A
reference switch
processing
VCC_IO
S
BR2B
RS2A
ENC1A/INT
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
N
100n
RS2B
+VIO
stepper
motor #1
+5V
TMC5072
SWION
N
O1B2
470n
NEXTADDR
S
O1B1
VCC
CSN/IO0
SCK/IO1
SDI/IO2
SDO/RING
100µF
RS1A
VSA
reference switch
processing
RS1B
charge pump
DRV_ENN
VCP
100n
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
REFR2/DIR2
REFL2/STEP2
TST_MODE
Figure 3.2 5V only operation
While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only
application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop
must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the
external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should
have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
14
3.3 One Motor with High Current
REFR1/DIR1
REFL1/STEP1
CPI
22n
CPO
The TMC5072 supports double motor current for a single driver by paralleling both power stages. In
order to operate in this mode, activate the flag single_driver in the global configuration register
GCONF. This register can be locked for subsequent write access.
+VM
VS
+VM
100n
100n
O1A1
Full Bridge A
5V Voltage
regulator
4.7µ
O1A2
Controller 1
Driver 1
Full Bridge B
+VIO
SWION
BR1B
SPI interface
TMC5072
VS
Single wire
interface
100n
O2A1
Full Bridge A
SW_SEL
ENC1A/INT
ENC1B/PP
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
high current
stepper motor
+VM
SWIOP
N
O1B2
BR1A
NEXTADDR
S
O1B1
VCC
CSN/IO0
SCK/IO1
SDI/IO2
SDO/RING
100µF
RS1A
VSA
5VOUT
reference switch
processing
RS1B
charge pump
DRV_ENN
VCP
100n
O2A2
Controller 2
Driver 2
O2B1
INT & position
pulse output
Full Bridge B
O2B2
CLK_IN
BR2A
reference switch
processing
VCC_IO
BR2B
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
REFR2/DIR2
REFL2/STEP2
TST_MODE
Figure 3.3 Driving a single motor with high current
3.4 External 5V Power Supply
When an external 5V power supply is available, the power dissipation caused by the internal linear
regulator can be eliminated. This especially is beneficial in high voltage applications, and when
thermal conditions are critical. There are two options for using this external 5V source: either the
external 5V source is used to support the digital supply of the driver by supplying the VCC pin, or the
complete internal voltage regulator becomes bridged and is replaced by the external supply voltage.
3.4.1
Support for the VCC Supply
This scheme uses an external supply for all digital circuitry within the driver (Figure 3.4). As the digital
circuitry makes up for most of the power dissipation, this way the internal 5V regulator sees only low
remaining load. The precisely regulated voltage of the internal regulator is still used as the reference
for the motor current regulation as well as for supplying internal analog circuitry.
When cutting pin VCC from 5VOUT, make sure that the VCC supply comes up before or synchronously
with the 5VOUT supply to ensure a correct power up reset of the internal logic. A simple schematic
uses two diodes forming an OR of the internal and the external power supplies for VCC. In order to
prevent the chip from drawing part of the power from its internal regulator, a low drop 1A Schottky
diode is used for the external 5V supply path, while a silicon diode is used for the 5VOUT path. An
enhanced solution uses a dual PNP transistor as an active switch. It minimizes voltage drop and thus
gives best performance.
In certain setups, switching of VCC voltage can be eliminated. A third variant uses the VCC_IO supply
to ensure power-on reset. This is possible, if VCC_IO comes up synchronously with or delayed to VCC.
Use a linear regulator to generate a 3.3V VCC_IO from the external 5V VCC source. This 3.3V regulator
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
15
will cause a certain voltage drop. A voltage drop in the regulator of 0.9V or more (e.g. LD1117-3.3)
ensures that the 5V supply already has exceeded the lower limit of about 3.0V once the reset
conditions ends. The reset condition ends earliest, when VCC_IO exceeds the undervoltage limit of
minimum 2.1V. Make sure that the power-down sequence also is safe. Undefined states can result
when VCC drops well below 4V without safely triggering a reset condition. Triggering a reset upon
power-down can be ensured when VSA goes down synchronously with or before VCC.
+VM
+VM
VSA
100n
+5V
4.7µ
VSA
5V Voltage
regulator
5VOUT
5VOUT
+5V
LL4448
100n
4.7µ
VCC
MSS1P3
5V Voltage
regulator
VCC
VCC_IO
3.3V
regulator
470n
470n
100n
3.3V
VCC supplied from external 5V. 5V or 3.3V IO voltage.
VCC supplied from external 5V. 3.3V IO voltage generated from same source.
+VM
VSA
5VOUT
100n
5V Voltage
regulator
4.7µ
BAT54
+5V
10k
VCC
2x BC857 or
1x BC857BS
470n
4k7
VCC supplied from external 5V using active switch. 5V or 3.3V IO voltage.
Figure 3.4 Using an external 5V supply for digital circuitry of driver (different options)
3.4.2
Internal Regulator Bridged
In case a clean external 5V supply is available, it can be used for complete supply of analog and
digital part (Figure 3.5). The circuit will benefit from a well regulated supply, e.g. when using a +/-1%
regulator. A precise supply guarantees increased motor current precision, because the voltage at
5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current
control. For best performance, the power supply should have low ripple to give a precise and stable
supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher
remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case,
increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low
frequency ripple, this would affect the precision of the motor current regulation as well as add
chopper noise.
Well-regulated, stable
supply, better than +-5%
+5V
VSA
5VOUT
4.7µ
5V Voltage
regulator
10R
VCC
470n
Figure 3.5 Using an external 5V supply to bypass internal regulator
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
16
3.5 Optimizing Analog Precision
CPI
22n
CPO
The 5VOUT pin is used as an analog reference for operation of the TMC5072. Performance will degrade
when there is voltage ripple on this pin. Most of the high frequency ripple in a TMC5072 design
results from the operation of the internal digital logic. The digital logic switches with each edge of
the clock signal. Further, ripple results from operation of the charge pump, which operates with
roughly 1 MHz and draws current from the VCC pin. In order to keep this ripple as low as possible, an
additional filtering capacitor can be put directly next to the VCC pin with vias to the GND plane giving
a short connection to the digital GND pins (pin 6 and pin 34). Analog performance is best, when this
ripple is kept away from the analog supply pin 5VOUT, using an additional series resistor of 2.2 Ω. The
voltage drop on this resistor will be roughly 100 mV (IVCC * R).
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
5V Voltage
regulator
GNDA
4.7µ
2R2
VCC
470n
Figure 3.6 RC-Filter on VCC for reduced ripple
3.6 Driver Protection and EME Circuitry
Some applications have to cope with ESD events caused by motor operation or external influence.
Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset
or even a destruction of the motor driver, depending on their energy. Especially plastic housings and
belt drive systems tend to cause ESD events. It is best practice to avoid ESD events by attaching all
conductive parts, especially the motors themselves to PCB ground, or to apply electrically conductive
plastic parts. In addition, the driver can be protected up to a certain degree against ESD events or live
plugging / pulling the motor, which also causes high voltages and high currents into the motor
connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the dV/dt caused
by ESD events. Larger capacitors will bring more benefit concerning ESD suppression, but cause
additional current flow in each chopper cycle, and thus increase driver power dissipation, especially at
high supply voltages. The values shown are example values – they might be varied between 100pF
and 1nF. The capacitors also dampen high frequency noise injected from digital parts of the circuit
and thus reduce electromagnetic emission. A more elaborate scheme uses LC filters to de-couple the
driver outputs from the motor connector. Varistors in between of the coil terminals eliminate coil
overvoltage caused by live plugging. Optionally protect all outputs by a varistor against ESD voltage.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
17
470pF
100V
OA1
Full Bridge A
OA1
OA2
S
N
stepper
motor
Full Bridge A
50Ohm @
100MHz
V1A
V1
OA2
50Ohm @
100MHz
470pF
100V
BRA
Driver
RSA
470pF
100V
S
N
stepper
motor
V1B
470pF
100V
Driver
100nF
16V
470pF
100V
OB1
Full Bridge B
OB1
Full Bridge B
OB2
50Ohm @
100MHz
V2A
V2
OB2
50Ohm @
100MHz
470pF
100V
BRB
RSB
100nF
16V
470pF
100V
Fit varistors to supply voltage
rating. SMD inductivities
conduct full motor coil
current.
Figure 3.7 Simple ESD enhancement and more elaborate motor output protection
www.trinamic.com
V2B
470pF
100V
Varistors V1 and V2 protect
against inductive motor coil
overvoltage.
V1A, V1B, V2A, V2B:
Optional position for varistors
in case of heavy ESD events.
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
4
18
SPI Interface
4.1 SPI Datagram Structure
The TMC5072 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the TMC5072 must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.
Each datagram sent to the device is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set. Each register is accessed via 32
data bits even if it uses less than 32 data bits.
For simplification, each register is specified by a one byte address:
- For a read access the most significant bit of the address byte is 0.
- For a write access the most significant bit of the address byte is 1.
Most registers are write only registers, some can be read additionally, and there are also some read
only registers.
SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
39 ...
→ 8 bit address
8 bit SPI status
... 0
→ 32 bit data
39 ... 32
→ to TMC5072:
RW + 7 bit address
from TMC5072:
8 bit SPI status
W
39 / 38 ... 32
38...32
LSB (transmitted last)
31 ... 0
8 bit data
8 bit data
31 ... 24
31...28
27...24
23 ... 16
23...20
19...16
8 bit data
8 bit data
15 ... 8
15...12
7 ... 0
11...8
7...4
3...0
3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4.1.1
Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.
Whenever data is read from or written to the TMC5072, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
19
Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to
be set to 0x21 in the access preceding the read access. For a write access to the register
(VACTUAL), the address byte has to be set to 0x80 + 0x22 = 0xA2. For read access, the data
bit might have any value (-). So, one can set them to 0.
action
read XACTUAL
read XACTUAL
write VMAX:= 0x00ABCDEF
write VMAX:= 0x00123456
data sent to TMC5072
→ 0x2100000000
→ 0x2100000000
→ 0xA700ABCDEF
→ 0xA700123456
data received from TMC5072
0xSS & unused data
0xSS & XACTUAL
0xSS & XACTUAL
0xSS00ABCDEF
*)S: is a placeholder for the status bits SPI_STATUS
4.1.2
SPI Status Bits Transferred with Each Datagram Read Back
New status information becomes latched at the end of each access and is available with the next SPI
transfer.
SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32
Bit
7
6
5
4
3
2
1
0
Name
Comment
status_stop_l(2)
status_stop_l(1)
velocity_reached(2)
velocity_reached(1)
driver_error(2)
driver_error(1)
reset_flag
reserved (0)
RAMP_STAT2[0] – 1: Signals motor 2 stop left switch status
RAMP_STAT1[0] – 1: Signals motor 1 stop left switch status
RAMP_STAT2[8] – 1: Signals motor 2 has reached its target velocity
RAMP_STAT1[8] – 1: Signals motor 1 has reached its target velocity
GSTAT[2] – 1: Signals driver 2 driver error (clear by reading GSTAT)
GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT)
GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT)
4.1.3
Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2 SPI Signals
The SPI bus on the TMC5072 has four signals:
- SCK – bus clock input
- SDI – serial data input
- SDO – serial data output
- CSN – chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC5072.
If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
20
4.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
tCC
tCL
tCH
tCH
tCC
SCK
tDU
SDI
bit39
tDH
bit38
bit0
tDO
SDO
tZC
bit39
bit38
bit0
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3
SPI interface timing
Parameter
SCK valid before or after change
of CSN
AC-Characteristics
clock period: tCLK
Symbol
tCC
fSCK
fSCK
assumes
synchronous CLK
tCSH
SCK low time
tCL
SCK high time
tCH
www.trinamic.com
Min
Typ
Max
10
*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only
*) Min time is for
synchronous CLK
only
*) Min time is for
synchronous CLK
only
assumes minimum
OSC frequency
CSN high time
SCK frequency using internal
clock
SCK frequency using external
16MHz clock
SDI setup time before rising
edge of SCK
SDI hold time after rising edge
of SCK
Data out valid time after falling
SCK clock edge
SDI, SCK and CSN filter delay
time
Conditions
Unit
ns
tCLK*)
>2tCLK+10
ns
tCLK*)
>tCLK+10
ns
tCLK*)
>tCLK+10
ns
4
MHz
8
MHz
tDU
10
ns
tDH
10
ns
tDO
no capacitive load
on SDO
tFILT
rising and falling
edge
12
20
tFILT+5
ns
30
ns
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
5
21
UART Single Wire Interface
The UART single wire interface allows the control of the TMC5072 with any microcontroller UART. It
shares transmit and receive line like an RS485 based interface. Data transmission is secured using a
cyclic redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can
be bridged without the danger of wrong or missed commands even in the event of electro-magnetic
disturbance. The automatic baud rate detection and an advanced addressing scheme make this
interface easy and flexible to use.
5.1 Datagram Structure
5.1.1
Write Access
UART WRITE ACCESS DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
0 … 63
8 bit slave
RW + 7 bit
sync + reserved
32 bit data
address
register addr.
56…63
63
…
CRC
56
55
…
24…55
data bytes 3, 2, 1, 0
(high to low byte)
24
1
23
…
16…23
register
address
16
4
15
3
…
2
SLAVEADDR
8
0
7
1
6
0
5
1
1
8…15
Reserved (don’t cares
but included in CRC)
0
0…7
CRC
A sync nibble precedes each transmission to and from the TMC5072 and is embedded into the first
transmitted byte, followed by an addressing byte. Each transmission allows a synchronization of the
internal baud rate divider to the master clock. The actual baud rate is adapted and variations of the
internal clock frequency are compensated. Thus, the baud rate can be freely chosen within the valid
range. Each transmitted byte starts with a start bit (logic 0, low level on SWIOP) and ends with a stop
bit (logic 1, high level on SWIOP). The bit time is calculated by measuring the time from the
beginning of start bit (1 to 0 transition) to the end of the sync frame (1 to 0 transition from bit 2 to
bit 3). All data is transmitted byte wise. The 32 bit data words are transmitted with the highest byte
first.
A minimum baud rate of 9000 baud is permissible, assuming 20 MHz clock (worst case for low baud
rate). Maximum baud rate is fCLK/16 due to the required stability of the baud clock.
The slave address is determined by the register SLAVEADDR. If the external address pin NEXTADDR is
set, the slave address becomes incremented by one.
The communication becomes reset if a pause time of longer than 63 bit times between the start bits
of two successive bytes occurs. This timing is based on the last correctly received datagram. In this
case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of
bus idle time. This scheme allows the master to reset communication in case of transmission errors.
Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout
of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treated the
same way. This allows a safe re-synchronization of the transmission after any error conditions.
Remark, that due to this mechanism, an abrupt reduction of the baud rate to less than 15 percent of
the previous value is not possible.
Each accepted write datagram becomes acknowledged by the receiver by incrementing an internal
cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the
success of an initialization sequence or single write accesses. Read accesses do not modify the
counter.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
5.1.2
22
Read Access
UART READ ACCESS REQUEST DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
8…15
16…23
24…31
31
…
CRC
24
23
0
…
16
register address
15
…
SLAVEADDR
8
0
7
1
6
0
5
1
Reserved (don’t cares
but included in CRC)
4
0...7
3
CRC
2
RW + 7 bit register
address
1
8 bit slave address
0
sync + reserved
The read access request datagram structure is identical to the write access datagram structure, but
uses a lower number of user bits. Its function is the addressing of the slave and the transmission of
the desired register address for the read access. The TMC5072 responds with the same baud rate as
the master uses for the read request.
In order to ensure a clean bus transition from the master to the slave, the TMC5072 does not
immediately send the reply to a read access, but it uses a programmable delay time after which the
first reply byte becomes sent following a read request. This delay time can be set in multiples of
eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the
master. In a multi-slave system, set SENDDELAY to min. 2 for all slaves. Otherwise a non-addressed
slave might detect a transmission error upon read access to a different slave.
UART READ ACCESS REPLY DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
CRC
24…55
data bytes 3, 2, 1, 0
(high to low byte)
56…63
63
…
CRC
56
55
32 bit data
…
0
23
…
15
3
…
2
16…23
register
address
0xFF
8
1
reserved (0)
7
0
6
1
5
0
8…15
4
1
0
0…7
16
sync + reserved
24
0 ...... 63
8 bit slave
RW + 7 bit
address
register addr.
The read response is sent to the master using address code %1111. The transmitter becomes switched
inactive four bit times after the last bit is sent.
Address %11111111 is reserved for read accesses going to the master. A slave cannot use this
address.
ERRATA IN READ ACCESS
A known bug in the UART interface implementation affects read access to registers that change during
the access. While the SPI interface takes a snapshot of the read register before transmission, the UART
interface transfers the register directly MSB to LSB without taking a snapshot. This may lead to
inconsistent data when reading out a register that changes during the transmission. Further, the CRC
sent from the driver may be incorrect in this case (but must not), which will lead to the master
repeating the read access. As a workaround, it is advised not to read out quickly changing registers
like XACTUAL, MSCNT or X_ENC during a motion, but instead first stop the motor or check the
position_reached flag to become active, and read out these values afterwards. If possible, use
X_LATCH and ENC_LATCH for a safe readout during motion (e.g. for homing). As the encoder cannot be
guaranteed to stand still during motor stop, only a dual read access and check for identical result
ensures correct X_ENC read data. Therefore it is advised to use the latching function instead. Use the
vzero and velocity_reached flag rather than reading VACTUAL.
www.trinamic.com
TMC5072 DATASHEET (Rev. 1.23 / 2020-JUN-12)
23
5.2 CRC Calculation
An 8 bit CRC polynomial is used for checking both read and write access. It allows detection of up to
eight single bit errors. The CRC8-ATM polynomial with an initial value of zero is applied LSB to MSB,
including the sync- and addressing byte. The sync nibble is assumed to always be correct. The
TMC5072 responds only to correctly transmitted datagrams containing its own slave address. It
increases its datagram counter for each correctly received write access datagram.
𝐶𝑅𝐶 = 𝑥 8 + 𝑥 2 + 𝑥 1 + 𝑥 0
SERIAL CALCULATION EXAMPLE
CRC = (CRC
工商网监
湘ICP备2023018690号
