TMC5130A-TA-T

POWER DRIVER FOR STEPPER MOTORS INTEGRATED CIRCUITS TMC5130A-TA DATASHEET Universal high voltage controller/driver for two-phase bipolar stepper motor. stealthChop™ for quiet movement. Integrated MOSFETs for up to 2 A motor current per coil. With Step/Dir Interface and SPI. APPLICATIONS Textile, Sewing Machines Factory Automation Lab Automation Liquid Handling Medical Office Automation CCTV, Security ATM, Cash recycler POS Pumps and Valves Heliostat Controller FEATURES AND BENEFITS DESCRIPTION 2-phase stepper motors up to 2A coil current (2.5A peak) Motion Controller with sixPoint™ ramp Step/Dir Interface with microstep interpolation microPlyer™ Voltage Range 4.75… 46V DC SPI & Single Wire UART Encoder Interface and 2x Ref.-Switch Input Highest Resolution 256 microsteps per full step stealthChop™ for extremely quiet operation and smooth motion spreadCycle™ highly dynamic motor control chopper dcStep™ load dependent speed control stallGuard2™ high precision sensorless motor load detection coolStep™ current control for energy savings up to 75% Integrated Current Sense Option Passive Braking and freewheeling mode Full Protection & Diagnostics The TMC5130A is a high performance stepper motor controller and driver IC with serial communication interfaces. It combines a flexible ramp generator for automatic target positioning with industries’ most advanced stepper motor driver. Based on TRINAMICs sophisticated stealthChop chopper, the driver ensures absolutely noiseless operation combined with maximum efficiency and best motor torque. High integration, high energy efficiency and a small form factor enable miniaturized and scalable systems for cost effective solutions. The complete solution reduces learning curve to a minimum while giving best performance in class. Compact Size 9x9mm2 TQFP48 package BLOCK DIAGRAM Ref. Switches Reference Switch Processing Interrupts Position Pulse Output Step/Dir IREF optional current scaling TMC5130 Step Multiplyer DAC Reference Motor UART SPI UART Single Wire MOTION CONTROLLER with Linear 6 Point RAMP Generator SPI to Master Programmable 256 µStep Sequencer spreadCycle DRIVER stealthChop Protection & Diagnostics Power Supply Charge Pump CLK Oscillator / Selector Encoder Unit CLK ABN TRINAMIC Motion Control GmbH & Co. KG Hamburg, Germany stallGuard2 coolStep dcStep TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 2 APPLICATION EXAMPLES: HIGH VOLTAGE – MULTIPURPOSE USE The TMC5130A scores with complete motion controlling features, integrated power stages, and power density. It offers a versatility that covers a wide spectrum of applications from battery powered systems up to embedded applications with 2A motor current per coil. The TMC5130A contains the complete intelligence which is required to drive a motor. Receiving target positions the TMC5130A manages motor movement. Based on TRINAMICs unique features stallGuard2, coolStep, dcStep, spreadCycle, and stealthChop, the TMC5130A optimizes drive performance. It trades off velocity vs. motor torque, optimizes energy efficiency, smoothness of the drive, and noiselessness. The small form factor of the TMC5130A keeps costs down and allows for miniaturized layouts. Extensive support at the chip, board, and software levels enables rapid design cycles and fast time-to-market with competitive products. High energy efficiency and reliability deliver cost savings in related systems such as power supplies and cooling. MINIATURIZED DESIGN FOR ONE STEPPER MOTOR Ref. Switches High-Level Interface SPI CPU TMC5130A M An ABN encoder interface with scaler unit and two reference switch inputs are used to control motor movement. Encoder COMPACT DESIGN High-Level Interface FOR UP TO CPU 255 STEPPER MOTORS UART TMC5130A M Addr. TMC5130A An application with 2 stepper motors is shown. Additionally, the ABN Encoder interface and two reference switches can be used for each motor. A single CPU controls the whole system. The CPUboard and the controller / driver boards are highly economical and space saving. M Addr. Up to 255 TMC5130 can be addressed. TMC5130-EVAL EVALUATION BOARD The TMC5130-EVAL is part of TRINAMICs universal evaluation board system which provides a convenient handling of the hardware as well as a user-friendly software tool for evaluation. The TMC5130 evaluation board system consists of three parts: STARTRAMPE (base board), ESELSBRÜCKE (connector board including several test points), and TMC5130-EVAL. ORDER CODES Order code TMC5130A-TA TMC5130-EVAL STARTRAMPE ESELSBRÜCKE www.trinamic.com Description 1-axis dcStep, coolStep, and stealthChop controller/driver; TQFP48 Evaluation board for TMC5130A two phase stepper motor controller/driver Baseboard for TMC5130-EVAL and further evaluation boards. Connector board for plug-in evaluation board system. Size [mm2] 9x9 85 x 55 85 x 55 61 x 38 TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 3 Table of Contents 1 PRINCIPLES OF OPERATION ......................... 5 1.1 KEY CONCEPTS ................................................ 7 1.2 CONTROL INTERFACES ..................................... 7 1.3 SOFTWARE ...................................................... 7 1.4 MOVING AND CONTROLLING THE MOTOR ........ 8 1.5 STEALTHCHOP DRIVER ..................................... 8 1.6 STALLGUARD2 – MECHANICAL LOAD SENSING8 1.7 COOLSTEP – LOAD ADAPTIVE CURRENT CONTROL ...................................................................... 9 1.8 DCSTEP – LOAD DEPENDENT SPEED CONTROL 9 1.9 ENCODER INTERFACE ....................................... 9 2 PIN ASSIGNMENTS .........................................10 2.1 2.2 3 PACKAGE OUTLINE ........................................10 SIGNAL DESCRIPTIONS .................................10 SAMPLE CIRCUITS ..........................................13 3.1 STANDARD APPLICATION CIRCUIT ................13 3.2 REDUCED NUMBER OF COMPONENTS .............14 3.3 INTERNAL RDSON SENSING..........................14 3.4 EXTERNAL 5V POWER SUPPLY ......................15 3.5 PRE-REGULATOR FOR REDUCED POWER DISSIPATION..............................................................16 3.6 5V ONLY SUPPLY..........................................17 3.7 HIGH MOTOR CURRENT .................................18 3.8 DRIVER PROTECTION AND EME CIRCUITRY ...20 4 SPI INTERFACE ................................................21 4.1 4.2 4.3 5 UART SINGLE WIRE INTERFACE ................24 5.1 5.2 5.3 5.4 6 7 SPI DATAGRAM STRUCTURE .........................21 SPI SIGNALS ................................................22 TIMING .........................................................23 DATAGRAM STRUCTURE .................................24 CRC CALCULATION .......................................26 UART SIGNALS ............................................26 ADDRESSING MULTIPLE SLAVES ....................27 REGISTER MAPPING .......................................29 8 SPREADCYCLE AND CLASSIC CHOPPER ... 59 8.1 8.2 8.3 8.4 9 10 SELECTING SENSE RESISTORS ............... 67 11 INTERNAL SENSE RESISTORS ................. 69 12 VELOCITY BASED MODE CONTROL ....... 71 13 DRIVER DIAGNOSTIC FLAGS.................. 73 13.1 13.2 13.3 14 14.1 14.2 14.3 14.4 14.5 15 15.1 15.2 15.3 15.4 15.5 16 16.1 16.2 16.3 17 STEALTHCHOP™ ..............................................51 19 7.5 7.6 www.trinamic.com TEMPERATURE MEASUREMENT ....................... 73 SHORT TO GND PROTECTION ....................... 73 OPEN LOAD DIAGNOSTICS ........................... 73 RAMP GENERATOR ..................................... 74 REAL WORLD UNIT CONVERSION ................. 74 MOTION PROFILES........................................ 75 VELOCITY THRESHOLDS ................................. 77 REFERENCE SWITCHES .................................. 78 EXTERNAL STEP/DIR DRIVER ...................... 79 STALLGUARD2 LOAD MEASUREMENT ... 80 TUNING STALLGUARD2 THRESHOLD SGT ..... 81 STALLGUARD2 UPDATE RATE AND FILTER .... 83 DETECTING A MOTOR STALL ......................... 83 HOMING WITH STALLGUARD......................... 83 LIMITS OF STALLGUARD2 OPERATION .......... 83 COOLSTEP OPERATION ............................. 84 USER BENEFITS............................................. 84 SETTING UP FOR COOLSTEP .......................... 84 TUNING COOLSTEP........................................ 86 STEP/DIR INTERFACE ................................ 87 17.1 TIMING ......................................................... 87 17.2 CHANGING RESOLUTION ............................... 88 17.3 MICROPLYER STEP INTERPOLATOR AND STAND STILL DETECTION ....................................................... 89 18 TWO MODES FOR CURRENT REGULATION ......51 AUTOMATIC SCALING ....................................52 VELOCITY BASED SCALING ............................54 COMBINING STEALTHCHOP AND SPREADCYCLE 56 FLAGS IN STEALTHCHOP................................57 FREEWHEELING AND PASSIVE BRAKING ........58 CHOPPER ................................ 60 CLASSIC CONSTANT OFF TIME CHOPPER ...... 63 RANDOM OFF TIME ...................................... 64 CHOPSYNC2 FOR QUIET 2-PHASE MOTOR .... 65 ANALOG CURRENT CONTROL AIN ............. 66 6.1 GENERAL CONFIGURATION REGISTERS ..........30 6.2 VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET .............................................33 6.3 RAMP GENERATOR REGISTERS .......................35 6.4 ENCODER REGISTERS .....................................40 6.5 MOTOR DRIVER REGISTERS ...........................42 7.1 7.2 7.3 7.4 SPREADCYCLE 18.1 18.2 DIAG OUTPUTS ........................................... 90 STEP/DIR MODE ......................................... 90 MOTION CONTROLLER MODE ........................ 90 DCSTEP .......................................................... 92 19.1 USER BENEFITS............................................. 92 19.2 DESIGNING-IN DCSTEP ................................. 92 19.3 DCSTEP INTEGRATION WITH THE MOTION CONTROLLER .............................................................. 93 19.4 STALL DETECTION IN DCSTEP MODE ............ 93 19.5 MEASURING ACTUAL MOTOR VELOCITY IN DCSTEP OPERATION ................................................... 94 19.6 DCSTEP WITH STEP/DIR INTERFACE ........... 95 TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 20 20.1 20.2 21 SINE-WAVE LOOK-UP TABLE ...................98 USER BENEFITS .............................................98 MICROSTEP TABLE ........................................98 EMERGENCY STOP.......................................99 22 ABN INCREMENTAL ENCODER INTERFACE .............................................................. 100 22.1 ENCODER TIMING ....................................... 101 22.2 SETTING THE ENCODER TO MATCH MOTOR RESOLUTION ............................................................ 101 22.3 CLOSING THE LOOP .................................... 102 23 23.1 DC MOTOR OR SOLENOID .................... 103 SOLENOID OPERATION ............................... 103 24 QUICK CONFIGURATION GUIDE ......... 104 25 GETTING STARTED .................................. 109 25.1 INITIALIZATION EXAMPLES ......................... 109 26 STANDALONE OPERATION .................... 110 27 EXTERNAL RESET ...................................... 113 28 CLOCK OSCILLATOR AND INPUT ........ 113 28.1 28.2 USING THE INTERNAL CLOCK...................... 113 USING AN EXTERNAL CLOCK....................... 114 www.trinamic.com 4 28.3 CONSIDERATIONS ON THE FREQUENCY........ 114 29 ABSOLUTE MAXIMUM RATINGS .......... 115 30 ELECTRICAL CHARACTERISTICS .......... 115 30.1 30.2 30.3 31 31.1 31.2 31.3 31.4 32 32.1 32.2 OPERATIONAL RANGE ................................. 115 DC AND TIMING CHARACTERISTICS ............ 116 THERMAL CHARACTERISTICS........................ 119 LAYOUT CONSIDERATIONS................... 120 EXPOSED DIE PAD ...................................... 120 WIRING GND ............................................ 120 SUPPLY FILTERING...................................... 120 LAYOUT EXAMPLE ....................................... 121 PACKAGE MECHANICAL DATA.............. 123 DIMENSIONAL DRAWINGS TQFP48-EP ..... 123 PACKAGE CODES ......................................... 124 33 DESIGN PHILOSOPHY ............................. 125 34 DISCLAIMER ............................................... 125 35 ESD SENSITIVE DEVICE.......................... 125 36 TABLE OF FIGURES .................................. 126 37 REVISION HISTORY ................................. 128 38 REFERENCES ............................................... 128 TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 1 5 Principles of Operation The TMC5130A motion controller and driver chip is an intelligent power component interfacing between CPU and stepper motor. All stepper motor logic is completely within the TMC5130A. No software is required to control the motor – just provide target positions. The TMC5130A offers a number of unique enhancements which are enabled by the system-on-chip integration of driver and controller. The sixPoint ramp generator of the TMC5130A uses stealthChop, dcStep, coolStep, and stallGuard2 automatically to optimize every motor movement. THE TMC5130A OFFERS THREE BASIC MODES OF OPERATION: MODE 1: Full Featured Motion Controller & Driver All stepper motor logic is completely within the TMC5130A. No software is required to control the motor – just provide target positions. Enable this mode by tying low pin SD_MODE. MODE 2: Step & Direction Driver An external high-performance S-ramp motion controller like the TMC4361 or a central CPU generates step & direction signals synchronized to other components like additional motors within the system. The TMC5130A takes care of intelligent current and mode control and delivers feedback on the state of the motor. The microPlyer automatically smoothens motion. Leave open SD_MODE and SPI_MODE. MODE 3: Simple Step & Direction Driver The TMC5130A positions the motor based on step & direction signals. The microPlyer automatically smoothens motion. No CPU interaction is required; configuration is done by hardware pins. Basic standby current control can be done by the TMC5130A. Optional feedback signals allow error detection and synchronization. Enable this mode by tying low pin SPI_MODE. REFR F AIN_IREF REFL 100n reference switch processing charge pump linear 6 point RAMP generator VCC interface selection (-TA package only) Opt. poscomp out PU=166K pullup resistor to VCC PD=166k pull down resistor to GND 470n SPI™ single wire UART Opt. interrupt out 2R2 CSN PU SCK PU SDI/NAI PU SDO/NAO PU SW_SEL PD Step & Direction pulse generation programmable sine table 4*256 entry Control register set f ace terwire InSingle SWP_DIAG1 PMD current comparator DAC RS BRB Half Bridge 2 N Optional incremental encoder inputs SD_MODE PU PU ISENSE SPI_MODE ENCN PU PU PU=166K pullup to VCC B ENCB TST_MODE 100n Half Bridge 1 Encoder unit A leave open OB2 ISENSE dcStep™ ENCA CLK oscillator/ selector VCC_IO opt. driver enable Figure 1.1 TMC5130A basic application block diagram with motion controller www.trinamic.com GNDP stallGuard2™ INT & position pulse output CLK_IN RS=0R15 allows for maximum coil current; Use low inductance SMD resistor type. Tie BRA and BRB to GND for internal current sensing coolStep™ Diff. Tranceiver opt. ext. clock 10-16MHz +VIO 3.3V or 5V I/O voltage DAC IREF PDD=100k pulldown PMD=50k to VCC/2 SWN_DIAG0 IREF current comparator Stepper driver Protection & diagnostics interface (-TA pckg only) PDD RS GNDP spreadCycle & stealthChop Chopper x BRA ISENSE DRV_ENN SPI interface OA2 Half Bridge 2 tep & coolS Chop th steal driver r moto ol contr n o i t Mo PU 2R2 and 470n are optional filtering components for best chopper precision 5V Voltage regulator 5VOUT ISENSE DRV_ENN VSA +VM OA1 Half Bridge 1 IREF CPO 4.7µ 5VOUT DAC Reference CPI 22n 100n RREF Optional for internal current sensing. RREF=9K1 allows for maximum coil current. VS GNDA 100n optional current scaling DIE PAD VCP F = 60ns spike filter +VM TMC 5130A Stepper motor driver / controller F reference / stop switches OB1 VS 100n +VM S 2 phase stepper motor N TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 6 VCP CPI DIR F AIN_IREF IREF VCC PU=166K pullup resistor to VCC PD=166k pull down resistor to GND CSN PU SCK PU SDI/NAI PU SDO/NAO PU SW_SEL single wire UART Opt. interrupt out PD programmable sine table 4*256 entry Control register set rface te wire InSingle x Stepper driver Protection & diagnostics interface (-TA pckg only) Opt. poscomp out PDD SWN_DIAG0 PMD current comparator DAC GNDP RS BRB stallGuard2™ OB2 Half Bridge 2 INT & position pulse output ISENSE dcStep™ PU=166K pullup to VCC CLK oscillator/ selector PU PU VCC_IO dcStep control Tie DCEN to GND if dcStep is not used leave open VS ISENSE DCIN GNDA DIE PAD SD_MODE SPI_MODE TST_MODE 100n OB1 Half Bridge 1 PU CLK_IN RS=0R15 allows for maximum coil current; Use low inductance SMD resistor type. Tie BRA and BRB to GND for internal current sensing coolStep™ Diff. Tranceiver opt. ext. clock 10-16MHz +VIO 3.3V or 5V I/O voltage DAC IREF PDD=100k pulldown PMD=50k to VCC/2 SWP_DIAG1 IREF current comparator spreadCycle & stealthChop Chopper PU interface selection (-TA package only) RS GNDP DRV_ENN SPI interface BRA ISENSE 100n +VM DRV_ENN SPI™ OA2 Half Bridge 2 tep & coolS Chop th steal driver r o m ot 5V Voltage regulator 2R2 470n ISENSE PU 4.7µ 2R2 and 470n are optional filtering components for best chopper precision +VM OA1 Half Bridge 1 DAC Reference Standstill current reduction CPO VSA 100n step multiplier microPlyer charge pump 5VOUT 5VOUT VS 22n 100n RREF Optional for internal current sensing. RREF=9K1 allows for maximum coil current. DCO 100n optional current scaling DCEN +VM STEP TMC 5130A / TMC 2130 Stepper motor driver F F = 60ns spike filter step & dir input opt. driver enable Figure 1.2 TMC5130A STEP/DIR application diagram +VM VCP 100n CPI charge pump CPO VSA CFG1 CFG2 CFG6 4.7µ 470n TG= toggle with 166K resistor between VCC and GND to detect open pin TG CFG1 TG CFG2 TG CFG3 TG CFG4 TG CFG5 TG DRV_ENN_CFG6 TG TRISTATE configuration (GND, VCC_IO or open) Driver error opt. ext. clock 10-16MHz +VIO 3.3V or 5V I/O voltage DIAG1 PDD DIAG0 PMD CLK_IN AIN_IREF CFG4 CFG1 CFG2 sine table 4*256 entry RS CFG1 spreadCycle & stealthChop Chopper DRV_ENN Stepper driver Protection & diagnostics CFG2 current comparator IREF DAC RS=0R15 allows for maximum coil current; Tie BRA and BRB to GND for internal current sensing current comparator DAC f ace Inter GNDP RS BRB Half Bridge 2 Status out (open drain) OB2 ISENSE Half Bridge 1 CLK oscillator/ selector ISENSE PU VCC_IO GNDA DIE PAD SPI_MODE SD_MODE DCO TST_MODE OB1 VS 100n 100n leave open Figure 1.3 TMC5130A standalone driver application diagram www.trinamic.com BRA GNDP CFG5 x OA2 Half Bridge 2 ISENSE IREF PDD=100k pulldown PMD=50k to VCC/2 Index pulse ISENSE PU Opt. driver enable input IREF CFG0 Configuration interface with TRISTATE detection +VM OA1 Half Bridge 1 DAC Reference le & dCyc sprea hChop t steal driver r o m ot 2R2 CFG0 CFG3 Standstill current reduction VCC 2R2 and 470n are optional filtering components for best chopper precision 100n F step multiplier microPlyer 5V Voltage regulator 5VOUT 5VOUT VS 22n 100n RREF Optional for internal current sensing. RREF=9K1 allows for maximum coil current. F = 60ns spike filter F TMC 5130A / TMC 2130 Standalone Stepper motor driver optional current scaling DIR STEP step & dir input +VM S 2 phase stepper motor N S 2 phase stepper motor N TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 7 1.1 Key Concepts The TMC5130A implements advanced features which are exclusive to TRINAMIC products. These features contribute toward greater precision, greater energy efficiency, higher reliability, smoother motion, and cooler operation in many stepper motor applications. stealthChop™ No-noise, high-precision chopper algorithm for inaudible motion and inaudible standstill of the motor. spreadCycle™ High-precision chopper algorithm for highly dynamic motion and absolutely clean current wave. dcStep™ Load dependent speed control. The motor moves as fast as possible and never loses a step. stallGuard2™ Sensorless stall detection and mechanical load measurement. coolStep™ Load-adaptive current control reducing energy consumption by as much as 75%. microPlyer™ Microstep interpolator for obtaining increased smoothness of microstepping when using the STEP/DIR interface. In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage conditions for enhancing safety and recovery from equipment malfunctions. 1.2 Control Interfaces The TMC5130A supports both, an SPI interface and a UART based single wire interface with CRC checking. Selection of the actual interface is done via the configuration pin SW_SEL, which can be hardwired to GND or VCC_IO depending on the desired interface. 1.2.1 SPI Interface The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus master to the bus slave another bit is sent simultaneously from the slave to the master. Communication between an SPI master and the TMC5130A slave always consists of sending one 40-bit command word and receiving one 40-bit status word. The SPI command rate typically is a few commands per complete motor motion. 1.2.2 UART Interface The single wire interface allows differential operation similar to RS485 (using SWIOP and SWION) or single wire interfacing (leaving open SWION). It can be driven by any standard UART. No baud rate configuration is required. 1.3 Software From a software point of view the TMC5130A is a peripheral with a number of control and status registers. Most of them can either be written only or read only. Some of the registers allow both read and write access. In case read-modify-write access is desired for a write only register, a shadow register can be realized in master software. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 8 1.4 Moving and Controlling the Motor 1.4.1 Integrated Motion Controller The integrated 32 bit motion controller automatically drives the motor to target positions, or accelerates to target velocities. All motion parameters can be changed on the fly. The motion controller recalculates immediately. A minimum set of configuration data consists of acceleration and deceleration values and the maximum motion velocity. A start and stop velocity is supported as well as a second acceleration and deceleration setting. The integrated motion controller supports immediate reaction to mechanical reference switches and to the sensorless stall detection stallGuard2. Benefits are: Flexible ramp programming Efficient use of motor torque for acceleration and deceleration allows higher machine throughput Immediate reaction to stop and stall conditions 1.4.2 STEP/DIR Interface The motor can optionally be controlled by a step and direction input. In this case, the motion controller remains unused. Active edges on the STEP input can be rising edges or both rising and falling edges as controlled by another mode bit (dedge). Using both edges cuts the toggle rate of the STEP signal in half, which is useful for communication over slow interfaces such as optically isolated interfaces. On each active edge, the state sampled from the DIR input determines whether to step forward or back. Each step can be a fullstep or a microstep, in which there are 2, 4, 8, 16, 32, 64, 128, or 256 microsteps per fullstep. A step impulse with a low state on DIR increases the microstep counter and a high decreases the counter by an amount controlled by the microstep resolution. An internal table translates the counter value into the sine and cosine values which control the motor current for microstepping. 1.5 stealthChop Driver stealthChop is a voltage chopper based principle. It guarantees absolutely quiet motor standstill and silent slow motion, except for noise generated by ball bearings. stealthChop can be combined with classic cycle-by-cycle chopper modes for best performance in all velocity ranges. Two additional chopper modes are available: a traditional constant off-time mode and the spreadCycle mode. The constant off-time mode provides high torque at highest velocity, while spreadCycle offers smooth operation and good power efficiency over a wide range of speed and load. spreadCycle automatically integrates a fast decay cycle and guarantees smooth zero crossing performance. The extremely smooth motion of stealthChop is beneficial for many applications. Programmable microstep shapes allow optimizing the motor performance for low cost motors. Benefits of using stealthChop: - Significantly improved microstepping with low cost motors - Motor runs smooth and quiet - Absolutely no standby noise - Reduced mechanical resonances yields improved torque 1.6 stallGuard2 – Mechanical Load Sensing stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall detection as well as other uses at loads below those which stall the motor, such as coolStep loadadaptive current reduction. This gives more information on the drive allowing functions like sensorless homing and diagnostics of the drive mechanics. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 9 1.7 coolStep – Load Adaptive Current Control coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement information to adjust the motor current to the minimum amount required in the actual load situation. This saves energy and keeps the components cool. Benefits are: - Energy efficiency - Motor generates less heat - Less or no cooling - Use of smaller motor power consumption decreased up to 75% improved mechanical precision improved reliability less torque reserve required → cheaper motor does the job Figure 1.4 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example. 0,9 Efficiency with coolStep 0,8 Efficiency with 50% torque reserve 0,7 0,6 0,5 Efficiency 0,4 0,3 0,2 0,1 0 0 50 100 150 200 250 300 350 Velocity [RPM] Figure 1.4 Energy efficiency with coolStep (example) 1.8 dcStep – Load Dependent Speed Control dcStep allows the motor to run near its load limit and at its velocity limit without losing a step. If the mechanical load on the motor increases to the stalling load, the motor automatically decreases velocity so that it can still drive the load. With this feature, the motor will never stall. In addition to the increased torque at a lower velocity, dynamic inertia will allow the motor to overcome mechanical overloads by decelerating. dcStep directly integrates with the ramp generator, so that the target position will be reached, even if the motor velocity needs to be decreased due to increased mechanical load. A dynamic range of up to factor 10 or more can be covered by dcStep without any step loss. By optimizing the motion velocity in high load situations, this feature further enhances overall system efficiency. Benefits are: - Motor does not loose steps in overload conditions - Application works as fast as possible - Highest possible acceleration automatically - Highest energy efficiency at speed limit - Highest possible motor torque using fullstep drive - Cheaper motor does the job 1.9 Encoder Interface The TMC5130A provides an encoder interface for external incremental encoders. The encoder can be used for homing of the motion controller (alternatively to reference switches) and for consistency checks on-the-fly between encoder position and ramp generator position. A programmable prescaler allows the adaptation of the encoder resolution to the motor resolution. A 32 bit encoder counter is provided. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 2 10 Pin Assignments GNDP - OA1 - BRA - OA2 - VS VSA VCP CPI 48 47 46 45 44 43 42 41 40 39 38 37 2.1 Package Outline TST_MODE 1 36 CLK 2 35 CPO CSN_CFG3 3 34 VCC SCK_CFG2 4 33 5VOUT SDI_NAI_CFG1 5 32 GNDA - 6 31 - SDO_NAO_CFG0 7 30 AIN_IREF REFL_STEP 8 29 DRV_ENN_CFG6 REFR_DIR 9 28 SWSEL VCC_IO 10 27 SWP_DIAG1 SD_MODE 11 26 SWN_DIAG0 SPI_MODE 12 25 ENCA_DCIN_CFG5 TMC5130A-TA TQFP-48 9mm x 9mm 17 18 19 20 21 22 BRB - OB2 - VS - 24 16 - ENCN_DCO 15 OB1 ENCB_DCEN_CFG4 14 - 23 13 GNDP PAD = GNDD Figure 2.1 TMC5130A-TA package and pinning TQFP-EP 48 (7x7mm body, 9x9mm with leads) 2.2 Signal Descriptions Pin TST_MODE Number 1 Type DI CLK 2 DI CSN_CFG3 3 SCK_CFG2 4 SDI_NAI_ CFG1 5 N.C. 6, 31, 36 SDO_NAO_ CFG0 7 www.trinamic.com DI (tpu) DI (tpu) DI (tpu) DIO (tpu) Function Test mode input. Tie to GND using short wire. CLK input. Tie to GND using short wire for internal clock or supply external clock. SPI chip select input (negative active) (SPI_MODE=1) or Configuration input (SPI_MODE=0) (tristate detection). SPI serial clock input (SPI_MODE=1) or Configuration input (SPI_MODE=0) (tristate detection). SPI data input (SPI_MODE=1) or Configuration input (SPI_MODE=0) (tristate detection) or Next address input for single wire interface. Unused pins; connect to GND for compatibility to future versions. SPI data output (tristate) (SPI_MODE=1) or Configuration input (SPI_MODE=0) (tristate detection) or Next address output for single wire interface. TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) Pin Number Type REFL_STEP 8 DI REFR_DIR 9 DI VCC_IO 10 SD_MODE 11 DI (pu) SPI_MODE 12 DI (pu) GNDP OB1 13, 14, 20, 43, 15 BRB 17 OB2 19 VS 21, 40 ENCN_DCO 23 DIO ENCB_DCEN_ CFG4 24 DI (tpu) ENCA_DCIN_ CFG5 25 DI (tpu) SWN_DIAG0 26 DIO SWP_DIAG1 27 DIO SWSEL 28 DI (pd) DRV_ENN_ CFG6 29 DI (tpu) AIN_IREF 30 AI GNDA 32 DNC. www.trinamic.com 48 16, 18, 22, 41, 45, 47 11 Function Left reference input (SPI_MODE=1, SD_MODE=0) or STEP input when (SD_MODE=1 or SPI_MODE=0). Right reference input (SPI_MODE=1, SD_MODE=0) or DIR input (SD_MODE=1 or SPI_MODE=0). 3.3V to 5V IO supply voltage for all digital pins. Mode selection input with pullup resistor. When tied low, the internal ramp generator generates step pulses. When tied high, the STEP/DIR inputs control the driver. Integrated pullup resistor. Mode selection input with pullup resistor. When tied low, the chip is in standalone mode and pins have their CFG functions. When tied high, the SPI or UART interfaces are available for control. Integrated pullup resistor. Power GND. Connect to GND plane near pin. Do not connect these pins. Provided to increase creeping distance on PCB in order to allow higher supply voltage without coating. Motor coil B output 1 Sense resistor connection for coil B. Place sense resistor to GND near pin. An additional 100nF capacitor to GND (GND plane) is recommended for best performance. Motor coil B output 2 Motor supply voltage. Provide filtering capacity near pin with short loop to nearest GNDP pin (respectively via GND plane). Encoder N-channel input (SD_MODE=0) or dcStep ready output (SD_MODE=1). With SD_MODE=0, pull to GND or VCC_IO, if the pin is not used. Encoder B-channel input (SD_MODE=0, SPI_MODE=1) or dcStep enable input (SD_MODE=1, SPI_MODE=1) - tie to GND for normal operation (no dcStep). Configuration input (SPI_MODE=0) (tristate detection) Encoder A-channel input (SD_MODE=0, SPI_MODE=1) or dcStep gating input for axis synchronization (SD_MODE=1, SPI_MODE=1) or Configuration input (SPI_MODE=0) (tristate detection). Diagnostics output DIAG0. Interrupt or STEP output for motion controller (SD_MODE=0, SPI_MODE=1). Use external pullup resistor with 47k or less in open drain mode. Single wire I/O (negative) (only with SWSEL=1) Diagnostics output DIAG1. Position compare or DIR output for motion controller (SD_MODE=0, SPI_MODE=1). Use external pullup resistor with 47k or less in open drain mode. Single wire I/O (positive) (only with SWSEL=1) Single wire interface select input, tie high for use of single wire interface (only when SPI_MODE=1). Integrated pull-down resistor. Enable input or configuration / Enable input. The power stage becomes switched off (all motor outputs floating) when this pin becomes driven to a high level. Analog reference voltage for current scaling (optional mode) or reference current for use of internal sense resistors Analog GND. Tie to GND plane. TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) Pin Number 5VOUT 33 VCC 34 CPO 35 CPI 37 VCP 38 VSA 39 OA2 42 BRA 44 OA1 46 Exposed die pad - Type Function Output of internal 5V regulator. Attach 2.2µF or larger ceramic capacitor to GNDA near to pin for best performance. Output to supply VCC of chip. 5V supply input for digital circuitry within chip and charge pump. Attach 470nF capacitor to GND (GND plane). May be supplied by 5VOUT. A 2.2 or 3.3 Ohm resistor is recommended for decoupling noise from 5VOUT. When using an external supply, make sure, that VCC comes up before or in parallel to 5VOUT or VCC_IO, whichever comes up later! Charge pump capacitor output. Charge pump capacitor input. Tie to CPO using 22nF 50V capacitor. Charge pump voltage. Tie to VS using 100nF capacitor. Analog supply voltage for 5V regulator. Normally tied to VS. Provide a 100nF filtering capacitor. Motor coil A output 2 Sense resistor connection for coil A. Place sense resistor to GND near pin. An additional 100nF capacitor to GND (GND plane) is recommended for best performance. Motor coil A output 1 Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane. Serves as GND pin for digital circuitry. *(pu) denominates a pin with pullup resistor; (tpu) denominates a pin with pullup resistor or toggle detection. Toggle detection is active in standalone mode, only (SPI_MODE=0) www.trinamic.com 12 TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 3 13 Sample Circuits The sample circuits show the connection of external components in different operation and supply modes. The connection of the bus interface and further digital signals is left out for clarity. Optional use lower voltage down to 6V VCP 22n 63V CPI CPO AIN_IREF REFR/DIR REFL/STEP 3.1 Standard Application Circuit +VM +VM VS VSA 5VOUT 100n 100n 16V 4.7µ 5V Voltage regulator reference switch processing charge pump DAC Reference 100n 100n 100µF IREF 2R2 VCC CSN SCK SDI/NAI SDO/NAO SWP/DIAG1 SWN/DIAG0 Full Bridge A S N Use low inductivity SMD type, e.g. 1206, 0.5W BRA Driver RSA DIAG / INT out and Single wire interface OB1 SW_SEL opt. ext. clock 12-16MHz +VIO 3.3V or 5V I/O voltage OA2 SPI interface Controller +VIO OA1 TMC5130A 470n Full Bridge B OB2 CLK_IN Encoder unit VCC_IO A B Use low inductivity SMD type, e.g. 1206, 0.5W BRB N RSB leave open Optional incremental encoder inputs GNDP GNDA DIE PAD TST_MODE DRV_ENN ENCN ENCB ENCA SD_MODE SPI_MODE 100n opt. driver enable Figure 3.1 Standard application circuit The standard application circuit uses a minimum set of additional components. Two sense resistors set the motor coil current. See chapter 10 to choose the right sense resistors. Use low ESR capacitors for filtering the power supply. The capacitors need to cope with the current ripple cause by chopper operation. A minimum capacity of 100µF near the driver is recommended for best performance. Current ripple in the supply capacitors also depends on the power supply internal resistance and cable length. VCC_IO can be supplied from 5VOUT, or from an external source, e.g. a low drop 3.3V regulator. In order to minimize linear voltage regulator power dissipation of the internal 5V voltage regulator in applications where VM is high, a different (lower) supply voltage can be used for VSA, if available. For example, many applications provide a 12V supply in addition to a higher driver supply voltage. Using the 12V supply for VSA rather than 24V will reduce the power dissipation of the internal 5V regulator to about 37% of the dissipation caused by supply with the full motor voltage. Basic layout hints Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are recommended for VS filtering. www.trinamic.com stepper motor TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 14 Attention In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by more than one diode drop upon power up or power down. 3.2 Reduced Number of Components Optional use lower voltage down to 6V +VM VSA 5VOUT 100n 5V Voltage regulator 4.7µ VCC Figure 3.2 Reduced number of filtering components The standard application circuit uses RC filtering to de-couple the output of the internal linear regulator from high frequency ripple caused by digital circuitry supplied by the VCC input. For cost sensitive applications, the RC-Filtering on VCC can be eliminated. This leads to more noise on 5VOUT caused by operation of the charge pump and the internal digital circuitry. There is a slight impact on microstep vibration and chopper noise performance. 3.3 Internal RDSon Sensing 5VOUT For cost critical or space limited applications, sense resistors can be omitted. For internal current sensing, a reference current set by a tiny external resistor programs the output current. For calculation of the reference resistor, refer chapter 11. AIN_IREF RREF DAC Reference IREF OA1 Full Bridge A OA2 S N stepper motor BRA Driver OB1 Full Bridge B OB2 BRB Figure 3.3 RDSon based sensing eliminates high current sense resistors www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 15 3.4 External 5V Power Supply When an external 5V power supply is available, the power dissipation caused by the internal linear regulator can be eliminated. This especially is beneficial in high voltage applications, and when thermal conditions are critical. There are two options for using an external 5V source: either the external 5V source is used to support the digital supply of the driver by supplying the VCC pin, or the complete internal voltage regulator becomes bridged and is replaced by the external supply voltage. 3.4.1 Support for the VCC Supply This scheme uses an external supply for all digital circuitry within the driver (Figure 3.4). As the digital circuitry makes up for most of the power dissipation, this way the internal 5V regulator sees only low remaining load. The precisely regulated voltage of the internal regulator is still used as the reference for the motor current regulation as well as for supplying internal analog circuitry. When cutting VCC from 5VOUT, make sure that the VCC supply comes up before or synchronously with the 5VOUT supply to ensure a correct power up reset of the internal logic. A simple schematic uses two diodes forming an OR of the internal and the external power supplies for VCC. In order to prevent the chip from drawing part of the power from its internal regulator, a low drop 1A Schottky diode is used for the external 5V supply path, while a silicon diode is used for the 5VOUT path. An enhanced solution uses a dual PNP transistor as an active switch. It minimizes voltage drop and thus gives best performance. In certain setups, switching of VCC voltage can be eliminated. A third variant uses the VCC_IO supply to ensure power-on reset. This is possible, if VCC_IO comes up synchronously with or delayed to VCC. Use a linear regulator to generate a 3.3V VCC_IO from the external 5V VCC source. This 3.3V regulator will cause a certain voltage drop. A voltage drop in the regulator of 0.9V or more (e.g. LD1117-3.3) ensures that the 5V supply already has exceeded the lower limit of about 3.0V once the reset conditions ends. The reset condition ends earliest, when VCC_IO exceeds the undervoltage limit of minimum 2.1V. Make sure that the power-down sequence also is safe. Undefined states can result when VCC drops well below 4V without safely triggering a reset condition. Triggering a reset upon power-down can be ensured when VSA goes down synchronously with or before VCC. +VM +VM VSA +5V 100n 4.7µ VSA 5V Voltage regulator 5VOUT 5VOUT +5V LL4448 100n 4.7µ VCC MSS1P3 5V Voltage regulator VCC VCC_IO 3.3V regulator 470n 470n 100n 3.3V VCC supplied from external 5V. 5V or 3.3V IO voltage. VCC supplied from external 5V. 3.3V IO voltage generated from same source. +VM VSA 5VOUT 100n 5V Voltage regulator 4.7µ +5V BAT54 10k VCC 2x BC857 or 1x BC857BS 470n 4k7 VCC supplied from external 5V using active switch. 5V or 3.3V IO voltage. Figure 3.4 Using an external 5V supply for digital circuitry of driver (different options) www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 3.4.2 16 Internal Regulator Bridged In case a clean external 5V supply is available, it can be used for complete supply of analog and digital part (Figure 3.5). The circuit will benefit from a well-regulated supply, e.g. when using a +/-1% regulator. A precise supply guarantees increased motor current precision, because the voltage at 5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current control. For best performance, the power supply should have low ripple to give a precise and stable supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case, increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low frequency ripple, this would affect the precision of the motor current regulation as well as add chopper noise. Well-regulated, stable supply, better than +-5% +5V VSA 5VOUT 4.7µ 5V Voltage regulator 10R VCC 470n Figure 3.5 Using an external 5V supply to bypass internal regulator 3.5 Pre-Regulator for Reduced Power Dissipation When operating at supply voltages up to 46V for VS and VSA, the internal linear regulator will contribute with up to 1W to the power dissipation of the driver. This will reduce the capability of the chip to continuously drive high motor current, especially at high environment temperatures. When no external power supply in the range 5V to 24V is available, an external pre-regulator can be built with a few inexpensive components in order to dissipate most of the voltage drop in external components. Figure 3.6 shows different examples. In case a well-defined supply voltage is available, a single 1W or higher power zener diode also does the job. +VM +VM 22k BCX56 or similar 22k BCX56 or similar 4k7 Z5.6V e.g. MM5Z5V6 VSA 5VOUT 470n 16V 4.7µ 5V Voltage regulator 2R2 100R VSA 5VOUT 470n 16V 4.7µ VCC 470n Simple pre-regulator for 24V up to 46V Figure 3.6 Examples for simple pre-regulators www.trinamic.com 5V Voltage regulator 2R2 VCC 470n Simple short circuit protected pre-regulator for 24V up to 46V TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 17 VCP 22n 63V CPI CPO AIN_IREF REFR/DIR REFL/STEP 3.6 5V Only Supply +5V 100n 16V +5V VS VSA 5VOUT 5V Voltage regulator reference switch processing 4.7µ charge pump DAC Reference 100n 100n 100µF IREF VCC OA1 TMC5130A 470n CSN SCK SDI/NAI SDO/NAO SWP/DIAG1 SWN/DIAG0 S N stepper motor Use low inductivity SMD type, e.g. 1206, 0.5W BRA Driver RSA DIAG / INT out and Single wire interface OB1 SW_SEL opt. ext. clock 12-16MHz +VIO 3.3V or 5V I/O voltage OA2 SPI interface Controller +VIO Full Bridge A Full Bridge B OB2 CLK_IN Encoder unit VCC_IO A B Use low inductivity SMD type, e.g. 1206, 0.5W BRB N RSB leave open Optional incremental encoder inputs GNDP GNDA DIE PAD TST_MODE DRV_ENN ENCN ENCB ENCA SD_MODE SPI_MODE 100n opt. driver enable Figure 3.7 5V only operation While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 18 3.7 High Motor Current When operating at a high motor current, the driver power dissipation due to MOSFET switch onresistance significantly heats up the driver. This power dissipation will heat up the PCB cooling infrastructure also, if operated at an increased duty cycle. This in turn leads to a further increase of driver temperature. An increase of temperature by about 100°C increases MOSFET resistance by roughly 50%. This is a typical behavior of MOSFET switches. Therefore, under high duty cycle, high load conditions, thermal characteristics have to be carefully taken into account, especially when increased environment temperatures are to be supported. Refer the thermal characteristics and the layout hints for more information. As a thumb rule, thermal properties of the PCB design become critical for the TQFP-48 at or above 1.2A RMS motor current for increased periods of time. Keep in mind that resistive power dissipation raises with the square of the motor current. On the other hand, this means that a small reduction of motor current significantly saves heat dissipation and energy. An effect which might be perceived at medium motor velocities and motor sine wave peak currents above roughly 1.2A peak is a slight sine distortion of the current wave when using spreadCycle. It results from an increasing negative impact of parasitic internal diode conduction, which in turn negatively influences the duration of the fast decay cycle of the spreadCycle chopper. This is, because the current measurement does not see the full coil current during this phase of the sine wave, because an increasing part of the current flows directly from the power MOSFETs’ drain to GND and does not flow through the sense resistor. This effect with most motors does not negatively influence the smoothness of operation, as it does not impact the critical current zero transition. The effect does not occur with stealthChop. 3.7.1 Reduce Linear Regulator Power Dissipation When operating at high supply voltages, as a first step the power dissipation of the integrated 5V linear regulator can be reduced, e.g. by using an external 5V source for supply. This will reduce overall heating. It is advised to reduce motor stand still current in order to decrease overall power dissipation. If applicable, also use coolStep. A decreased clock frequency will reduce power dissipation of the internal logic. Further a decreased chopper frequency also can reduce power dissipation. 3.7.2 Operation near to / above 2A Peak Current The driver can deliver up to 2.5A motor peak current. Considering thermal characteristics, this only is possible in duty cycle limited operation. When a peak current up to 2.5A is to be driven, the driver chip temperature is to be kept at a maximum of 105°C. Linearly derate the design peak temperature from 125°C to 105°C in the range 2A to 2.5A output current (see Figure 3.8). Exceeding this may lead to triggering the short circuit detection. Limit by lower limit of overtemperature threshold High temperature range 125°C 115°C d de en e m tim om of ec s t r i od no er n dp tio e ra as ea cre Op r in fo Die Temperature 135°C Specified operational range for max. 125°C 105°C 1.5A 1.75A 2A Current limitation Derating for >2A 2.25A 2.5A Peak coil current Figure 3.8 Derating of maximum sine wave peak current at increased die temperature www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 3.7.3 19 Reduction of Resistive Losses by Adding Schottky Diodes Schottky Diodes can be added to the circuit to reduce driver power dissipation when driving high motor currents (see Figure 3.9). The Schottky diodes have a conduction voltage of about 0.5V and will take over more than half of the motor current during the negative half wave of each output in slow decay and fast decay phases, thus leading to a cooler motor driver. This effect starts from a few percent at 1.2A and increases with higher motor current rating up to roughly 20%. As a 30V Schottky diode has a lower forward voltage than a 50V or 60V diode, it makes sense to use a 30V diode when the supply voltage is below 30V. The diodes will have less effect when working with stealthChop due to lower times of diode conduction in the chopper cycle. At current levels below 1.2A coil current, the effect of the diodes is negligible. OA1 Full Bridge A OA2 BRA Driver S N stepper motor RSA OB1 Full Bridge B OB2 1A Schottky Diodes like MSS1P6 or MSS1P3 (VM limited to 30V) BRB RSB Figure 3.9 Schottky diodes reduce power dissipation at high peak currents up to 2A (2.5A) www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 20 3.8 Driver Protection and EME Circuitry Some applications have to cope with ESD events caused by motor operation or external influence. Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset or even a destruction of the motor driver, depending on their energy. Especially plastic housings and belt drive systems tend to cause ESD events of several kV. It is best practice to avoid ESD events by attaching all conductive parts, especially the motors themselves to PCB ground, or to apply electrically conductive plastic parts. In addition, the driver can be protected up to a certain degree against ESD events or live plugging / pulling the motor, which also causes high voltages and high currents into the motor connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the dV/dt caused by ESD events. Larger capacitors will bring more benefit concerning ESD suppression, but cause additional current flow in each chopper cycle, and thus increase driver power dissipation, especially at high supply voltages. The values shown are example values – they might be varied between 100pF and 1nF. The capacitors also dampen high frequency noise injected from digital parts of the application PCB circuitry and thus reduce electromagnetic emission. A more elaborate scheme uses LC filters to de-couple the driver outputs from the motor connector. Varistors in between of the coil terminals eliminate coil overvoltage caused by live plugging. Optionally protect all outputs by a varistor against ESD voltage. 470pF 100V OA1 Full Bridge A OA1 OA2 S N stepper motor Full Bridge A 50Ohm @ 100MHz V1A V1 OA2 50Ohm @ 100MHz 470pF 100V BRA Driver RSA 470pF 100V S N stepper motor V1B 470pF 100V Driver 100nF 16V 470pF 100V OB1 Full Bridge B OB1 Full Bridge B OB2 50Ohm @ 100MHz V2A V2 OB2 50Ohm @ 100MHz 470pF 100V BRB RSB 100nF 16V 470pF 100V V2B 470pF 100V Fit varistors to supply voltage rating. SMD inductivities conduct full motor coil current. Figure 3.10 Simple ESD enhancement and more elaborate motor output protection www.trinamic.com Varistors V1 and V2 protect against inductive motor coil overvoltage. V1A, V1B, V2A, V2B: Optional position for varistors in case of heavy ESD events. TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 4 21 SPI Interface 4.1 SPI Datagram Structure The TMC5130A uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are typically able to communicate using integer multiples of 8 bit. The NCS line of the device must be handled in a way, that it stays active (low) for the complete duration of the datagram transmission. Each datagram sent to the device is composed of an address byte followed by four data bytes. This allows direct 32 bit data word communication with the register set. Each register is accessed via 32 data bits even if it uses less than 32 data bits. For simplification, each register is specified by a one byte address: - For a read access the most significant bit of the address byte is 0. - For a write access the most significant bit of the address byte is 1. Most registers are write only registers, some can be read additionally, and there are also some read only registers. SPI DATAGRAM STRUCTURE MSB (transmitted first) 40 bit 39 ...  8 bit address  8 bit SPI status ... 0   32 bit data 39 ... 32 31 ... 0  to TMC5130A RW + 7 bit address  from TMC5130A 8 bit SPI status 8 bit data 8 bit data 39 / 38 ... 32 38...32 31 ... 24 31...28 27...24 23 ... 16 23...20 19...16 W LSB (transmitted last) 8 bit data 8 bit data 15 ... 8 15...12 7 ... 0 11...8 7...4 3...0 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 4.1.1 Selection of Write / Read (WRITE_notREAD) The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to be added to the address for a write access. The SPI interface always delivers data back to the master, independent of the W bit. The data transferred back is the data read from the address which was transmitted with the previous datagram, if the previous access was a read access. If the previous access was a write access, then the data read back mirrors the previously received write data. So, the difference between a read and a write access is that the read access does not transfer data to the addressed register but it transfers the address only and its 32 data bits are dummies, and, further the following read or write access delivers back the data read from the address transmitted in the preceding read cycle. A read access request datagram uses dummy write data. Read data is transferred back to the master with the subsequent read or write access. Hence, reading multiple registers can be done in a pipelined fashion. Whenever data is read from or written to the TMC5130A, the MSBs delivered back contain the SPI status, SPI_STATUS, a number of eight selected status bits. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 22 Example: For a read access to the register (XACTUAL) with the address 0x21, the address byte has to be set to 0x21 in the access preceding the read access. For a write access to the register (VACTUAL), the address byte has to be set to 0x80 + 0x22 = 0xA2. For read access, the data bit might have any value (-). So, one can set them to 0. action read XACTUAL read XACTUAL write VMAX:= 0x00ABCDEF write VMAX:= 0x00123456 data sent to TMC5130A  0x2100000000  0x2100000000  0xA700ABCDEF  0xA700123456 data received from TMC5130A  0xSS & unused data  0xSS & XACTUAL  0xSS & XACTUAL  0xSS00ABCDEF *)S: is a placeholder for the status bits SPI_STATUS 4.1.2 SPI Status Bits Transferred with Each Datagram Read Back New status information becomes latched at the end of each access and is available with the next SPI transfer. SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32 Bit Name Comment 7 status_stop_r 6 5 4 3 2 1 0 status_stop_l position_reached velocity_reached standstill sg2 driver_error reset_flag RAMP_STAT[1] – 1: Signals stop right switch status (motion controller only) RAMP_STAT[0] – 1: Signals stop left switch status (motion controller only) RAMP_STAT[9] – 1: Signals target reached (motion controller only) RAMP_STAT[8] – 1: Signals target velocity reached (motion controller only) DRV_STATUS[31] – 1: Signals motor stand still DRV_STATUS[24] – 1: Signals stallguard flag active GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT) GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT) 4.1.3 Data Alignment All data are right aligned. Some registers represent unsigned (positive) values, some represent integer values (signed) as two’s complement numbers, single bits or groups of bits are represented as single bits respectively as integer groups. 4.2 SPI Signals The SPI bus on the TMC5130A has four signals: - SCK – bus clock input - SDI – serial data input - SDO – serial data output - CSN – chip select input (active low) The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum of 40 SCK clock cycles is required for a bus transaction with the TMC5130A. If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a 40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips. CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal shift register are latched into the internal control register and recognized as a command from the master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge of CSN are recognized as the command. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 23 4.3 Timing The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional 10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the timing parameters of an SPI bus transaction, and the table below specifies their values. CSN tCC tCL tCH tCH tCC SCK tDU SDI bit39 tDH bit38 bit0 tDO SDO tZC bit39 bit38 bit0 Figure 4.1 SPI timing Hint Usually this SPI timing is referred to as SPI MODE 3 SPI interface timing Parameter SCK valid before or after change of CSN AC-Characteristics clock period: tCLK Symbol tCC fSCK fSCK assumes synchronous CLK tCSH SCK low time tCL SCK high time tCH www.trinamic.com Min Typ Max 10 *) Min time is for synchronous CLK with SCK high one tCH before CSN high only *) Min time is for synchronous CLK only *) Min time is for synchronous CLK only assumes minimum OSC frequency CSN high time SCK frequency using internal clock SCK frequency using external 16MHz clock SDI setup time before rising edge of SCK SDI hold time after rising edge of SCK Data out valid time after falling SCK clock edge SDI, SCK and CSN filter delay time Conditions Unit ns tCLK*) >2tCLK+10 ns tCLK*) >tCLK+10 ns tCLK*) >tCLK+10 ns 4 MHz 8 MHz tDU 10 ns tDH 10 ns tDO no capacitive load on SDO tFILT rising and falling edge 12 20 tFILT+5 ns 30 ns TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 5 24 UART Single Wire Interface The UART single wire interface allows the control of the TMC5130A-TA with any microcontroller UART. It shares transmit and receive line like an RS485 based interface. Data transmission is secured using a cyclic redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can be bridged without the danger of wrong or missed commands even in the event of electro-magnetic disturbance. The automatic baud rate detection and an advanced addressing scheme make this interface easy and flexible to use. 5.1 Datagram Structure 5.1.1 Write Access UART WRITE ACCESS DATAGRAM STRUCTURE each byte is LSB…MSB, highest byte transmitted first 0 … 63 8 bit slave RW + 7 bit sync + reserved 32 bit data address register addr. 56…63 63 … CRC 56 55 … 24…55 data bytes 3, 2, 1, 0 (high to low byte) 24 1 23 … 16…23 register address 16 15 3 … 2 SLAVEADDR 8 1 7 0 6 1 5 0 8…15 Reserved (don’t cares but included in CRC) 4 1 0 0…7 CRC A sync nibble precedes each transmission to and from the TMC5130A and is embedded into the first transmitted byte, followed by an addressing byte. Each transmission allows a synchronization of the internal baud rate divider to the master clock. The actual baud rate is adapted and variations of the internal clock frequency are compensated. Thus, the baud rate can be freely chosen within the valid range. Each transmitted byte starts with a start bit (logic 0, low level on SWIOP) and ends with a stop bit (logic 1, high level on SWIOP). The bit time is calculated by measuring the time from the beginning of start bit (1 to 0 transition) to the end of the sync frame (1 to 0 transition from bit 2 to bit 3). All data is transmitted byte wise. The 32 bit data words are transmitted with the highest byte first. A minimum baud rate of 9000 baud is permissible, assuming 20 MHz clock (worst case for low baud rate). Maximum baud rate is fCLK/16 due to the required stability of the baud clock. The slave address is determined by the register SLAVEADDR. If the external address pin NEXTADDR is set, the slave address becomes incremented by one. The communication becomes reset if a pause time of longer than 63 bit times between the start bits of two successive bytes occurs. This timing is based on the last correctly received datagram. In this case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of bus idle time. This scheme allows the master to reset communication in case of transmission errors. Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treated the same way. This allows a safe re-synchronization of the transmission after any error conditions. Remark, that due to this mechanism an abrupt reduction of the baud rate to less than 15 percent of the previous value is not possible. Each accepted write datagram becomes acknowledged by the receiver by incrementing an internal cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the success of an initialization sequence or single write accesses. Read accesses do not modify the counter. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 5.1.2 25 Read Access UART READ ACCESS REQUEST DATAGRAM STRUCTURE each byte is LSB…MSB, highest byte transmitted first sync + reserved 8 bit slave address RW + 7 bit register address CRC 0...7 8…15 16…23 24…31 31 … CRC 24 0 23 … 16 register address 15 3 … 2 SLAVEADDR 8 1 7 0 6 1 5 0 4 1 0 Reserved (don’t cares but included in CRC) The read access request datagram structure is identical to the write access datagram structure, but uses a lower number of user bits. Its function is the addressing of the slave and the transmission of the desired register address for the read access. The TMC5130A responds with the same baud rate as the master uses for the read request. In order to ensure a clean bus transition from the master to the slave, the TMC5130A does not immediately send the reply to a read access, but it uses a programmable delay time after which the first reply byte becomes sent following a read request. This delay time can be set in multiples of eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the master. In a multi-slave system, set SENDDELAY to min. 2 for all slaves. Otherwise a non-addressed slave might detect a transmission error upon read access to a different slave. UART READ ACCESS REPLY DATAGRAM STRUCTURE each byte is LSB…MSB, highest byte transmitted first 24…55 data bytes 3, 2, 1, 0 (high to low byte) 56…63 … CRC 56 55 CRC … 32 bit data 24 0 23 … 15 3 … 2 16…23 register address 0xFF 8 1 reserved (0) 7 0 6 1 5 0 8…15 4 1 0 0…7 16 sync + reserved 63 0 ...... 63 8 bit slave RW + 7 bit address register addr. The read response is sent to the master using address code %1111. The transmitter becomes switched inactive four bit times after the last bit is sent. Address %11111111 is reserved for read accesses going to the master. A slave cannot use this address. ERRATA IN READ ACCESS A known bug in the UART interface implementation affects read access to registers that change during the access. While the SPI interface takes a snapshot of the read register before transmission, the UART interface transfers the register directly MSB to LSB without taking a snapshot. This may lead to inconsistent data when reading out a register that changes during the transmission. Further, the CRC sent from the driver may be incorrect in this case (but must not), which will lead to the master repeating the read access. As a workaround, it is advised not to read out quickly changing registers like XACTUAL, MSCNT or X_ENC during a motion, but instead first stop the motor or check the position_reached flag to become active, and read out these values afterwards. If possible, use X_LATCH and ENC_LATCH for a safe readout during motion (e.g. for homing). As the encoder cannot be guaranteed to stand still during motor stop, only a dual read access and check for identical result ensures correct X_ENC read data. Use the vzero and velocity_reached flag rather than reading VACTUAL. www.trinamic.com TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15) 26 5.2 CRC Calculation An 8 bit CRC polynomial is used for checking both read and write access. It allows detection of up to eight single bit errors. The CRC8-ATM polynomial with an initial value of zero is applied LSB to MSB, including the sync- and addressing byte. The sync nibble is assumed to always be correct. The TMC5130A responds only to correctly transmitted datagrams containing its own slave address. It increases its datagram counter for each correctly received write access datagram. 𝐶𝑅𝐶 = 𝑥 8 + 𝑥 2 + 𝑥 1 + 𝑥 0 SERIAL CALCULATION EXAMPLE CRC = (CRC