TLD4012

Tr i path Technol ogy, I nc. - Technical Information T LD4012 ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY Technical Information Revision 2.0a – May 2002 GENERAL DESCRIPTION The TLD4012 is an ADSL line driver that provides very low power consumption and low distortion in a very small package as a result of Tripath’s proprietary power processing technology. This device accepts differential input signals from an analog front-end (AFE), and can be used in full-rate (G.dmt), or G.lite systems. This TLD4012 offers a low power consumption of 650mW for full-rate, full-power, CO-side, FDM (non-overlapped) transmissions. APPLICATIONS FEATURES Full-rate or G.lite line cards DSLAMs DLC equipment Central office switches BENEFITS Reduced line card power Reduced system power Increased line card density More ports per cubic foot of system space Improved system performance Simplifies thermal management on PCB Improved reliability Flexible solution Tripath Proprietary Power Processing technology Very low power consumption PCONS(Full-rate ADSL) = 650 mW (typ) PCONS (G.lite) = 390 mW (typ) Low distortion Spurious free dynamic range = -80 dBc 26kHz to 138kHz, RLINE=100Ω, PLINE=19.8dBm Third harmonic distortion = -83 dBc at f = 100 kHz, -82 dBc at f = 500 kHz, -63 dBc at f = 1 MHz, VOUT = 10Vpp (differential), 70Ω load 500 mA minimum output current into a 71Ω load Digitally programmable gain (from 12.8 to 27.8 dB in 1 dB steps) Low-power mode -130 mW typical (line terminated -allows reception of incoming signals) Disabled mode - 10 mW typical (no line termination) Over-temperature and over-current protection with Fault output 5x5 mm 32-pin TQFP with exposed die pad AUTO_CLR VDD5 25 VSS5 16 VDD15 21 VSS15 20 NC INP 3 Power Processing Block 23 OUTP 18 OUTN EN_AC GND INP INN 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 124 23 22 21 20 19 18 9 17 10 11 12 13 14 15 16 NC 30 FBP VDD5 GND FBN FBP REXT NC OUTP NC VDD15 VSS15 NC OUTN NC INN 4 29 FBN G3 9 G2 8 G1 7 G0 RESETB LOPWR EN_AC AUTO_CLR 6 14 15 1 31 GND G0 G1 FORC_BIAS RESETB 2 GND 5 GND 28 GND 12 FORC_BIAS 13 TH_FAULT (Top View) 1 Block Diagram TLD4012 – JB/Rev. 2.0a/05.02 TH_FAULT LOPWR VSS5 FAULT Control & Logic Output current limit 27 REXT 11 FAULT G2 NC G3 Tr i path Technol ogy, I nc. - Technical Information OVERVIEW TLD4012 is a low-power, low-distortion ADSL line driver. This driver offers power consumption ranging from 600mW to 650mW, and provides active, or synthetic, output impedance matching to reduce power consumption. This driver supports an impedance synthesis factor of 2.55 (refer to Figure 1 in the “Test/Applications Circuits” section of this document). The table below summarizes the total power consumption of this device for FDM and overlapped transmissions. Power consumption is reduced by using +/-14V supplies for VDD15/VSS15. High supplies VDD15/VSS15 +/- 14.0 V +/- 15.0 V Power consumption FDM (non-overlapped) (19.8dBm) 650 mW 675 mW Power consumption overlapped (20.4dBm) 710 mW 740 mW Power consumption values given above, and in the following specifications, are for total power consumed from the supplies. This includes power dissipated in the device and power delivered to the load, where the load includes both the line and the matching resistors. Power dissipation in the driver can be determined by subtracting power delivered to the load (line and matching resistors) from the power consumption given in the specifications. The power consumption provided above does not account for loading due to the hybrid which will vary with application. With +/-14V supplies, the maximum output swing, VOUTMAX, is at least 40VPPDIFF over process, temperature and a 5% supply tolerance. This is sufficient for full-power FDM signals with a PAR of 6.45. Note that when using +/-14V supplies with a 5% tolerance the worst-case spurious free dynamic range in the receiving band, and intermodulation distortion may be degraded slightly from the values given in the specifications below. When using 14V nominal supplies the maximum degradation expected when the +/14V supplies are 5% low (minimum +/-13.3V) versus +/-15V supplies 5% low (minimum +/-14.25V) is less than 4dB worse case. All other minimum and maximum specifications in the tables that follow are valid from +/-13.3 to +/-15.75V on VSS15/VDD15. This allows the use of +/-14V supplies with a 5% tolerance for VSS15/VDD15. Lower PAR (peak-to-average ratio) values allow the high voltage supplies (VSS15 and VDD15) to be reduced further, thus reducing power consumption. For example, for a 5.3 PAR VSS15/VDD15 can be reduced to +/-12V. This will reduce power consumption to about 600mW for full-rate, 19.8dBm ADSL FDM (non-overlapped) transmissions. Contact Tripath regarding use of the TLD4012 below +/-13.3V. The recommended values for the line-matching resistors, RS, and the recommended transformer turns ratios to properly match the line are (see Figure 1 in “Test/Application” section below): R S = 1 0Ω N = 1:1.4 The 2.55 synthesis factor of the TLD4012 and the values above for RS and N will result in a match to the 100Ω line impedance. The synthesis factor, k, is defined as the factor by which the line driver multiplies the line-matching resistor, RS. If your application can take advantage of higher synthesis factors, contact Tripath regarding options that can reduce power consumption still further. 2 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information ABSOLUTE MAXIMUM RATINGS SYMBOL VDD5 VSS5 VDD15 VSS15 TJ TA TSTORE TSOLDER IOUT VIN VCMR Positive 5V Supply Voltage Negative 5V Supply Voltage Positive 15V Supply Voltage Negative 15V Supply Voltage Maximum Junction Temperature Operating Free-air Temperature Range Storage Temperature Range Manual soldering for three seconds Reflow soldering for five seconds Output current limit, OUTP or OUTN Input voltage, INP or INN Common mode input voltage range PARAMETER Value +6 -6 + 18 - 18 150 -40 to +85 -55 to 150 350 245 1.1 VSS5 to VDD5 VSS5 to VDD5 UNITS V V V V ºC ºC ºC ºC A V V Notes: 1. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. 2. The absolute value of VDD5 and VSS5 must always be less than or equal to the absolute value of VDD15 and VSS15. 3. The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink and must be connected to a copper plane on the printed circuit board for proper heat dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. This copper plane must be connected to VSS15. See the Application Information section of this document for additional information. 4. Application must insure that VSS15 is applied before VSS5. A clamp diode connected between VSS5 and VSS15 can be used to insure proper application of supply voltages to the TLD4012 (see Test/Application Circuits of this document). Note that only one diode is needed per board for multi-channel line cards, but diode selection should account for the increased current transient that the diode must carry for multiple channels. If the +/-5V rail’s rise time is fast, for example in applications in which the driver’s supplies might be hot-plugged, this method may not be sufficient and supply sequencing may be necessary. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD5 VSS5 VDD15 VSS15 VIH VIL IODLEAK IODMAX Positive 5V Supply Voltage Negative 5V Supply Voltage Positive 15V Supply Voltage Negative 15V Supply Voltage High-level Input Voltage, all digital inputs Low-level Input Voltage, all digital inputs Open drain leakage current, FAULT output Open drain sink current at VOL=0.4V max, FAULT output 1 PARAMETER MIN. + 4.75 - 5.25 + 13.3 - 15.75 2.7 0 TYP. +5 -5 + 15 - 15 MAX. + 5.25 - 4.75 + 15.75 - 13.3 +VDD5 0.8 1 UNITS V V V V V V µA mA Note: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits. 3 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = 25°C, VDD5 = +5V, VSS5 = -5V, VDD15 = +15V, VSS15 = -15V. Also, see Test/Application Circuits. See functional description for details regarding synthetic output impedance. Minimum and maximum limits are guaranteed but may not be 100% tested. SYMBOL PCONS1 PARAMETER Power Consumption CONDITIONS RLOAD = 71Ω, POUT = 154 mW, Full-rate, overlapped ADSL signal, line power = 110 mW (20.4 dBm), with synthetic output impedance (see Fig. 1) MIN. TYP. 740 MAX. UNITS mW PCONS3 PCONS4 PCONS5 PCONS6 IDD5 ISS5 IDD15 ISS15 Iq1 Iq2 Iq1LP Iq2LP VBG VOUTmax IOUTmax ISC VIO ∆VOS VOSHI Ib ∆Ib RIDIFF CIDIFF ROUTLP RLOAD = 50Ω, No Input Signal, LOPWR = Low (see Fig. 1) Power Consumption, no signal, low power RLOAD = 50Ω, No Input Signal, mode LOPWR = High (see Fig. 1) G.Lite RLOAD = 71Ω, POUT = 58 mW, G.Lite signal, line power = 41.6 mW (16.2 dBm). See Fig. 1. Disable mode RESETB = Low Power Consumption, no signal RLOAD = 71Ω, POUT = 154 mW, Full-rate, overlapped ADSL signal with synthetic output impedance (see Fig. 1) Operating Current VSS5 RLOAD = 71Ω, POUT = 154 mW, Full-rate, overlapped ADSL signal with synthetic output impedance (see Fig. 1) Operating Current VDD15 RLOAD = 71Ω, POUT = 154 mW, Full-rate, overlapped ADSL signal with synthetic output impedance (see Fig. 1) Operating Current VSS15 RLOAD = 71Ω, POUT = 154 mW, Full-rate, overlapped ADSL signal with synthetic output impedance (see Fig. 1) Quiescent Current (VDD5 and VSS5) RLOAD = 71Ω, No input signal, LOPWR = Low Quiescent Current (VDD15 and VSS15) RLOAD = 71Ω, No input signal, LOPWR = Low Quiescent Current (VDD5 and VSS5), low RLOAD = 71Ω, No input signal, power mode LOPWR = High Quiescent Current (VDD15 and VSS15), RLOAD = 71Ω, No input signal, low power mode LOPWR = High Band-gap Voltage Operating Current VDD5 Differential Output Voltage, peak-to-peak Gain = 17.8 to 27.8 dB, RLOAD = 71Ω differential Gain = 12.8 to 16.8 dB, RLOAD = 71Ω Differential Output Current RLOAD = 71Ω Short-circuit Output Current Differential Input Offset Voltage Offset Voltage Drift Differential Output Offset Voltage Input Bias Current Differential Input Bias Current Differential Input Resistance Differential Input Capacitance Output Resistance (while in Low-power mode) LOPWR = High Gain = 27.8dB, EN_AC = High, 5kΩ across INN and INP EN_AC = Low -100 REXT = 24kΩ 42 20 500 250 130 390 mW mW mW 10 47.0 mW mA 49.0 mA 8.0 mA 9.5 mA 21.7 1.1 11.0 0.68 1.28 mA mA mA mA V V mA 800 600 30 100 0.5 0.2 800 2 0.5 mA µV µV/°C mV µA µA kΩ pF Ω 4 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information PERFORMANCE CHARACTERISTICS Unless otherwise specified, TA = 25°C, VDD5 = +5V, VSS5 = -5V, VDD15 = +15V, VSS15 = -15V. Also, see Test/Application Circuit. Minimum and maximum limits are guaranteed but may not be 100% tested. SYMBOL BWSS SFDR PARAMETER Spurious Free Dynamic Range in the receive band with respect to –40dBm ADSL transmit signal Intermodulation Distortion CONDITIONS Gain = 20.8 dB, RLINE = 100Ω, PLINE = 20.4 dBm, f = 26 kHz to 138 kHz Gain = 22.8dB @ 50 kHz 10VPPDIFF each tone @ 100 kHz f = 1.025MHz, ∆f = 50kHz SFDR >1MHz Gain = 17.8 to 27.8dB f = 100 kHz f = 500 kHz RLOAD = 71Ω f = 1 MHz VOUT = 10VPPDIFF f = 100 kHz Gain = 17.8 to 27.8dB f = 500 kHz RLOAD = 71Ω f = 1 MHz VOUT = 10VPPDIFF Gain = 17.8 to 27.8dB f = 100 kHz f = 500 kHz RLOAD = 71Ω f = 1 MHz VOUT = 10VPPDIFF VOUT from –10V to +10V, measured from –7.5V to +7.5V, Gain = 20.8 dB Gain = 20.8dB, f = 10 KHz Gain = 20.8dB, f = 10 kHz Gain = 20.8dB, f = 30kHz to 1.1MHz, RIN = 5kΩ Gain = 27.8 dB @ 100 kHz VIN = 100 mVPP @ 500 kHz EN_AC = High @ 1 MHz Gain = 22.8 dB @ 100 kHz VSUPPLYAC = 100 mVPP @ 500 kHz @ 1 MHz Gain = 22.8 dB @ 100 kHz VSUPPLYAC = 100 mVPP @ 500 kHz @ 1 MHz Gain = 22.8 dB @ 100 kHz VSUPPYAC = 100 mVPP @ 500 kHz @ 1 MHz Gain = 22.8 dB @ 100 kHz VSUPPLYAC = 100 mVPP @ 500 kHz @ 1 MHz Output=TBDVPPDIFF, 500kHz MIN. TYP. 10 -80 MAX. UNITS MHz dB Small-signal Bandwidth, -3 dB Gain = 20.8dB, VOUT = 1VPPDIFF IMD -84 -84 -75 -90 -77 -70 -83 -82 -63 -93 -67 -55 200 8 2.9 188 65 83 70 65 70 60 50 60 52 45 82 76 67 75 59 51 0.4 dBc HD2 2 Harmonic Distortion rd nd dBc HD3 3 Harmonic Distortion th dBc HD5 5 Harmonic Distortion dBc SR eN iN eNOTOT CMRR PSRRVDD5 PSRRVSS5 PSRRVDD15 PSRRVSS15 ∆Gain Slew Rate Input Noise Voltage Input Noise Current Overall Output Noise Voltage Common Mode Rejection Ratio Power Supply Rejection Ratio, VDD5 Power Supply Rejection Ratio, VSS5 Power Supply Rejection Ratio, VDD15 Power Supply Rejection Ratio, VSS15 Gain accuracy V/µs nV/ √Hz pA/ √Hz nV/ √Hz dB dB dB dB dB dB -0.4 5 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information PIN DESCRIPTION PIN PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EP EN_AC GND INP INN GND G0 G1 G2 G3 NC FAULT FORC_BIAS TH_FAULT RESETB LOPWR VSS5 NC OUTN NC VSS15 VDD15 NC OUTP NC VDD5 NC REXT GND FBN FBP AUTO_CLR NC Exposed pad PIN FUNCTION Digital input Ground Analog input Analog input Ground Digital input Digital input Digital input Digital input No Connect Digital output (open drain) Digital input Analog input Digital input Digital input Power supply No Connect Analog output No Connect Power supply Power supply No Connect Analog output No Connect Power supply No Connect Analog input Ground Analog input Analog input Digital input No Connect Substrate PIN DESCRIPTION A logic high enables the input common-mode feedback loop, and input bias current cancellation circuit Device Ground Positive terminal of differential input Negative terminal of differential input Device Ground Least Significant Bit of programmable gain select Second Least Significant Bit of programmable gain select Third Least Significant Bit of programmable gain select Most Significant Bit of programmable gain select A logic level high indicates that the device has an output short circuit or that a thermal overload has occurred When set to a logic high, the device forces the bias on regardless of fault conditions Intended for test only When set to a logic high, the device simulates a thermal fault. Intended for test only When AUTO_CLR is set to a logic low, a logic low pulse on RESETB clears the internal Fault latch; otherwise, connect RESETB to VDD5; Logic low puts device in disabled mode When set to logic high, the device goes into low-power mode Negative 5V supply voltage Negative terminal of differential output Negative 15V supply voltage Positive 15V supply voltage Positive terminal of differential output Positive 5V supply voltage Sets over-current limit Device Ground Feedback path for synthesized output impedance Feedback path for synthesized output impedance A logic high forces an immediate reset of the fault latch when RESETB is a logic high. A logic low requires that the RESETB pin be pulsed low to reset the fault latch Exposed pad at underside of device; must be connected to VSS15. Internally connected to the substrate. 6 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information T LD4012 32-PIN TQFP WITH EXPOSED DIE PAD (Top View) AUTO_CLR VDD5 GND FBN FBP NC REXT EN_AC GND INP INN GND G0 G1 G2 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 124 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 NC NC OUTP NC VDD15 VSS15 NC OUTN NC FORC_BIAS RESETB 7 TH_FAULT LOPW R VSS5 NC FAULT G3 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information FUNCTIONAL DESCRIPTION Programmable Gain The gain of the TLD4012 is programmed by the digital inputs G3, G2, G1 and G0. The gain given below is the gain from the input to the output of the TLD4012 with RS=10Ω and RLOAD=50Ω as shown in Figure 1. Note that output voltage swing is limited for gains less than 17.8 dB (see parameter VOUTMAX in Electrical Characteristics). G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 G0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain, dB 12.8 13.8 14.8 15.8 16.8 17.8 18.8 19.8 20.8 21.8 22.8 23.8 24.8 25.8 26.8 27.8 Gain, V/V 4.37 4.90 5.50 6.17 6.92 7.76 8.71 9.77 10.96 12.30 13.80 15.49 17.38 19.50 21.88 24.55 Protection Circuits The TLD4012 has built-in protection against over-temperature and over-current conditions. There are two modes in which the fault protection circuits can operate depending on the state of the AUTO_CLR pin. The two modes operate as follows: 1. AUTO_CLR pin is set to a logic low level - When the device goes into an over-temperature or overcurrent condition, the FAULT pin is latched into a logic HIGH state indicating a fault condition. When this occurs, the amplifier outputs enter disable mode and are in a high-impedance state provided OUTP and OUTN are not driven externally to exceed approximately +/-2.0Vppdiff. After the fault condition has been removed, a logic LOW pulse must be applied to the RESETB pin for a minimum of 100 ns to reset the FAULT output to a logic low level, and re-enable the output to a normal, low impedance mode. 2. AUTO_CLR pin is set to a logic high level - After a fault occurs and the fault condition is removed, the device will enable the outputs, and reset the FAULT pin every 1 micro-second. In this mode the fault latch is reset internally on power up so an external reset is not required. Note that in the case of an over-current fault, if the cause of the over-current condition has not actually cleared, the output stage will cycle continuously between the normal, enabled state, and the fault, or disabled state. In this mode the FAULT output pin can cycle continuously until the cause of the fault is cleared. If this operation is not desirable, see the “Over-current Protection” section below. If a microcontroller or DMT processor is used to monitor the FAULT output, and to control the device, AUTO_CLR should be set to a logic low level. Otherwise, AUTO_CLR should be set to a logic high level and the device will reset itself on power-up and after a fault condition has been removed. 8 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information Over-temperature Protection An over-temperature fault occurs if the junction temperature of the device exceeds approximately 160°C. When a fault occurs the TLD4012 output driver enters the disabled mode, and asserts a logic HIGH on the FAULT pin. An over-temperature fault can only be cleared after the junction temperature drops below approximately 120°C. Over-current Protection An over-current fault occurs when current delivered from either of the output pins, OUTP or OUTN, exceeds the current limit value. When a fault occurs, the TLD4012’s output driver enters disabled mode, and asserts a logic HIGH on the FAULT pin. The level at which the current limit occurs is set by REXT. The relationship between the over-current limit and REXT is: REXT = 19.2 / ICL , where ICL is the short circuit current limit in A, and REXT is in kΩ. The acceptable range of REXT is 19.2 kΩ to 32 kΩ, or 1.0 A to 600 mA, respectively. A typical value for REXT in most ADSL applications is 24kΩ which results in an 800mA current limit. If the device is operated with AUTO_CLR set to a logic high level, and an over-current condition occurs, the device will cycle between the fault state and normal state as described in the “Protection Circuits” section above. If the cycling mode described above is not desirable, the over-current limit can be set to 1.0 A, (i.e. REXT = 19.2 kΩ). With this current limit value, the device will not enter the cycling mode if a short occurs on the twisted pair because the matching resistors, RS, will limit the current to less than 1.0A. The overtemperature protection will eventually act to protect the device, and in the event of a short on the board, the over-current protection will still take affect to protect the device. Low-Power Mode The TLD4012 can be placed into a low-power consumption mode by asserting a logic HIGH on the LOPWR input. In this mode the device consumes approximately 130 mW, but still provides a low output resistance to allow reception of incoming signals. Disable Mode The TLD4012 can be placed in a lower power disabled mode by holding RESETB to a logic low level. In this mode the power dissipation is only 10 mW, and the line is not terminated so reception of incoming signals is not reliable. In this mode the outputs are high impedance as long as they are not driven externally more than about +/-2.0Vppdiff around ground. Beyond this voltage the outputs become low impedance. Upon power-up the TLD4012 does not exit disabled mode until the VDD5/VSS5 power supply pins are greater than about 4.2V. It will automatically enter disabled mode when the VDD5/VSS5 supply pins are less than about 4.0V. Input Common-mode Feedback Loop and Input-Bias-Current Cancellation The TLD4012 has a common-mode feedback loop on the input stage and an input-bias-current cancellation circuit. Setting the EN_AC input to a logic high level enables both features. When enabled the common-mode feedback loop will set the common-mode input voltage. This allows use of a differential filter (i.e. not referenced to ground) between the AFE and the driver. When the common-mode feedback loop is disabled (EN_AC = Low) the application should replace the single input resistor, RIN, shown in Figure 1 with two input resistors connected from the inputs, INN and INP, to ground. 9 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information TEST/APPLICATION CIRCUIT Synthesized Output Impedance Device TLD4012 employs synthesized output impedance with a synthesis factor of 2.55. As with any line driver, using synthesized impedance reduces power consumption, but may compromise receive-signal strength in some applications. The 10Ω matching resistors will properly terminate a 100Ω line when a 1:1.4 transformer is used (see Figure 1). Note that, for simplicity, the hybrid and other filtering associated with the receive signal path are not shown. VDD5 VSS5 VDD15 VSS15 10µF 0.1 µF 10µF 0.1 µF 1µF 0.1 µF D1 1 µF 0.1 µF TLD4012 VDD5 25 VSS5 16 VDD15 21 VSS15 20 30 FBP RLOAD From Analog Front End CIN RIN INP 3 Power Processing Block 23 OUTP 18 OUTN RS RLINE RS INN 4 CIN G3 G2 G1 G0 RESETB LOPW R EN_AC AUTO_CLR 9 8 7 6 14 15 1 31 29 FBN Output current limit 27 REXT 11 FAULT VLOGIC 25k 2 GND 5 GND 28 GND 12 13 FORC_BIAS TH_FAULT REXT T1 Micro Controller Control & Logic T1 = 1:1.4 Transformer CIN = 0.1 µF RIN = 5 kΩ R S = 10 Ω REXT = 24 KΩ RLINE = 100 Ω D1 = One UPS840 schottky diode or equivalent per 48 drivers. Test/Application Circuit – with synthesized output impedance, TLD4012 Figure 1 10 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information APPLICATION INFORMATION Power Dissipation Derating for 5x5mm TQFP with Exposed Die Pad For operating at ambient temperatures above 25°C the device power dissipation, PDISS, must be de-rated based on a 150°C maximum junction temperature TJ (max) as given by the following equation: PDISS = (TJ(max) – TA)/θJA Where θJA of the package is determined from the table, and TA is the ambient temperature. Airflow (LFPM) 0 200 500 θJA,C/W (Copper Pad Soldered To PCB) 5x5mm 34.5 29.1 27.2 Values apply when the exposed pad is soldered to a JEDEC standard test board. Note that PDISS is the power dissipated on the chip, not PCONS which is the power consumed from the supplies. The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink and should be connected to a copper plane on the printed circuit board for optimum heat dissipation. This copper plane must be connected to VSS15. 11 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information PACKAGE INFORMATION 5x5mm TQFP with exposed die pad D1 f1 E1 f2 Pin 1 e b A2 c L1 L S A1 All dimensions in mm BODY SIZE D1 5. 0 E1 5. 0 LEAD COUN T STAN D-OFF A1 BOD Y THIC K NESS A2 1.0 LEAD LENGT H L1 1.0 LEAD WIDT H b 0.22 LEAD THIC K NESS c 0.15 LEAD PITC H e 0.5 32 0.04 LEAD BOTTO M ATTAC H L 0.450.75 LEAD SHOU L DER S Min0.2 EXPOSE D PAD (BOTTOM SIDE) f1 3.5 f2 3.5 12 TLD4012 – JB/Rev. 2.0a/05.02 Tr i path Technol ogy, I nc. - Technical Information Tripath and Digital Power Processing are trademarks of Tripath Technology, Inc. Other trademarks referenced in this document are owned by their respective companies. Tripath Technology, Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application of use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. TRIPATH’S PRODUCT ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHONOLOGY, INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury of the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 2. Contact Information TRIPATH TECHNOLOGY, INC 2560 Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.tripath.com/cont_s.htm For more Technical Information, please visit us @ www.tripath.com/data.htm 13 TLD4012 – JB/Rev. 2.0a/05.02