US3004CW

US3004/US3005 5 BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH DUAL LDO CONTROLLER FEATURES Meets Latest VRM 8.4 Specification for PIII Provides Single Chip Solution for Vcore, GTL+ and Clock Supply On board DAC programs the output voltage from 1.3V to 3.5V. The US3004/5 remains on for VID code of (11111). Dual linear regulator controller on board for 1.5V GTL+ and 2.5V clock supplies Loss less Short Circuit Protection Synchronous operation allows maximum efficiency Patented architecture allows fixed frequency operation as well as 100% duty cycle during dynamic load Min part count, No external Compensation Soft Start High current totem pole driver for direct driving of the external Power MOSFET Power Good function DESCRIPTION The US3004/5 series of controller ICs are specifically designed to meet Intel specification for Pentium III™ microprocessor applications as well as the next generation P6 family processors. The IC provides a single chip controller IC for the Vcore , GTL+ and clock supplies required for the Pentium III applications. These devices feature a patented topology that in combination with a few external components as shown in the typical application circuit ,will provide in excess of 20A of output current for an on- board DC/DC converter while automatically providing the right output voltage via the 5 bit internal DAC meeting the latest VRM specification .These products also feature, loss less current sensing by using the Rds-on of the high side Power MOSFET as the sensing resistor, a Power Good window comparator that switches its open collector output low when the output is outside of a ±10% window. Other features of the device are ; Undervoltage lockout for both 5V and 12V supplies, an external programmable soft start function as well as programming the oscillator frequency by using an external capacitor. APPLICATIONS Pentium III & next generation processor DC to DC converter application Low cost Pentium with AGP TYPICAL APPLICATION L1 L2 Q1 C5 C13 C3 R2 R3 R13 R1 C7 R12 Q2 R4 C10 5V Vout 3 3.3V C4 C6 R10 8 CS+ 9 HDrv 7 CS11 LDrv 10 Gnd 14 Vfb3 Lin1 2 Q3 C11 12 V12 1 Ct C1 13 SS C2 D4 15 D3 16 D2 17 D1 18 D0 19 PGd 6 Vfb2 4 5 V5 R7 R11 C15 Vfb1 3 Lin2 20 Q4 C9 R14 3004app2-1.9 Vout 1 12V US3004 R8 Vout 2 C12 VID4 VID3 VID2 VID1 VID0 3.3V R5 R6 R9 C14 R15 Power Good C8 Notes: Pentium III is trade mark of Intel Corp. PACKAGE ORDER INFORMATION Ta (°C) 0 TO 70 0 TO 70 Device US3004CW US3005CW Package 20 pin Plastic SOIC WB 20 pin Plastic SOIC WB 2.5V Output Voltage Adjustable Fixed Rev. 1.2 12/8/00 4-1 US3004,US3005 ABSOLUTE MAXIMUM RATINGS V5 supply Voltage ........................................... 10V V12 Supply Voltage ............................................ 20V Storage Temperature Range ................................. -65 TO 150°C Operating Junction Temperature Range .......... 0 TO 125°C PACKAGE INFORMATION 20 PIN WIDE BODY PLASTIC SOIC (W) TOP VIEW Ct / En 1 Lin1 2 Vfb1 3 Vfb2 4 V5 5 PGd 6 CS- 7 CS+ 8 HDrv 9 Gnd 10 20 Lin2 19 D0 18 D1 17 D2 16 D3 15 D4 14 Vfb3 13 SS 12 V12 11 LDrv θJA =85°C/W Unless otherwise specified ,these specifications apply over ,V12 = 12V, V5 = 5V and Ta=0 to 70°C. Typical values refer to Ta =25°C. Low duty cycle pulse testing are used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER SYM TEST CONDITION VID Section DAC output voltage (note 1) DAC Output Line Regulation DAC Output Temp Variation VID Input LO VID Input HI VID input internal pull-up resistor to V5 Power Good Section Under voltage lower trip point Vout ramping down Under voltage upper trip point Vout ramping up UV Hysterises Over voltage upper trip point Vout ramping up Over voltage lower trip point Vout ramping down OV Hysterises Power Good Output LO RL=3mA Power Good Output HI RL=5K pull up to 5V Soft Start Section Soft Start Current CS+ =0V , CS- =5V MIN 0.99Vs TYP Vs MAX 1.01Vs 0.1 0.5 0.4 2 27 UNITS V % % V V kΩ ELECTRICAL SPECIFICATIONS 0.89Vs .015Vs 1.09Vs .015Vs 4.8 0.90Vs 0.92Vs .02Vs 1.10Vs 1.08Vs .02Vs 0.91Vs .025Vs 1.11Vs .025Vs 0.4 V V V V V V V V uA 10 4-2 Rev. 1.2 12/8/00 US3004/US3005 UVLO Section UVLO Threshold-12V UVLO Hysterises-12V UVLO Threshold-5V UVLO Hysterises-5V Error Comparator Section Input bias current Input Offset Voltage Delay to Output Current Limit Section C.S Threshold Set Current C.S Comp Offset Voltage Hiccup Duty Cycle Supply Current Operating Supply Current Supply ramping up Supply ramping up 9.2 0.3 4.1 0.2 10 0.4 4.3 0.3 10.8 0.5 4.5 0.4 2 +2 100 200 240 +5 2 V V V V uA mV nS uA mV % -2 Vdiff=10mV 160 -5 Css=0.1 uF CL=3000pF V5 V12 20 14 70 70 200 220 V5 1.477 1.500 2.500 2 50 1.522 100 130 300 250 0.2 mA nS nS nS Khz V V V V uA mA Output Drivers Section Rise Time CL=3000pF Fall Time CL=3000pF Dead band Time CL=3000pF Oscillator Section Osc Frequency Ct=150pF Osc Valley Osc Peak LDO Controller Section Vfb1 & Vfb2 (US3004) Vfb2 (US3005) Vfb1 (US3005) Input bias current Lin1 or Lin2 Drive Current Note 1: Vs refers to the set point voltage given in Table 1. D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vs 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 100 190 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vs 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 Table 1 - Set point voltage vs. VID codes Rev. 1.2 12/8/00 4-3 US3004,US3005 PIN DESCRIPTIONS PIN# PIN SYMBOL 19 D0 18 17 16 15 D1 D2 D3 D4 Pin Description LSB input to the DAC that programs the output voltage. This pin can be pulled up externally by a 10k resistor to either 3.3V or 5V supply. Input to the DAC that programs the output voltage.This pin can be pulled up externally by a 10kΩ resistor to either 3.3V or 5V supply. Input to the DAC that programs the output voltage.This pin can be pulled up externally by a 10k resistor to either 3.3V or 5V supply. MSB input to the DAC that programs the output voltage.This pin can be pulled up externally by a 10k resistor to either 3.3V or 5V supply. This pin selects a range of output voltages for the DAC.When in the LOW state the range is 1.3V to 2.05V. For VID codes of all "1" the US3004 keeps all the outputs on. This pin is an open collector output that switches LO when the output of the converter is not within ±10% (typ) of the nominal output voltage.When PWRGD pin switches LO the sat voltage is less than 0.4V at 3mA. This pin is connected directly to the output of the Core supply to provide feedback to the Error comparator. This pin is connected to the Drain of the power MOSFET of the Core supply and it provides the positive sensing for the internal current sensing circuitry. An external resistor programs the C.S threshold depending on the Rds of the power MOSFET. An external capacitor is placed in parallel with the programming resistor to provide high frequency noise filtering. This pin is connected to the Source of the power MOSFET for the Core supply and it provides the negative sensing for the internal current sensing circuitry. This pin provides the soft start for the switching regulator. An internal current source charges an external capacitor that is conected from this pin to the GND which ramps up the outputs of the switching regulator, preventing the outputs from overshooting as wellas limiting the input current. The second function of the Soft Start cap is to provide long off time (HICCUP) for the synchronous MOSFET during current limiting. This pin programs the oscillator frequency in the range of 50 kHZ to 500kHZ with an external capacitor connected from this pin to the GND. This pin controls the gate of an external transistor for either the GTL+ linear regulator or Clock supply. This pin provides the feedback for the linear regulator that its output drive is Lin1 pin. For US3005, this pin is connected to the 2.5V regulator, eliminating the external dividers. This pin controls the gate of an external transistor for either the GTL+ linear regulator or Clock supply. This pin provides the feedback for the linear regulator that its output drive is Lin2 pin. This pin serves as the ground pin and must be conected directly to the ground plane. A high frequency capacitor (0.1 to 1 uF) must be connected from V5 and V12 pins to this pin for noise free operation. Output driver for the synchronous power MOSFET. Output driver for the high side power MOSFET. This pin is connected to the 12 V supply and serves as the power Vcc pin for the output drivers.A high frequency capacitor (0.1 to 1 uF) must be connected directly from this pin to GND pin in order to supply the peak current to the power MOSFET during the transitions. 5V supply voltage. 6 PGd 14 8 Vfb3 CS+ 7 13 CSSS 1 2 3 Ct Lin1 Vfb1 20 4 10 Lin2 Vfb2 Gnd 11 9 12 LDrv HDrv V12 5 V5 4-4 Rev. 1.2 12/8/00 US3004/US3005 BLOCK DIAGRAM Vfb3 Enable V12 Vset Enable V12 UVLO V5 + Vset HDrv PWM Control V12 D0 D1 D2 D3 D4 Vfb2 5Bit DAC, Ctrl Logic Enable Slope Comp LDrv Osc CSOver Current Soft Start & Fault Logic CS+ 200uA Enable Ct / En SS Lin2 1.1Vset PGd 1.5V Lin1 0.9Vset Gnd Vfb1 3004blk2-1.3 Figure 1 - Simplified block diagram of the US3004. Rev. 1.2 12/8/00 4-5 US3004,US3005 TYPICAL APPLICATION Pentium III L1 L2 Q1 R16 C5 C13 C3 R2 R3 R1 C7 Q2 R4 R12 R13 C16 C10 R17 5V Vout 3 3.3V C4 C6 Q3 C11 R18 12 V12 1 Ct C1 13 SS C2 D4 15 D3 16 D2 17 D1 18 D0 19 PGd 6 Vfb2 4 5 V5 8 CS+ 9 HDrv 7 CS11 LDrv 10 Gnd 14 Vfb3 Lin1 2 R7 R11 C15 Vfb1 3 Lin2 20 C9 R14 3004app2-2.0 Vout 1 12V US3004 R8 Q4 C12 Vout 2 VID4 VID3 VID2 VID1 VID0 3.3V R5 R9 C14 R15 Power Good C8 Figure 2- Typical application of US3004 or 3005 in an on board DC-DC converter providing the Core , GTL+, and Clock supplies for the Pentium II microprocessor. PART # US3004 US3005 R7 VALUE SEE PARTS LIST SHORT R8 VALUE SEE PARTS LIST OPEN Table2, describing the differences between 3004 and 3005 applications. 4-6 Rev. 1.2 12/8/00 US3004/US3005 US3004/5 Application Parts List Q1 Q2 Q3 Q4 L1 L2 C1 C2,6 C3 C4 C5 C7,14,15 C8 C9 C10 C11 C12 C13 C16 R1 R2,3,4 R5,15 R7,12 R8 R9,11,14 R13 R16 R17 R18 MOSFET MOSFET Bipolar Trans, GP MOSFET Inductor Inductor Capacitor, Ceramic Capacitor, Ceramic Capacitor, Electrolytic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Ceramic Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 1 1 1 1 1 1 1 2 2 1 1 3 1 1 6 1 1 1 1 1 3 2 2 1 3 1 1 1 1 IRL3103s, TO263 package IRL3103D1S, TO263 package MPS2222A, SOT23 package IRLR024, TO252 package L=1uH, 5052 core with 4 turns of 1.0mm wire L=2.7uH, 5052B core with 7 turns of 1.2mm wire 150pF, 0603 1uF, 0603 10MV1200GX, 1200uF,10V 1uF, 0805 220pF, 0603 1000pF, 0603 0.1uF, 0603 6MV1000GX, 1000uF,6.3V 6MV1500GX, 1500uF,6.3V 6MV150GX, 150uF,6.3V 6MV1000GX, 1000uF,6.3V 10MV470GX, 470uF,10V 4.7uF, 1206 3.3kΩ, 5%, 0603 4.7Ω, 5%, 1206 10kΩ, 5%, 0603 100Ω, 1%, 0603 150Ω, 1%, 0603 100Ω, 5%, 0603 22kΩ, 1%, 0603 220Ω, 1%, 0603 330Ω, 1%, 0603 10Ω, 5%, 0603 IR IR MOT IR Micro Metal Micro Metal Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU Transient Voltage. Note 2: R14 and R15 set the 1.5V approximately 1% higher to account for the trace resistance drop. Rev. 1.2 12/8/00 4-7 US3004,US3005 TYPICAL APPLICATION Pentium with AGP L1 L2 Q1 R16 C5 C13 C3 R2 R3 R1 C7 Q2 R4 R12 R13 C16 C10 R17 5V Vout 3 3.3V C4 C6 C9 R18 12 V12 1 Ct C1 13 SS C2 D4 15 D3 16 D2 17 D1 18 D0 19 PGd 6 Vfb2 4 5 V5 8 CS+ 9 HDrv 7 CS11 LDrv 10 Gnd 14 Vfb3 Lin1 2 Q3 C11 R7 R11 C15 Vfb1 3 Lin2 20 R9 R14 3.3V R5 C14 3004app3-1.4 12V US3004 Q4 R8 3.3V C12 VID4 VID3 VID2 VID1 VID0 R15 Power Good C8 Figure 3- Typical application of US3004 in a Pentium with AGP where the power dissipation of the 3.3V linear regulator is equally distributed between Q3 and Q4 pass transistors. This equal distribution is possible by accurately regulating the first regulator using the US3004 linear controller and its internal 1% reference voltage while the second controller regulates the output of the first regulator from 4.17V to 3.3V, thereby distributing the power dissipation equally. 4-8 Rev. 1.2 12/8/00 US3004/US3005 US3004 Application Parts List Ref Desig Q1 Q2 Q3,4 L1 L2 C1 C2,6 C3 C4 C5 C7,14,15 C8 C9 C10 C11 C12 C13 C16 R1 R2,3,4 R5,15 R7 R8 R9,11,14 R12 R13 R16 R17 R18 Description MOSFET MOSFET MOSFET Inductor Inductor Capacitor, Ceramic Capacitor, Ceramic Capacitor, Electrolytic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Electrolytic Capacitor, Ceramic Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Qty 1 1 2 1 1 1 2 2 1 1 3 1 1 6 1 1 1 1 1 3 2 1 2 3 1 1 1 1 1 Part # IRL3103s, TO263 package IRL3103D1S, TO263 package IRL3303S, TO263 package L=1uH, 5052 core with 4 turns of 1.0mm wire L=2.7uH, 5052B core with 7 turns of 1.2mm wire 150pF, 0603 1uF, 0603 10MV1200GX, 1200uF,10V 1uF, 0805 220pF, 0603 1000pF, 0603 0.1uF, 0603 6MV1000GX, 1000uF,6.3V 6MV1500GX, 1500uF,6.3V, 6MV150GX, 150uF,6.3V 6MV1000GX, 1000uF,6.3V 10MV470GX, 470uF,10V 4.7uF, 1206 3.3kΩ, 5%, 0603 4.7Ω, 5%, 1206 10kΩ, 5%, 0603 267Ω, 1%, 0603 150Ω, 1%, 0603 100Ω, 5%, 0603 100Ω, 1%, 0603 22kΩ, 1%, 0603 220Ω, 1%, 0603 330Ω, 1%, 0603 10Ω, 5%, 0603 Manuf IR IR IR Micro Metal Micro Metal Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU Transient Voltage. Rev. 1.2 12/8/00 4-9 US3004,US3005 Application Information An example of how to calculate the components for the application circuit is given below. Assuming, two sets of output conditions that this regulator must meet, a) Vo=2.8V , Io=14.2A, ∆Vo=185mV, ∆Io=14.2A b) Vo=2V , Io=14.2A, ∆Vo=140mV, ∆Io=14.2A The regulator design will be done such that it meets the worst case requirement of each condition. Output Capacitor Selection The first step is to select the output capacitor. This is done primarily by selecting the maximum ESR value that meets the transient voltage budget of the total ∆Vo specification. Assuming that the regulators DC initial accuracy plus the output ripple is 2% of the output voltage, then the maximum ESR of the output capacitor is calculated as : ESR ≤ 100 = 7 mΩ 14.2 The Sanyo MVGX series is a good choice to achieve both the price and performance goals. The 6MV1500GX , 1500uF, 6.3V has an ESR of less than 36 mΩ typ . Selecting 6 of these capacitors in parallel has an ESR of ≈6 mΩ which achieves our low ESR goal. Other type of Electrolytic capacitors from other manufacturers to consider are the Panasonic “FA” series or the Nichicon “PL” series. Reducing the Output Capacitors Using Voltage Level Shifting Technique The trace resistance or an external resistor from the output of the switching regulator to the Slot 1 can be used to the circuit advantage and possibly reduce the number of output capacitors, by level shifting the DC regulation point when transitioninig from light load to full load and vice versa. To accomplish this, the output of the regulator is typically set about half the DC drop that results from light load to full load. For example, if the total resistance from the output capacitors to the Slot 1 and back to the GND pin of the device is 5mΩ and if the total ∆I, the change from light load to full load is 14A, then the output voltage measured at the top of the resistor divider which is also connected to the output capacitors in this case, must be set at half of the 70 mV or 35mV higher than the DAC voltage setting. This in tentional voltage level shifting during the load transient eases the requirement for the output capacitor ESR at the cost of load regulation. One can show that the new ESR requirement eases up by half the total trace resistance. For example, if the ESR requirement of the output capacitors without voltage level shifting must be 7mΩ then after level shifting the new ESR will only need to be 9.5mΩ if the trace resistance is 5mΩ (7+5/2=9.5). However, one must be careful that the combined “voltage level shifting” and the transient response is still within the maximum tolerance of the Intel specification. To insure this, the maximum trace resistance must be less than: Rs≤ 2(Vspec - 0.02*Vo - ∆Vo)/∆I Where : Rs=Total maximum trace resistance allowed Vspec=Intel total voltage spec Vo=Output voltage ∆Vo=Output ripple voltage ∆I=load current step For example, assuming: Vspec=±140 mV=±0.1V for 2V output Vo=2V ∆Vo=assume 10mV=0.01V ∆I=14.2A Then the Rs is calculated to be: Rs≤ 2(0.140 - 0.02*2 - 0.01)/14.2=12.6mΩ However, if a resistor of this value is used, the maximum power dissipated in the trace (or if an external resistor is being used) must also be considered. For example if Rs=12.6 m Ω , t he power dissipated is (Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to be dissipated in a system. So, if the Rs=5mΩ, then the power dissipated is about 1W which is much more acceptable. If level shifting is not implemented, then the maximum output capacitor ESR was shown previously to be 7mΩ which translated to ≈ 6 of the 1500uF, 6MV1500GX type Sanyo capacitors. With Rs=5mΩ, the maximum ESR becomes 9.5mΩ which is equivalent to ≈ 4 caps. Another important consideration is that if a trace is being used to implement the resistor, the power dissipated by the trace increases the case temperature of the output capacitors which could seriously effect the life time of the output capacitors. Output Inductor Selection The output inductance must be selected such that under low line and the maximum output voltage condition, the inductor current slope times the output capacitor ESR is ramping up faster than the capacitor voltage is 4-10 Rev. 1.2 12/8/00 US3004/US3005 drooping during a load current step. However if the inductor is too small , the output ripple current and ripple voltage become too large. One solution to bring the ripple current down is to increase the switching frequency , however that will be at the cost of reduced efficiency and higher system cost. The following set of formulas are derived to achieve the optimum performance without many design iterations. The maximum output inductance is calculated using the following equation : L = ESR *C *(Vi i -Vom ax )/(2*∆I ) nm n Where : Vinmin = Minimum input voltage For Vo = 2.8 V , ∆I = 14.2 A L =0.006 * 9000 * ( 4.75 - 2.8) / (2 * 14.2) = 3.7 uH Assuming that the programmed switching frequency is set at 200 KHZ , an inductor is designed using the Micrometals’ powder iron core material. The summary of the design is outlined below : The selected core material is Powder Iron , the selected core is T50-52D from Micro Metal wounded with 8 Turns of # 16 AWG wire, resulting in 3 uH inductance with ≈ 3 mΩ of DC resistance. Assuming L = 3 uH and the switching frequency ; Fsw = 200 KHZ , the inductor ripple current and the output ripple voltage is calculated using the following set of equations : T = 1/Fsw T ≡ Switching Period D ≈ ( Vo + Vsync ) / ( Vin - Vsw + Vsync ) D ≡ Duty Cycle Ton = D * T Vsw ≡ High side Mosfet ON Voltage = Io * Rds Rds ≡ Mosfet On Resistance Toff = T - Ton Vsync ≡ Synchronous MOSFET ON Voltage=Io * Rds ∆Ir = ( Vo + Vsync ) * Toff /L ∆Ir ≡ Inductor Ripple Current ∆Vo = ∆Ir * ESR ∆Vo ≡Output Ripple Voltage In our example for Vo = 2.8V and 14.2 A load , Assuming IRL3103 MOSFET for both switches with maximum on resistance of 19 mΩ, we have : T = 1 / 200000 = 5 uSec Vsw =Vsync= 14.2*0.019=0.27 V D ≈ ( 2.8 + 0.27 ) / ( 5 - 0.27 + 0.27 ) = 0.61 Ton = 0.61 * 5 = 3.1 uSec Toff = 5 - 3.1 = 1.9 uSec ∆Ir = ( 2.8 + 0.27 ) * 1.9 / 3 = 1.94 A ∆Vo = 1.94 * .006 = .011 V = 11 mV Power Component Selection Assuming IRL3103 MOSFETs as power components, we will calculate the maximum power dissipation as follows: For high side switch the maximum power dissipation happens at maximum Vo and maximum duty cycle. Dmax ≈ ( 2.8 + 0.27 ) / ( 4.75 - 0.27 + 0.27 ) = 0.65 Pdh = Dmax * Io^2*Rds(max) Pdh= 0.65*14.2^2*0.029=3.8 W Rds(max)=Maximum Rds-on of the MOSFET at 125°C For synch MOSFET, maximum power dissipation happens at minimum Vo and minimum duty cycle. Dmin ≈ ( 2 + 0.27 ) / ( 5.25 - 0.27 + 0.27 ) = 0.43 Pds = (1-Dmin)*Io^2*Rds(max) Pds=(1 - 0.43) * 14.2^2 * 0.029 = 3.33 W Heatsink Selection Selection of the heat sink is based on the maximum allowable junction temperature of the MOSFETS. Since we previously selected the maximum Rds-on at 125°C, then we must keep the junction below this temperature. Selecting TO220 package gives θjc=1.8°C/W ( From the venders’ datasheet ) and assuming that the selected heatsink is Black Anodized , the Heat sink to Case thermal resistance is ; θcs=0.05°C/W , the maximum heat sink temperature is then calculated as : Ts = Tj - Pd * (θjc + θcs) Ts = 125 - 3.82 * (1.8 + 0.05) = 118 °C With the maximum heat sink temperature calculated in the previous step, the Heat Sink to Air thermal resistance (θsa) is calculated as follows : Assuming Ta=35 °C ∆T = Ts - Ta = 118 - 35 = 83 °C Temperature Rise Above Ambient θsa = ∆T/Pd θsa = 83 / 3.82 = 22 °C/W Next , a heat sink with lower θsa than the one calculated in the previous step must be selected. One way to do this is to simply look at the graphs of the “Heat Sink Temp Rise Above the Ambient” vs. the “Power Dissipation” given in the heatsink manufacturers’ catalog and select a heat sink that results in lower temperature rise than the one calculated in previous step. The following heat sinks from AAVID and Thermaloy meet this criteria. Co. Part # Thermalloy 6078B AAVID 577002 Rev. 1.2 12/8/00 4-11 US3004,US3005 Following the same procedure for the Schottcky diode results in a heatsink with θsa = 25 °C/W. Although it is possible to select a slightly smaller heatsink, for simplicity the same heatsink as the one for the high side MOSFET is also selected for the synchronous MOSFET. Switcher Current Limit Protection The PWM controller uses the MOSFET Rds-on as the sensing resistor to sense the MOSFET current and compares to a programmed voltage which is set externally via a resistor (Rcs) placed between the drain of the MOSFET and the “CS+” terminal of the IC as shown in the application circuit. For example, if the desired current limit point is set to be 22A and from our previous sel i t m axi um M O SFET Rdsecton, he m on=19m Ω, then the current sense resistor, Rcs is calculated as : Vcs=IcL*Rds=22*0.019=0.418V Rcs=Vcs/Ib=(0.418V)/(200uA)=2.1kΩ Where: Ib=200uA is the internal current setting of the device Switcher Timing Capacitor Selection The switching frequency can be programmed using an external timing capacitor. The value of Ct can be approximated using the equation below: Note that since the MOSFETs Rds-on increases with temperature, this number must be divided by ≈ 1.5, inorder to find the Rds-on max at room temperature. The Motorola MTP3055VL has a maximum of 0.18Ω Rds-on at room temperature, which meets our requirement. To select the heatsink for the LDO Mosfet the first step is to calculate the maximum power dissipation of the device and then follow the same procedure as for the switcher. Pd = ( Vin - Vo ) * IL Where : Pd = Power Dissipation of the Linear Regulator IL = Linear Regulator Load Current For the 1.5V and 2A load: Pd = (3.3 - 1.5)*2=3.6 W Assuming Tj-max=125°C Ts = Tj - Pd * (θjc + θcs) Ts = 125 - 3.6 * (1.8 + 0.05) = 118 °C With the maximum heat sink temperature calculated in the previous step, the Heat Sink to Air thermal resistance (θsa) is calculated as follows : Assuming Ta=35 °C ∆T = Ts - Ta = 118 - 35 = 83 °C Temperature Rise Above Ambient θsa = ∆T/Pd θsa = 83 / 3.6 = 23 °C/W The same heat sink as the one selected for the switcher MOSFETs is also suitable for the 1.5V regulator. It is also possible to use TO263 package or even the MTD3055VL in D pak if the load current is less than 1.5A. For the 2.5V regulator since the dropout voltage is only 0.8V and the load current is less than 0.5A, for most applications the same MOSFET without heat sink or for low cost applications, one can use PN2222A in TO92 or SOT23 package. LDO Regulator Component Selection 3.5 × 10 −5 CT Where : CT=Ti min g Capacitor FSW = Switching Frequency FSW ≈ If, FSW=200 kHz : 3.5 × 10 −5 CT ≈ = 175 pF 200 × 10 3 LDO Power MOSFET Selection The first step in selectiong the power MOSFET for the linear regulators is to select its maximum Rds-on based on the input to output Dropout voltage and the maximum load current. Rds(max)=(Vin - Vo)/IL For Vo=1.5V, and Vin=3.3V , IL=2A Rds-max=(3.3 - 1.5)/2= 0.9Ω Since the internal voltage reference for the linear regulators is set at 1.5V for all devices, there is no need to divide the output voltage for the 1.5V, GTL+ regulator. For the 2.5V, Clock supply the resistor dividers are selected per following: Vo=(1+Rt/Rb)*Vref Where: Rt=Top resistor divider Rb=Bottom resistor divider Vref=1.5V typical Assuming Rt=100Ω, for Vo=2.5V Rb=Rt/[(Vo/Vref) - 1] Rb=100/[(2.5/1.5) - 1]=150Ω 4-12 Rev. 1.2 12/8/00 US3004/US3005 For 1.5V output, Rt can be shorted and Rb left open. However it is recommended to leave the resistor dividers as shown in the typical application circuit so that the output voltage can be adjusted higher to account for the trace resistance in the final board layout. It is also recommended that an external filter to be added on the linear regulators to reduce the amount of the high frequency ripple at the output of the regulators. This can simply be done by the resistor capacitor combination as shown in the application circuit. For US3005 that include the resistor dividers internally, Vfb1 can be directly connected to the output voltage without any external resistors for a preset voltage of 2.5V . The disadvantage is that the output voltage is not adjustable anymore. The application circuit given for Pentium II can use either US3004 or US3005 family of parts for maximum flexibility. Disabling the LDO Regulators The LDO controllers can easily be disabled by connecting the feedback pins, Vfb1 and Vfb2 to a voltage higher than 2.5V such as 5V for all devices. Switcher Output Voltage Adjust As it was discussed earlier,the trace resistance from the output of the switching regulator to the Slot 1 can be used to the circuit advantage and possibly reduce the number of output capacitors, by level shifting the DC regulation point when transitioninig from light load to full load and vice versa. To account for the DC drop, the output of the regulator is typically set about half the DC drop that results from light load to full load. For example, if the total resistance from the output capacitors to the Slot 1 and back to the GND pin of the part is 5mΩ and if the total ∆I, the change from light load to full load is 14A, then the output voltage measured at the top of the resistor divider which is also connected to the output capacitors in this case, must be set at half of the 70 mV or 35mV higher than the DAC voltage setting. To do this, the top resistor of the resistor divider(R12 in the application circuit) is set at 100Ω, and the R13 is calculated. For example, if DAC voltage setting is for 2.8V and the desired output under light load is 2.835V, then R13 is calculated using the following formula : R13= 100*{Vdac /(Vo - 1.004*Vdac)} [Ω] R13= 100*{2.8 /(2.835 - 1.004*2.800)} = 11.76 kΩ Select 11.8 kΩ , 1% Note: The value of the top resistor must not exceed 100Ω . The bottom resistor can then be adjusted to raise the output voltage. It is highly recommended to place an inductor between the system 5V supply and the input capacitors of the switching regulator to isolate the 5V supply from the switching noise that occurs during the turn on and off of the switching components. Typically an inductor in the range of 1 to 3 uH will be sufficient in this type of application. Switcher External Shutdown The best way to shutdown the switcher is to pull down on the soft start pin using an external small signal transistor such as 2N3904 or 2N7002 small signal MOSFET. This allows slow ramp up of the output, the same as the power up. Soft Start Capacitor Selection The soft start capacitor must be selected such that during the start up when the output capacitors are charging up, the peak inductor current does not reach the current limit treshold. A minimum of 1uF capacitor insures this for most applications. An internal 10uA current source charges the soft start capacitor which slowly ramps up the inverting input of the PWM comparator Vfb3. This insures the output voltage to ramp at the same rate as the soft start cap thereby limiting the input current. For example, with 1uF and the 10uA internal current source the ramp up rate is (∆V/ ∆t)=I/C = 1V/100mS. Assuming that the output capacitance is 9000uF, the maximum start up current will be: I=9000uF*(1V/100mS)=0.09A Input Filter Rev. 1.2 12/8/00 4-13 US3004,US3005 Layout Considerations Switching regulators require careful attention to the layout of the components, specifically power components since they switch large currents. These switching components can create large amount of voltage spikes and high frequency harmonics if some of the critical components are far away from each other and are connected with inductive traces. The following is a guideline of how to place the critical components and the connections between them in order to minimize the above issues. Start the layout by first placing the power components: 1) Place the input capacitors C3 and the high side mosfet ,Q1 as close to each other as possible 2) Place the synchronous mosfet,Q2 and the Q1 as close to each other as possible with the intention that the source of Q1 and drain of the Q2 has the shortest length. 3) Place the snubber R4 & C7 between Q1 & Q2. 4) Place the output inductor ,L2 and the output capacitors ,C10 between the mosfet and the load with output capacitors distributed along the slot 1 and close to it. 5) Place the bypass capacitors, C4 and C6 right next to 12V and 5V pins. C4 next to the 12V, pin 12 and C6 next to the 5V, pin 5. 6) Place the controller IC such that the pwm output drives, pins 9 and 11 are relatively short distance from gates of Q1 and Q2. 7) Place resistor dividers, R7 & R8 close to pin 3, R12 & R13 (note 1) close to pin 14 and R14 and R15 (note 1) close to pin 20. Note 1: Although, the PWM controller does not require R12-15 resistors, and the feedback pins 3 and 14 can be directly connected to their respective outputs, they can be used to set the outputs slightly higher to account for any output drop at the load due to the trace resistance. 8) Place R11, C15, Q3 and C11 close to each other and do the same with R9, C14, Q4 and C12. Note: It is better to place the linear regulator components close to the IC and then run a trace from the output of each regulator to its respective load such as 2.5V to the clock and 1.5V for GTL + termination. However, if this is not possible then the trace from the linear drive output pins, pins 2 and 20 must be routed away from any high frequency data signals. It is critical, to place high frequency ceramic capacitors close to the clock chip and termination resistors to provide local bypassing. 9) Place timing capacitor C1 close to pin1 and soft start capacitor C2 close to pin 13 Component connections: Note : It is extremely important that no data bus should be passing through the switching regulator section specifically close to the fast transition nodes such as PWM drives or the inductor voltage. Using the 4 layer board, dedicate on layer to GND, another layer as the power layer for the 5V, 3.3V, Vcore, 1.5V and if it is possible for the 2.5V. Connect all grounds to the ground plane using direct vias to the ground plane. Use large low inductance/low impedance plane to connect the following connections either using component side or the solder side. a) C3 to Q1 Drain b) Q1 Source to Q2 Drain c) Q2 drain to L2 d) L2 to the output capacitors, C10 e) C10 to the slot 1 f) Input filter L1 to the C3 g) C9 to Q4 drain h) C12 to the Q4 source Connect the rest of the components using the shortest connection possible 4-14 Rev. 1.2 12/8/00