VT73LVP10S1

Preliminary VT73LVP10 TTL to Differential LVPECL Translator with Enable Applications •= PECL clock source General Description The Vaishali VT73LVP10 is a general purpose TTL (CMOS) to differential LVPECL translator, with active-LOW enable. The device operates from a single 3.3V supply. When /EN is LOW or open circuit, the device accepts an LVTTL or LVCMOS input and provides differential LVPECL outputs referenced to the positive supply rail. When /EN is HIGH, the Q output is set to the LOW state and QN output is set to the HIGH state. Features •= •= •= •= 700ps typical propagation delay Differential LVPECL outputs Flow-through pinout -40 C to +85 C operating temperature range o o •= •= •= 5V - tolerant inputs ESD rating >2000V (Human Body Model) or >200V (Machine Model) Available as die, 8-pin SOIC or 8 pin MSOP package Figure 1. Functional Block Diagram & Pin Assignment 8 pin SOIC/ MSOP NC 1 8 VDD Q2 LVPECL QN 3 TTL/ CMOS 7D 6 NC /EN 4 100kΩ 5 GND 2002-01-15 Vaishali Semiconductor Page 1 www.vaishali.com 747 Camden Avenue, Suite C Campbell CA 95008 MDST-0014-07 Ph. 408.377.6060 Fax 408.377.6063 VT73LVP10 Preliminary Table 1. Pin Description Name /EN Q QN VDD D GND PECL data output PECL complementary data output Connect to 3.3V CMOS/TTL data input Connect to ground Description CMOS/TTL Active LOW enable input, with pull-down resistor Type I O O P I P Pin # 4* 2 3 8 7 5 Legend: I = Input O = Output P = Power supply connection * = Internal 100kΩ pull-down resistor Table 2. Absolute Maximum Ratings Symbol VDD VIN IOUT TSTG Parameter Supply voltage Input voltage Output current in LOW state Storage temperature Conditions Referenced to GND Referenced to GND Min -0.5 Typ Max 6 6 50 Units V V mA o -65 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3. Operating Conditions Symbol VDD TA VIH VIL tRin tFin Parameter Power Supply Voltage Ambient Temperature Input HIGH Voltage Input LOW Voltage Input slew rate Input slew rate Conditions Min 3.0 -40 Typ Max 3.6 85 Units V o C D, /EN inputs D, /EN inputs 10% to 90% (L → H) 90% to 10% (H → L) 2.0 0.8 1 1 V V V/ns V/ns 2002-01-15 Vaishali Semiconductor Page 2 www.vaishali.com 747 Camden Avenue, Suite C Campbell CA 95008 MDST-0014-06 Ph. 408.377.6060 Fax 408.377.6063 VT73LVP10 Preliminary Table 4. DC Characteristics TA = -40 C to +85 C, VDD = 3.0V to 3.6V unless otherwise stated below. o o Symbol IIH IIL Parameter Input HIGH Current Conditions VIN = 2.7V D input /EN input Min Typ Max 1 50 1 20 -1.2 Units µA µA Input LOW Current VIN = 0.5V D input /EN input VIK VOH Input Clamp Diode Voltage Output HIGH Voltage (1, 2) IIN = -18mA -40 C 25 C 85 C o o o V mV mV mV mV mV mV mA VDD = 3.3V 2275 2200 2125 2375 2300 2225 1450 1500 1550 33 2475 2400 2325 1550 1600 1650 VOL Output LOW Voltage (1, 2) -40 C 25 C 85 C o o o VDD = 3.3V 1350 1400 1450 IDD Power Supply Current (2) Notes:1.The VT73LVP10 is designed to meet these specifications after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board. 2. Q and QN outputs are loaded with 50 ohms to VDD-2 volts. Table 5. AC Characteristics TA = -40 C to +85 C, VDD = 3.0V to 3.6V o o Symbol tPLH tPHL tPLH tPHL tr/tf fMAX fMAX Parameter Propagation Delay Propagation Delay Propagation Delay Propagation Delay Output Rise/Fall time Maximum Input Frequency Maximum Input Frequency (2) (1) (1) Conditions Min Typ 0.7 0.7 Max 1.2 1.2 2.5 2.5 0.7 Units ns ns ns ns ns MHz MHz /EN to Q, QN /EN to Q, QN 20%-80% LVTTL or LVCMOS input 750mV peak-to-peak sine wave (AC coupled) 0.25 170 400 1.5 1.5 0.35 Notes: 1. Q and QN outputs are loaded with 50 ohms to VDD-2 volts. 2. Measured using a 750mV peak-to-peak, 50% duty cycle clock source. Ordering Information Part Number VT73LVP10S1 VT73LVP10S1X VT73LVP10M VT73LVP10MX VT73LVP10/D VT73LVP10/DW 2002-01-15 Vaishali Semiconductor Marking VT73LVP10S1 VT73LVP10S1 VT73LVP10M VT73LVP10M Shipping/Packaging Tubes Tape & Reel Tubes Tape & Reel Dice in waffle-pak Dice in wafer form No. of Pins 8 8 8 8 Package SOIC SOIC MSOP MSOP Temperature -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C MDST-0014-06 Page 3 www.vaishali.com 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063