BCM® in a VIA Package
Bus Converter
BCM4414xD1E13A2yzz
®
S
US
C
C
NRTL
US
Isolated Fixed-Ratio DC-DC Converter
Features & Benefits
Product Ratings
• Up to 125A continuous low voltage side current
VHI = 384V (260 – 410V)
ILO = up to 125A
• Fixed transformation ratio (K) of 1/32
VLO = 12V (8.1 – 12.8V)
(no load)
K = 1/32
• Up to 711W/in3 power density
• 97.1% peak efficiency
Product Description
• Built-in EMI filtering and inrush limiting circuit
The BCM4414xD1E13A2yzz in a VIA package is a high efficiency
Bus Converter, operating from a 260 to 410VDC high voltage bus to
deliver an isolated 8.1 to 12.8VDC unregulated, low voltage.
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
This unique ultra-low profile module incorporates DC-DC
conversion, integrated filtering and PMBus commands and controls
in a chassis or PCB mount form factor.
• 4414 package
• High MTBF
The BCM offers low noise, fast transient response and industry
leading efficiency and power density. A low voltage side referenced
PMBus compatible telemetry and control interface provides access
to the BCM’s configuration, fault monitoring, and other telemetry
functions.
• Thermally enhanced VIA package
• PMBus® [1] management interface
• Suitable for Hot-Swap applications
Leveraging the thermal and density benefits of Vicor’s VIA
packaging technology, the BCM module offers flexible thermal
management options with very low top and bottom side
thermal impedances.
Typical Applications
• 380VDC Power Distribution
• Information and Communication
Technology (ICT) Equipment
When combined with downstream Vicor DC-DC conversion
components and regulators, the BCM allows the Power Design
Engineer to employ a simple, low-profile design, which will
differentiate the end system without compromising on cost or
performance metrics.
• High End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High Density Energy Systems
• Transportation
Size:
4.35 x 1.40 x 0.37in
110.55 x 35.54 x 9.40mm
• Green Buildings and Microgrids
Part Ordering Information
Product
Function
Package
Length
Package
Width
Package
Type
Max
High
Side
Voltage
BCM
44
14
x
D1
BCM =
Bus Converter
Module
Length in
Inches x 10
Width in
Inches x 10
B = Board VIA
V = Chassis VIA
[1]
[2]
High Side
Max
Voltage
Low
Range
Side
Ratio
Voltage
E
13
Internal Reference
The PMBus name, SMIF, Inc. and logo are trademarks of SMIF, Inc.
High temperature current derating may apply; See Figure 1, specified thermal operating area.
BCM® in a VIA™ Package
Page 1 of 43
Rev 1.7
08/2020
Max
Low
Side
Current
Product Grade
(Case Temperature)
Option Field
A2
y
zz
C = -20 to 100°C [2]
T = -40 to 100°C [2]
02 = Chassis/PMBus
06 = Short Pin/PMBus
10 = Long Pin/PMBus
BCM4414xD1E13A2yzz
Typical Applications
3 Phase AIM
BCM in a VIA package
+
+HI
+LO
EXT_BIAS
SCL
L1
L2
L3
L
O
A
D
SDA
SGND
-
ADDR
-HI
-LO
ISOLATION BOUNDARY
3 phase AC to point of load (3 phase AIM + BCM4414xD1E13A2yzz)
BCM in a VIA package
+HI
+LO
EXT_BIAS
5V
SCL
SDA
SGND
ADDR
-HI
-LO
R1
SCL
CLOCK
ISOLATION BOUNDARY
+HI
+LO
EXT_BIAS
5V
SCL
SDA
SGND
ADDR
-HI
-LO
R2
ISOLATION BOUNDARY
Paralleling BCM in a VIA package – connection to Host PMBus®
BCM® in a VIA™ Package
Page 2 of 43
Rev 1.7
08/2020
GROUND
BCM in a VIA package
SGND
DATA
DC
L
O
A
D
+
–
SDA
Host PMBus®
BCM4414xD1E13A2yzz
Typical Applications (Cont.)
Host PMBus®
PMBus
V
+
EXT
–
SGND
SGND
BCM in a VIA Package
SGND
EXT_BIAS
SCL
SDA
SGND
}
3
SGND
ADDR
FUSE
V
HI
C
+HI
+LO
–HI
–LO
Non-Isolated
Point of Load
Regulators
HI
HV
SOURCE_RTN
LOAD
LV
ISOLATION BOUNDARY
BCM4414xD1E13A2yzz at point of load – connection to Host PMBus®
Host PMBus®
PMBus
V
+
EXT
SGND
–
SGND
SGND
BCM in a VIA Package
EXT_BIAS
SCL
SDA
SGND
}
3
SGND
ADDR
FUSE
V
HI
SOURCE_RTN
C
+HI
+LO
–HI
–LO
LOAD
HI
HV
LV
ISOLATION BOUNDARY
BCM4414xD1E13A2yzz direct to load – connection to Host PMBus
BCM® in a VIA™ Package
Page 3 of 43
Rev 1.7
08/2020
BCM4414xD1E13A2yzz
Pin Configuration
1
+HI
10
TOP VIEW
3
12
–LO
–LO
+LO
5
6
7
8
9
PMBus™
+LO
–LO
–LO
2
11
13
4
2
11
13
4
–HI
EXT BIAS
SCL
SDA
SGND
ADDR
BCM in a 4414 VIA Package - Chassis (Lug) Mount
–HI
TOP VIEW
–LO
–LO
+LO
9
8
7
6
5
PMBus™
+HI
1
–LO
–LO
10
12
ADDR
SGND
SDA
SCL
EXT BIAS
+LO
3
BCM in a 4414 VIA Package - Board (PCB) Mount
Note: The dot on the VIA housing indicates the location of the signal pin 9.
Pin Descriptions
Pin Number
Signal Name
Type
1
+HI
HIGH SIDE POWER
2
–HI
3, 4
+LO
5
EXT BIAS
INPUT
5V supply input
6
SCL
INPUT
I2C Clock, PMBus® Compatible
7
SDA
INPUT/OUTPUT
I2C Data, PMBus Compatible
8
SGND
LOW SIDE
SIGNAL RETURN
Signal Ground
9
ADDR
INPUT
10, 11, 12, 13
–LO
LOW SIDE
POWER RETURN
HIGH SIDE POWER
RETURN
LOW SIDE
POWER
Function
High voltage side positive power terminal
High voltage side negative power terminal
Low voltage side positive power terminal
Address assignment - Resistor based
Low voltage side negative power terminal
Notes: All signal pins (5, 6, 7, 8, 9) are referenced to the low voltage side and isolated from the high voltage side.
Keep SGND signal separated from the low voltage side power return terminal (–LO) in electrical design.
BCM® in a VIA™ Package
Page 4 of 43
Rev 1.7
08/2020
BCM4414xD1E13A2yzz
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Comments
+HI to –HI
HI_DC or LO_DC Slew Rate
Min
Max
Unit
-1
480
V
N/A
V/µs
-1
15
V
-0.3
10
V
0.15
A
Internal hot-swap circuitry
+LO to –LO
EXT BIAS to SGND
SCL to SGND
-0.3
5.5
V
SDA to SGND
-0.3
5.5
V
ADDR to SGND
-0.3
3.6
V
Isolation Voltage /
Dielectric Withstand
Basic insulation (high voltage side to case)
2121
VDC
Basic insulation (high voltage side to low voltage side) [1]
2121
VDC
N/A
VDC
(low voltage side to case)
[1]
The absolute maximum rating listed above for the dielectric withstand (high voltage side to the low voltage side) refers to the VIA package. The internal
safety approved isolating component (ChiP) provides reinforced insulation (4242V) from the high voltage side to the low voltage side. However, the VIA
package itself can only be tested at a basic insulation value (2121V).
BCM® in a VIA™ Package
Page 5 of 43
Rev 1.7
08/2020
BCM4414xD1E13A2yzz
Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
-40°C ≤ TCASE ≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain Specification – Forward Direction Operation (High Voltage Side to Low Voltage Side)
HI Side Voltage Range,
(Continuous)
VHI_DC
260
410
V
HI Side Voltage Range,
(Transient)
VHI_TRANS
260
410
V
HI Side Voltage
Initialization Threshold
VµC_ACTIVE
130
V
HI Side Quiescent Current
IHI_Q
HI side voltage where internal controller is initialized,
(powertrain inactive)
Disabled, VHI_DC = 384V
2
TCASE ≤ 100ºC
4
VHI_DC = 384V, TCASE = 25ºC
No Load Power Dissipation
HI Side Inrush Current Peak
DC HI Side Current
Transformation Ratio
LO Side Current (Continuous)
LO Side Current (Pulsed)
Efficiency (Ambient)
PHI_NL
IHI_INR_PK
IHI_IN_DC
K
ILO_OUT_DC
ILO_OUT_PULSE
ηAMB
11
5.9
VHI_DC = 384V
15
24
VHI_DC = 260V to 410V, TCASE = 25 ºC
16
VHI_DC = 260V to 410V
25
VHI_DC = 410V, CLO_EXT = 1000μF, RLOAD_LO = 25% of full
load current
10
15
At ILO_OUT_DC = 125A, TCASE ≤ 90ºC
4.1
1/32
TCASE ≤ 90°C
125
A
2ms pulse, 25% duty cycle, ILO_OUT_AVG ≤ 50% rated
ILO_OUT_DC
167
A
VHI_DC = 384V, ILO_OUT_DC = 125A
96.2
97
VHI_DC = 260V to 410V, ILO_OUT_DC = 125A
95.2
VHI_DC = 384V, ILO_OUT_DC = 62.5A
96.5
97.4
95.8
97
%
ηHOT
VHI_DC = 384V, ILO_OUT_DC = 125A, TCASE = 85°C
Efficiency (Over Load Range)
η20%
25A < ILO_OUT_DC < 125A
95
RLO_COLD
VHI_DC = 384V, ILO_OUT_DC = 125A, TCASE = -40°C
1.6
1.9
2.3
RLO_AMB
VHI_DC = 384V, ILO_OUT_DC = 125A
2.0
2.4
2.8
RLO_HOT
VHI_DC = 384V, ILO_OUT_DC = 125A, TCASE = 85°C
2.5
2.8
3.2
LO side voltage ripple frequency = 2x FSW
0.95
1.00
1.05
Switching Frequency
LO Side Voltage Ripple
FSW
VLO_OUT_PP
CLO_EXT = 0μF, ILO_OUT_DC = 125A, VHI_DC = 384V,
20MHz BW
TCASE ≤ 100ºC
BCM® in a VIA™ Package
Page 6 of 43
A
V/V
Efficiency (Hot)
LO Side Output Resistance
W
A
TCASE ≤ 100ºC
High Voltage to Low Voltage, K = VLO_DC / VHI_DC,
at no load
mA
%
%
195
MHz
mV
250
Rev 1.7
08/2020
mΩ
BCM4414xD1E13A2yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
-40°C ≤ TCASE ≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain Specification – Forward Direction Operation (High Voltage Side to Low Voltage Side) Cont.
Effective HI Side Capacitance
(Internal)
CHI_INT
Effective value at 384VHI_DC
0.4
µF
Effective LO Side Capacitance
(Internal)
CLO_INT
Effective value at 12VLO_DC
238
µF
Rated LO Side Capacitance (External)
CLO_OUT_EXT
Rated LO Side Capacitance (External),
CLO_OUT_AEXT
Parallel Array Operation
Excessive capacitance may drive module into
short circuit protection
1000
µF
CLO_OUT_AEXT Max = N * 0.5 * CLO_OUT_EXT MAX, where
N = the number of units in parallel
Powertrain Hardware Protection Specification – Forward Direction Operation (High Voltage Side to Low Voltage Side)
• These built-in powertrain protections are fixed in hardware and cannot be configured through PMBus®.
• When duplicated in supervisory limits, hardware protections serve a secondary role and become active when supervisory limits are
disabled through PMBus.
Auto Restart Time
tAUTO_RESTART
Startup into a persistent fault condition. Non-latching
fault detection given VHI_DC > VHI_UVLO+
290
360
ms
HI Side Overvoltage
Lockout Threshold
VHI_OVLO+
430
440
450
V
HI Side Overvoltage
Recovery Threshold
VHI_OVLO-
410
430
440
V
HI Side Overvoltage
Lockout Hysteresis
VHI_OVLO_HYST
10
V
tHI_OVLO
100
µs
1
ms
HI Side Overvoltage Lockout
Response Time
HI Side Soft-Start Time
tHI_SOFT-START
LO Side Overcurrent
Trip Threshold
ILO_OUT_OCP
LO Side Overcurrent
Response Time Constant
tLO_OUT_OCP
LO Side Short Circuit
Protection Trip Threshold
ILO_OUT_SCP
LO Side Short Circuit
Protection Response Time
tLO_OUT_SCP
Overtemperature
Shutdown Threshold
BCM® in a VIA™ Package
Page 7 of 43
tOTP+
From powertrain active. Fast current limit protection
disabled during soft-start
135
Effective internal RC filter
170
3
187
125
Rev 1.7
08/2020
A
ms
A
1
Internal
210
µs
°C
BCM4414xD1E13A2yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
-40°C ≤ TCASE ≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Powertrain Supervisory Limits Specification – Forward Direction Operation (High Voltage Side to Low Voltage Side)
• These supervisory limits are set in the internal controller and can be reconfigured or disabled through PMBus®.
• When disabled, the powertrain protections presented in the previous table will intervene during fault events.
HI Side Overvoltage Lockout
Threshold
VHI_OVLO+
420
434.5
450
V
HI Side Overvoltage Recovery
Threshold
VHI_OVLO-
405
424
440
V
HI Side Overvoltage Lockout
Hysteresis
VHI_OVLO_HYST
10.5
V
HI Side Overvoltage Lockout
Response Time
tHI_OVLO
100
µs
HI Side Undervoltage Lockout
Threshold
VHI_UVLO-
200
226
250
V
HI Side Undervoltage Recovery
Threshold
VHI_UVLO+
225
244
259
V
HI Side Undervoltage Lockout
Hysteresis
VHI_UVLO_HYST
15
V
HI Side Undervoltage Lockout
Response Time
tHI_UVLO
100
µs
20
ms
HI Side Undervoltage Startup Delay
tHI_UVLO+_DELAY
LO Side Overcurrent Trip Threshold
ILO_OUT_OCP
LO Side Overcurrent
Response Time Constant
tLO_OUT_OCP
From VHI_DC = VHI_UVLO+ to powertrain active, (i.e., one
time startup delay from application of VHI_DC to VLO_DC)
159
Effective internal RC filter
tOTP+
Internal
125
Overtemperature Recovery
Threshold
tOTP–
Internal
105
Undertemperature Shutdown
Threshold (Internal)
tUTP
BCM® in a VIA™ Package
Page 8 of 43
tUTP_RESTART
177
2
Overtemperature Shutdown
Threshold
Undertemperature Restart Time
168
ms
°C
110
115
C-Grade
-25
T-Grade
-45
Startup into a persistent fault condition. Non-latching
fault detection given VHI_DC > VHI_UVLO+
Rev 1.7
08/2020
A
3
°C
°C
s
BCM4414xD1E13A2yzz
LO Side Current (A)
150
125
100
75
50
25
0
-60
-40
-20
0
20
40
60
80
100
120
140
Case Temperature (°C)
260V – 410V
Figure 1 — Specified thermal operating area
1. The BCM in a VIA package is cooled through the bottom case (bottom housing).
2. The thermal rating is based on typical measured device efficiency.
3. The case temperature in the graph is the measured temperature of the bottom housing, such that the internal operating temperature
does not exceed 125°C.
2500
200
175
2000
LO Side Current (A)
LO Side Power (W)
2250
1750
1500
1250
1000
750
500
250
0
150
125
100
75
50
25
260
275
290
305
320
335
350
365
380
395
0
410
HI Side Voltage (V)
PLO_OUT_DC
260
275
290
305
PLO_OUT_PULSE
0
25
50
75
LO Side Capacitance
(% Rated CLO_EXT_MAX)
LO Side Current (% ILO_DC)
Figure 3 — Specified HI side startup into load current and external capacitance
BCM® in a VIA™ Package
Page 9 of 43
335
ILO_OUT_DC
Figure 2 — Specified electrical operating area using rated RLO_HOT
110
100
90
80
70
60
50
40
30
20
10
0
320
350
365
380
HI Side Voltage (V)
Rev 1.7
08/2020
100
ILO_OUT_PULSE
395
410
BCM4414xD1E13A2yzz
PMBus® Reported Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
-40°C ≤ TCASE ≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Monitored Telemetry
PMBus® READ COMMAND
ACCURACY
(RATED RANGE)
FUNCTIONAL
REPORTING RANGE
UPDATE
RATE
REPORTED UNITS
HI Side Voltage
(88h) READ_VIN
± 5% (LL - HL)
130V to 450V
100µs
VACTUAL = VREPORTED x 10-1
HI Side Current
(89h) READ_IIN
± 20% (10 - 20% of FL)
± 5% (20 - 133% of FL)
-0.85A to 5.9A
100µs
IACTUAL = IREPORTED x 10-3
LO Side Voltage [1]
(8Bh) READ_VOUT
± 5%(LL - HL)
4.25V to 14V
100µs
VACTUAL = VREPORTED x 10-1
LO Side Current
(8Ch) READ_IOUT
± 20% (10 - 20% of FL)
± 5% (20 - 133% of FL)
-27A to 190A
100µs
IACTUAL = IREPORTED x 10-2
LO Side Resistance
(D4h) READ_ROUT
± 5% (50 - 100% of FL) at NL
± 10% (50 - 100% of FL) (LL - HL)
1.0mΩ to 3.0mΩ
100ms
RACTUAL = RREPORTED x 10-5
(8Dh) READ_TEMPERATURE_1
± 7°C (Full Range)
- 55ºC to 130ºC
100ms
TACTUAL = TREPORTED
ATTRIBUTE
Temperature [2]
[1]
[2]
Default READ LO Side Voltage returned when unit is disabled = -300V.
Default READ Temperature returned when unit is disabled = -273°C.
Variable Parameters
• Factory setting of all Thresholds and Warning limits listed below are 100% of specified protection values.
• Variables can be written only when module is disabled with VHI < VHI_UVLO- and external bias (VDDB) applied.
• Module must remain in a disabled mode for 3ms after any changes to the variables below to allow sufficient time to commit changes to EEPROM.
ATTRIBUTE
PMBus COMMAND
CONDITIONS / NOTES
VHI_OVLO- is automatically 3%
lower than this setpoint
ACCURACY
(RATED RANGE)
FUNCTIONAL
REPORTING
RANGE
DEFAULT
VALUE
± 5% (LL - HL)
130V to 435V
100%
± 5% (LL - HL)
130V to 435V
100%
± 5% (LL - HL)
130V to 260V
100%
HI Side Overvoltage
Protection Limit
(55h) VIN_OV_FAULT_LIMIT
HI Side Overvoltage
Warning Limit
(57h) VIN_OV_WARN_LIMIT
HI Side Undervoltage
Protection Limit
(D7h) DISABLE_FAULTS
HI Side Overcurrent
Protection Limit
(5Bh) IIN_OC_FAULT_LIMIT
± 20% (10 - 20% of FL)
± 5% (20 - 133% of FL)
0 to 5.25A
100%
HI Side Overcurrent
Warning Limit
(5Dh) IIN_OC_WARN_LIMIT
± 20% (10 - 20% of FL)
± 5% (20 - 133% of FL)
0 to 5.25A
100%
Can only be disabled to a preset
default value
Overtemperature
Protection Limit
(4Fh) OT_FAULT_LIMIT
Internal temperature
± 7°C (Full Range)
0 to 125°C
100%
Overtemperature
Warning Limit
(51h) OT_WARN_LIMIT
Internal temperature
± 7°C (Full Range)
0 to 125°C
100%
± 50µs
0 to 100ms
0 ms
Turn On Delay
(60h) TON_DELAY
Additional time delay to the
undervoltage startup delay
BCM® in a VIA™ Package
Rev 1.7
Page 10 of 43 08/2020
BCM4414xD1E13A2yzz
Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
-40°C ≤ TCASE ≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted. Please Note: For chassis mount model, Vicor part
number 42550 will be needed for applications requiring the use of the signal pins. Signal cable 42550 is rated up to five insertions and extractions. To avoid
unnecessary stress on the connector, the cable should be appropriately strain relieved.
EXT. BIAS (VDDB) Pin
• VDDB powers the internal controller.
• VDDB needs to be applied to enable and disable the BCM through PMBus® control (using OPERATION COMMAND), and to adjust warning and
protection thresholds.
• VDDB voltage not required for telemetry; however, if VDDB is not applied, telemetry information will be lost when VIN is removed.
SIGNAL TYPE
STATE
Regular
Operation
INPUT
Startup
ATTRIBUTE
SYMBOL
VDDB Voltage
VVDDB
VDDB Current Consumption
IVDDB
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
4.5
5
9
V
50
mA
Inrush Current Peak
IVDDB_INR
VVDDB slew rate = 1V/µs
3.5
A
Turn On Time
tVDDB_ON
From VVDDB_MIN to PMBus active
1.5
ms
SGND Pin
• All PMBus interface signals (SCL, SDA, ADDR) are referenced to SGND pin.
• SGND pin also serves as return pin (ground pin) for VDDB.
• Keep SGND signal separated from the low voltage side power return terminal (–LO) in electrical design.
Address (ADDR) Pin
• This pin programs the address using a resistor between ADDR pin and signal ground.
• The address is sampled during startup and is stored until power is reset. This pin programs only a Fixed and Persistent address.
• This pin has an internal 10kΩ pullup resistor to 3.3V.
• 16 addresses are available. The range of each address is 206.25mV (total range for all 16 addresses is 0V to 3.3V).
SIGNAL TYPE
MULTI‐LEVEL
INPUT
STATE
Regular
Operation
Startup
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
ADDR Input Voltage
VSADDR
See address section
ADDR Leakage Current
ISADDR
Leakage current
ADDR Registration Time
tSADDR
From VVDDB_MIN
BCM® in a VIA™ Package
Rev 1.7
Page 11 of 43 08/2020
MIN
TYP
0
1
MAX
UNIT
3.3
V
1
µA
ms
BCM4414xD1E13A2yzz
Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High-power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is not supported.
• PMBus® command compatible.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
Electrical Parameters
VIH
Input Voltage Threshold
2.1
VIL
0.8
VOH
Output Voltage Threshold
3
VOL
Leakage Current
ILEAK_PIN
Signal Sink Current
ILOAD
Unpowered device
10
VOL = 0.4V
CI
Signal Noise Immunity
VNOISE_PP
4
300
Idle state = 0Hz
10
V
µA
mA
10
10MHz to 100MHz
V
V
0.4
Total capacitive load of
one device pin
Signal Capacitive Load
V
pF
mV
Timing Parameters
DIGITAL
INPUT/OUTPUT
Regular
Operation
Operating Frequency
FSMB
Free Time Between
Stop and Start Condition
tBUF
Hold TimeAfter Start or
Repeated Start Condition
tHD:STA
Repeat Start Condition
Setup Time
tSU:STA
First clock is generated
after this hold time
1.3
µs
0.6
µs
0.6
µs
tSU:STO
0.6
µs
Data Hold Time
tHD:DAT
300
ns
Data Setup Time
tSU:DAT
100
ns
Clock Low Timeout
tTIMEOUT
25
Clock Low Period
tLOW
1.3
Clock High Period
tHIGH
0.6
35
ms
µs
50
µs
25
ms
Cumulative Clock Low
Extend Time
tLOW:SEXT
Clock or Data Fall Time
tF
20
300
ns
Clock or Data Rise Time
tR
20
300
ns
tLOW tR
tF
VIH
VIL
tHD,STA
SDA
P
kHz
Stop Condition Setup Time
SCL
VIH
VIL
400
tBUF
tHD,DAT
tHIGH
tSU,DAT
S
BCM® in a VIA™ Package
Rev 1.7
Page 12 of 43 08/2020
tSU,STA
tSU,STO
S
P
BCM® in a VIA™ Package
Rev 1.7
Page 13 of 43 08/2020
OUTPUT
INPUT
+VLO
+VHI
VµC_ACTIVE
STARTUP
tHI _UVLO+_DELAY
VHI_UVLO+
VHI_OVLO+
VNOM
VHI_UVLO-
VHI_OVLO-
OVERVOLTAGE
T
NI
E
IA N
LT
VO
I NO
R
N
E
R
ER UR
OV
TU
OL E T
E
E
R
D
D
D
NT SI
SI
SI
CO LO
HI
HI
ON
LIZ
E
AG
T
A
OPERATION
COMMAND
CONTROL
M
ON
T
OR
H
S
ND
F
A
OF
OVERCURRENT
tAUTO_RESTART
tLO_OUT_SCP
>tHI_UVLO+_DELAY
M M
C O CO
S
N
N
O
RE
T I ATIO
E
A
D
E R ER
SI
HI
O P OP
R
TA
M
ND
CI
D
SI
HI
T
E
TU
RN
SHUTDOWN
T
UI
RC
EN
EV
OF
F
BCM4414xD1E13A2yzz
Timing Diagram (Forward Direction)
BCM4414xD1E13A2yzz
Application Characteristics
30
98.0
27
97.5
Full Load Efficiency (%)
Power Dissipation (W)
Temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (high voltage side to low voltage side). See associated figures for general trend data.
24
21
18
15
12
9
6
3
0
97.0
96.5
96.0
95.5
95.0
94.5
94.0
260
275
290
305
320
335
350
365
380
395
410
-40
-20
HI Side Voltage (V)
TTOP SURFACE CASE:
- 40°C
25°C
VHI_DC:
85°C
Figure 4 — No load power dissipation vs. VHI_DC
Power Dissipation (W)
Efficiency (%)
40
60
80
100
260V
384V
410V
80
97
95
93
91
89
87
85
83
81
72
64
56
48
40
32
24
16
8
0
0.0
0.0
VHI_DC:
260V
384V
LO Side Current (A)
VHI_DC:
72
Power Dissipation (W)
80
97
95
93
91
89
87
85
83
81
56
48
40
32
24
16
8
0.0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
LO Side Current (A)
260V
Figure 8 — Efficiency at TCASE = 25°C
410V
64
0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
VHI_DC:
384V
Figure 7 — Power dissipation at TCASE = -40°C
99
0.0
260V
410V
Figure 6 — Efficiency at TCASE = -40°C
79
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
LO Side Current (A)
Efficiency (%)
20
Figure 5 — Full load efficiency vs. temperature
99
79
0
Case Temperature (ºC)
384V
LO Side Current (A)
410V
VHI_DC:
260V
384V
Figure 9 — Power dissipation at TCASE = 25°C
BCM® in a VIA™ Package
Rev 1.7
Page 14 of 43 08/2020
410V
99
80
97
72
64
Power Dissipation (W)
Efficiency (%)
BCM4414xD1E13A2yzz
95
93
91
89
87
85
83
81
79
0.0
56
48
40
32
24
16
8
0
0.0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
LO Side Current (A)
LO Side Current (A)
260V
VHI_DC:
384V
VHI_DC:
410V
Figure 10 — Efficiency at TCASE = 85°C
410V
80
72
4
LO Side
Voltage Ripple (mV)
LO Side
Output Resistance (mΩ)
384V
Figure 11 — Power dissipation at TCASE = 85°C
5
3
2
1
0
260V
64
56
48
40
32
24
16
8
-40
-20
0
20
40
60
80
0
100
0.0
Case Temperature (°C)
ILO_DC:
LO Side Current (A)
VHI_DC:
125A
Figure 12 — RLO vs. temperature; Nominal VHI_DC
ILO_DC = 125A at TCASE = 85°C
12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
384V
Figure 13 — VLO_OUT_PP vs. ILO_DC ; No external CLO_OUT_EXT. Board
mounted module, scope setting: 20MHz analog BW
BCM® in a VIA™ Package
Rev 1.7
Page 15 of 43 08/2020
BCM4414xD1E13A2yzz
Figure 14 — Full load LO side voltage ripple, 10 µF CHI_IN_EXT;
No external CLO_OUT_EXT. Board mounted module,
scope setting: 20MHz analog BW
Figure 15 — 0A – 125A transient response:
CHI_IN_EXT = 10µF, no external CLO_OUT_EXT
Figure 16 — 125A – 0A transient response:
CHI_IN_EXT = 10µF, no external CLO_OUT_EXT
Figure 17 — Startup from application of VHI_DC = 384V, 25% ILO_DC,
100% CLO_OUT_EXT
Figure 18 — Startup from application of OPERATION COMMAND
with pre-applied VHI_DC = 384V, 25% ILO_DC,
100% CLO_OUT_EXT
BCM® in a VIA™ Package
Rev 1.7
Page 16 of 43 08/2020
BCM4414xD1E13A2yzz
General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
-40°C ≤ TCASE ≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Mechanical
Length
L
Lug (Chassis) Mount
110.30 / [4.34] 110.55 / [4.35] 110.80 / [4.36] mm / [in]
Length
L
PCB (Board) Mount
112.51 / [4.43] 112.76 / [4.44] 113.01 / [4.45] mm / [in]
Width
W
35.29 / [1.39]
35.54 / [1.40] 35.79 / [1.41]
Height
H
9.019 / [0.355]
9.40 / [0.37] 9.781 / [0.385] mm / [in]
Volume
Vol
Weight
W
Without heatsink
36.93 / [2.25]
cm3/ [in3]
140.5 / [4.96]
g / [oz]
Pin Material
C145 copper
Underplate
Low stress ductile Nickel
50
100
Palladium
0.8
6
Soft Gold
0.12
2
200
400
BCM4414xD1E13A2yzz (T-Grade)
-40
125
BCM4414xD1E13A2yzz (C-Grade)
-20
125
BCM4414xD1E13A2yzz (T-Grade),
derating applied, see safe thermal
operating area
-40
100
BCM4414xD1E13A2yzz (C-Grade),
derating applied, see safe thermal
operating area
-20
100
Pin Finish (Gold)
Pin Finish (Tin)
Whisker resistant matte Tin
mm / [in]
µin
µin
Thermal
Operating Internal Temperature
Operating Case Temperature
Thermal Resistance Top Side
Thermal Resistance Coupling Between
Top Case and Bottom Case
Thermal Resistance Bottom Side
TINT
TCASE
ΦINT_TOP
ΦHOU
ΦINT_BOT
°C
Estimated thermal resistance to
maximum temperature internal
component from isothermal top
0.97
°C/W
Estimated thermal resistance of thermal
coupling between the top and bottom
case surfaces
0.57
°C/W
Estimated thermal resistance to
maximum temperature internal
component from isothermal bottom
0.67
°C/W
54
Ws/°C
Thermal Capacity
Assembly
Storage
Temperature
TST
BCM4414xD1E13A2yzz (T-Grade)
-40
125
°C
BCM4414xD1E13A2yzz (C-Grade)
-40
125
°C
ESDHBM
Human Body Model,
“ESDA / JEDEC JDS-001-2012” Class I-C
(1kV to < 2kV)
1000
ESDCDM
Charge Device Model,
“JESD 22-C101-E” Class II (200V to
< 500V)
200
ESD Withstand
BCM® in a VIA™ Package
Rev 1.7
Page 17 of 43 08/2020
BCM4414xD1E13A2yzz
General Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
-40°C ≤ TCASE ≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
780
940
pF
Safety
Isolation Capacitance
CHI_LO
Unpowered unit
620
Isolation Resistance
RHI_LO
At 500VDC
10
MTBF
MΩ
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
2.31
MHrs
Telcordia Issue 2 - Method I Case III;
25°C Ground Benign, Controlled
3.41
MHrs
cTÜVus EN 60950-1
Agency Approvals / Standards
cURus UL60950-1
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
BCM® in a VIA™ Package
Rev 1.7
Page 18 of 43 08/2020
BCM4414xD1E13A2yzz
BCM in a VIA Package
ILO
IHI
RLO
+
+
K • ILO
VHI
+
IHI_Q
–
V•I
K
+
K • VHI
VLO
–
–
–
Figure 19 — BCM DC model (Forward Direction)
The BCM uses a high frequency resonant tank to move energy
from the high voltage side to the low voltage side and vice versa.
The resonant LC tank, operated at high frequency, is amplitude
modulated as a function of the HI side voltage and the LO side
current. A small amount of capacitance embedded in the high
voltage side and low voltage side stages of the module is sufficient
for full functionality and is key to achieving high power density.
The effective DC voltage transformer action provides additional
interesting attributes. Assuming that RLO = 0Ω and IHI_Q = 0A,
Eq. (3) now becomes Eq. (1) and is essentially load independent,
resistor R is now placed in series with VHI.
The BCM4414xD1E13A2yzz can be simplified into the model shown
in Figure 19.
R
R
At no load:
Vin
VHI
VLO = VHI • K
VLO
In the presence of a load, VLO is represented by:
VLO = VHI • K – ILO • RLO
(3)
The relationship between VHI and VLO becomes:
VLO = (VHI – IHI • R) • K
IHI – IHI_Q
K
(4)
RLO represents the impedance of the BCM and is a function of the
RDS_ON of the HI side and LO side MOSFETs, PC board resistance of
HI side and LO side boards and the winding resistance of the power
transformer. IHI_Q represents the HI side quiescent current of the
BCM controller, gate drive circuitry and core losses.
(5)
Substituting the simplified version of Eq. (4)
(IHI_Q is assumed = 0A) into Eq. (5) yields:
VLO = VHI • K – ILO • R • K 2
and ILO is represented by:
ILO =
V
Vout
LO
Figure 20 — K = 1/32 BCM with series HI side resistor
(2)
VHI
BCM
SAC
1/32
KK == 1/32
(1)
K represents the “turns ratio” of the BCM.
Rearranging Eq (1):
K =
+
–
(6)
This is similar in form to Eq. (3), where RLO is used to represent the
characteristic impedance of the BCM. However, in this case a real
resistor, R, on the high voltage side of the BCM is effectively scaled
by K 2 with respect to the low voltage side.
Assuming that R = 1Ω, the effective R as seen from the low voltage
side is 1.0mΩ, with K = 1/32.
BCM® in a VIA™ Package
Rev 1.7
Page 19 of 43 08/2020
BCM4414xD1E13A2yzz
A similar exercise can be performed with the addition of a
capacitor or shunt impedance at the high voltage side of the BCM.
A switch in series with VHI is added to the circuit. This is depicted in
Figure 21.
SS
VVin
HI
+
–
BCM
SAC
K=
= 1/32
1/32
K
C
VVout
LO
A solution for keeping the impedance of the BCM low involves
switching at a high frequency. This enables the use of small
magnetic components because magnetizing currents remain low.
Small magnetics mean small path lengths for turns. Use of low loss
core material at high frequencies also reduces core losses.
Figure 21 — BCM with High side capacitor
A change in VHI with the switch closed would result in a change in
capacitor current according to the following equation:
dVHI
IC (t) = C
(7)
dt
Low impedance is a key requirement for powering a highcurrent, low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a BCM
between the regulation stage and the point of load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, these benefits are
not achieved if the series impedance of the BCM is too high. The
impedance of the BCM must be low, i.e., well beyond the crossover
frequency of the system.
The two main terms of power loss in the BCM module are:
n No load power dissipation (PHI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
n Resistive loss (PR ): refers to the power loss across
LO
Assume that with the capacitor charged to VHI, the switch is
opened and the capacitor is discharged through the idealized BCM.
In this case,
IC = ILO • K
(8)
the BCM module modeled as pure resistive impedance.
PDISSIPATED = PHI_NL + PRLO
Therefore,
PLO_OUT = PHI_IN – PDISSIPATED = PHI_IN – PHI_NL – PRLO
substituting Eq. (1) and (8) into Eq. (7) reveals:
ILO(t) =
C
K2
•
dVLO
dt
(9)
(10)
(11)
The above relations can be combined to calculate the overall
module efficiency:
The equation in terms of the LO side has yielded a K 2 scaling factor
for C, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger capacitance
on the low voltage side when expressed in terms of the high
voltage side. With K = 1/32 as shown in Figure 21, C = 1µF would
appear as C = 1024µF when viewed from the low voltage side.
η=
=
PLO_OUT
PHI_IN
PHI_IN – PHI_NL – PRLO
PHI_IN
VHI • IHI – PHI_NL – (ILO)2 • RLO
= 1 –
BCM® in a VIA™ Package
Rev 1.7
Page 20 of 43 08/2020
=
VHI • IHI
(
)
PHI_NL + (ILO)2 • RLO
VHI • IHI
(12)
BCM4414xD1E13A2yzz
Thermal Considerations
ΦINT
+ TC_BOT
–
The VIA package provides effective conduction cooling from either
of the two module surfaces. Heat may be removed from the top
surface, the bottom surface or both. The extent to which these
two surfaces are cooled is a key component for determining the
maximum power that can be processed by a VIA, as can be seen
from the specified thermal operating area in Figure 1. Since the
VIA has a maximum internal temperature rating, it is necessary to
estimate this temperature based on a system-level thermal solution.
For this purpose, it is helpful to simplify the thermal solution into
a roughly equivalent circuit where power dissipation is modeled as
a current source, isothermal surface temperatures are represented
as voltage sources and the thermal resistances are represented as
resistors. Figure 22 shows the “thermal circuit” for the VIA module.
s
PDISS
s
Figure 23 — Single-sided cooling VIA thermal model
n Double side cooling: while this option might bring limited
+
ΦINT_TOP
TC_TOP
–
ΦHOU
–
PDISS
ΦINT_BOT
s
Current Sharing
TC_BOT
+
The performance of the BCM is based on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with a positive temperature
coefficient series resistance.
s
Figure 22 — Double-sided cooling VIA thermal model
In this case, the internal power dissipation is PDISS, ΦINT_TOP
and ΦINT_BOT are the thermal resistance characteristics of the
VIA module and the top and bottom surface temperatures are
represented as TC_TOP and TC_BOT. It is interesting to note that the
package itself provides a high degree of thermal coupling between
the top and bottom case surfaces (represented in the model by the
resistor ΦHOU). This feature enables two main options regarding
thermal designs:
n Single side cooling: the model of Figure 22 can be simplified by
calculating the parallel resistor network and using one simple
thermal resistance number and the internal power dissipation
curves; an example for bottom side cooling only is shown in
Figure 23.
In this case, ΦINT can be derived as follows:
ΦINT =
(ΦINT_TOP + ΦHOU) • ΦINT_BOT
ΦINT_TOP + ΦHOU + ΦINT_BOT
advantage to the module internal components (given the
surface-to-surface coupling provided), it might be appealing in
cases where the external thermal system requires allocating
power to two different elements, such as heatsinks with
independent airflows or a combination of chassis/air cooling.
This type of characteristic is close to the impedance characteristic
of a DC power distribution system both in dynamic (AC) behavior
and for steady state (DC) operation.
When multiple BCM modules of a given part number are
connected in an array, they will inherently share the load current
according to the equivalent impedance divider that the system
implements from the power source to the point of load. Ensuring
equal current sharing among modules requires that BCM array
impedances be matched.
Some general recommendations to achieve matched array
impedances include:
n Dedicate common copper planes/wires within the PCB/Chassis
to deliver and return the current to the modules.
n Provide as symmetric a PCB/Wiring layout as possible
among modules
(13)
For further details see AN:016 Using BCM Bus Converters
in High Power Arrays.
BCM® in a VIA™ Package
Rev 1.7
Page 21 of 43 08/2020
BCM4414xD1E13A2yzz
Dielectric Withstand
VHI
ZHI_EQ1
BCM®1
ZLO_EQ1
R0_1
ZHI_EQ2
BCM®2
The chassis of the BCM in a VIA package is required to be
connected to Protective Earth when installed in the end application
and must satisfy the requirements of IEC 60950-1 for
Class I products.
VLO
ZLO_EQ2
R0_2
+ DC
Load
ZHI_EQn
BCM®n
ZLO_EQn
R0_n
The BCM in a VIA package contains an internal safety approved
isolating component (ChiP) that provides Reinforced Insulation from
high voltage side to low voltage side. The isolating component is
individually tested for Reinforced Insulation from the high voltage
side to the low voltage side at 4242VDC prior to final assembly
of the VIA. The Reinforced Insulation can only be tested on the
completed VIA assembly at Basic Insulation values, as specified
in the electric strength Test Procedure noted in clause 5.2.2 of
IEC 60950-1.
Test Procedure Note from IEC 60950-1
Figure 24 — BCM module array
“For equipment incorporating both REINFORCED INSULATION and
lower grades of insulation, care is taken that the voltage applied
to the REINFORCED INSULATION does not overstress BASIC
INSULATION or SUPPLEMENTARY INSULATION.”
Fuse Selection
Summary
In order to provide flexibility in configuring power systems, BCM in
a VIA package modules are not internally fused. Input line fusing
of BCM products is recommended at the system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
n Current rating
(usually greater than maximum current of BCM module)
n Maximum voltage rating
(usually greater than the maximum possible input voltage)
n Ambient temperature
n Nominal melting I2t
n Recommend fuse: 10A Littelfuse 505 Series or
The final VIA assembly provides basic insulation from the high
voltage side to case, basic insulation from the high voltage side to
the low voltage side and functional insulation from low voltage
side to case. The case is required to be connected to protective
earth in the final installation. The protective earth connection can
be accomplished through a dedicated wiring harness (example: ring
terminal clamped by mounting screw) or surface contact (example:
pressure contact on bare conductive chassis or PCB copper layer
with no solder mask).
The ground connection of the top case must be 3 orders of
magnitude more resistive than the current return connection to
the bottom case. The construction of the VIA can be summarized
by describing it as a “Class II” component installed in a “Class I”
subassembly. The insulation from the high voltage side to the low
voltage side can only be tested at basic insulation values on the
fully assembled VIA product.
10A Littelfuse 487 Series (HI side)
ChiP Isolation
Reverse Operation
BCM modules are capable of reverse power operation. Once the
unit is started, energy will be transferred from the low voltage
side back to the high voltage side whenever the low voltage side
exceeds VHI • K. The module will continue operation in this fashion
as long as no faults occur.
High voltage side
SELV
The BCM4414xD1E13A2yzz has not been qualified for continuous
operation in a reverse power condition. However, fault protections
that help to protect the module in forward operation will also
protect the module in reverse operation.
Transient operation in reverse is expected in cases where there is
significant energy storage on the low voltage side and transient
voltages appear on the high voltage side.
Low voltage side
RI
Figure 25 — ChiP before final assembly in the VIA
BCM® in a VIA™ Package
Rev 1.7
Page 22 of 43 08/2020
BCM4414xD1E13A2yzz
HV VIA Isolation Drawing
- LO
EMI
Receiver
- LO
+HI
+LO
ChiP
Input
Output
SELV
VIA Input Board
DC
Power
Supply
VIA Output Board
-HI
+LO
Screen
Room /
Filters
LISN
LISN
+HI
+LO
Single
VIA BCM
(DUT)
–HI
–LO
Load
RI
- LO
BI
- LO
PE
FI
Figure 27 — Typical test setup block diagram for
Conducted Emissions
Hot-Swap
Figure 26 — BCM in a VIA package after final assembly
Filtering
The BCM in a VIA package has built-in single stage EMI filtering
with Hot-Swap circuitry located on the high voltage side. The
integrated EMI filtering consists of a common mode choke,
differential mode capacitors, and Y2 common mode capacitors. A
typical test set-up block diagram for conducted emissions is shown
in Figure 27.
The built-in EMI filtering reduces the HI side voltage ripple. External
LO side filtering can be added as needed, with ceramic capacitance
used as a LO side bypass for this purpose. The filtering, along
with Hot-Swap circuitry, protects the BCM in a VIA package from
overvoltage transients imposed by a system that would exceed
maximum ratings. VIA HI side and LO side voltage ranges shall not
be exceeded. An internal overvoltage function prevents operation
outside of the normal operating HI side range. However, the VIA
is exposed to the applied voltage even when disabled and must
withstand it.
The source response is generally the limiting factor in the
overall system response, given the wide bandwidth of the BCM.
Anomalies in the response of the source will appear at the LO side
of the module multiplied by its K factor.
Total load capacitance at the LO side of the BCM shall not exceed
the specified maximum to ensure correct operation in startup.
Due to the wide bandwidth and small LO side impedance of the
BCM, low frequency bypass capacitance and significant energy
storage may be more densely and efficiently provided by adding
capacitance at the HI side of the BCM.
At frequencies less than 500kHz, the BCM appears as an
impedance of RLO between the source and load. Within this
frequency range, capacitance connected at the HI side appears as
an effective scaled capacitance on the LO side per the relationship
defined in equation (14).
This enables a reduction in the size and number of capacitors used
in a typical system.
CLO =
CHI
K2
(14)
Many applications use a power architecture based on a 380VDC
distribution bus. This supply level is emerging as a new standard
for efficient distribution of power through board, rack and chassis
mounted telecom and datacom systems. The interconnection
between the different modules is accomplished with a backplane
and motherboard. Power is commonly provided to the various
module slots via a 380VDC distribution bus.
In the event of a fault, removal of the faulty module from the rack
is relatively easy, provided that the remaining power modules can
support the step increase in load. Plugging in the replacement
module has more potential for problems, as it presents an
uncharged capacitor load and will draw a large inrush current. This
could cause a momentary, but unacceptable interruption or sag
in the backplane power bus if not limited. Additional problems
may arise if ordinary power module connectors are used, since
the connector pins will engage and disengage in a random and
unpredictable sequence during insertion and removal.
Hot-Swap or hot-plug is a highly desirable feature in many
applications, but also results in several issues that must be
addressed in the system design. A number of related phenomena
occur with a live insertion and removal event, including contact
bouncing, arcing between HI side connector pins, and large voltage
and current transients. Hot-Swap circuitry in the converter modules
protects the module itself and the rest of the system from the
problems associated with live insertion.
This module provides a high level of integration for DC-DC
converters in 380VDC distribution systems, saving design time
and board space. To allow for maintenance, reconfiguration,
redundancy and system upgrades, the BCM in a VIA package is
designed to address the function of Hot-Swapping at the 380VDC
distribution bus. Hot-Swap circuitry, as shown in Figure 28, uses
an active MOSFET switching device in series with the HI side line.
During module insertion, the MOSFET is driven into a resistive state
to limit the inrush current as the input capacitance of the inserted
unit is charged. The MOSFET is fully enhanced once the module’s
HI side capacitor has sufficiently charged to minimize losses
during normal operation. Verification of the Hot-Swap circuitry
performance is illustrated through plots of the module’s response
to a live insertion event in Figures 30 and 31.
BCM® in a VIA™ Package
Rev 1.7
Page 23 of 43 08/2020
BCM4414xD1E13A2yzz
Hot-Swap Test – Scope Pictures
VHI
of VIA
BCM
VHI of ChiP
BCM
IHI of VIA
BCM
VLO of VIA
BCM
ChiP BCM
Charge
Pump
Hot-swap
Controller
Figure 28 — High level diagram for 384VDC BCM in a VIA package
showing internal Hot-Swap circuitry and ChiP BCM
The BCM in a VIA package provides the opportunity to incorporate
Hot-Swap capabilities into redundant power module arrays.
This allows telecoms and other mission critical applications to
continue operating without interruption even through failure and
replacement of one or more power modules.
Hot-Swap Test – Test circuit and Procedure
n Two parallel BCMs in a VIA package with mercury relay#1 open
Figure 30 — Hot-Swap start-up
Ch1: IHI of BCM#2
Ch2: VLO of BCM#2
Ch3: VHI of BCM#2 shows the fast voltage transient at the high side
terminal of BCM#2
Ch4: VHI of internal ChiP BCM#2 shows the soft start charging of
the high side capacitor.
n Close mercury relay#1 and measure inrush current going
into BCM#2
+HI
4000µF
+LO
DC
–HI
Maximum Input
Voltage
Electronic
Load
Max Load
BCM
#1
–LO
Mercury
Relay #1
+HI
+LO
BCM
#2
–HI
–LO
Figure 31 — Expanded time scale version of Figure 30 showing
startup of BCM#2
Figure 29 — Hot-Swap test circuit
BCM® in a VIA™ Package
Rev 1.7
Page 24 of 43 08/2020
BCM4414xD1E13A2yzz
System Diagram for PMBus® Interface
5V
EXT_BIAS
BCM in a VIA
Package
SCL
SDA
SGND
SCL
SDA
Host
PMBus®
SGND
ADDR
The controller of the BCM in a VIA package is referenced to the low voltage side signal ground (SGND).
The BCM in a VIA package provides the Host PMBus system with accurate telemetry monitoring and reporting, threshold and
warning limits adjustment, in addition to corresponding status flags. The standalone BCM is periodically polled for status by the host
PMBus. Direct communication to the BCM is enabled by a page command. For example, the page (0x00) prior to a telemetry inquiry
points to the controller data and page (0x01) prior to a telemetry inquiry points to the BCM parameters.
The BCM enables the PMBus compatible host interface with an operating bus speed of up to 400kHz. The BCM follows the PMBus
command structure and specification.
BCM® in a VIA™ Package
Rev 1.7
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BCM4414xD1E13A2yzz
PMBus® Interface
Where:
Refer to “PMBus Power System Management Protocol Specification
Revision 1.2, Part I and II” for complete PMBus specifications details
at http://pmbus.org.
X, is a “real world” value in units (A, V, °C, s)
Y, is a two’s complement integer received from the BCM controller
m, b and R are two’s complement integers defined as follows:
Device Address
Command
The PMBus address (ADDR Pin) should be set to one of the
predetermined 16 possible addresses shown in the table below
using a resistor between the ADDR pin and SGND pin.
The BCM accepts only a fixed and persistent address and does not
support SMBus address resolution protocol. At initial power-up, the
BCM controller will sample the address pin voltage and will keep
this address until device power is removed.
Code
m
R
b
TON_DELAY
60h
1
3
0
READ_VIN
88h
1
1
0
READ_IIN
89h
1
3
0
READ_VOUT [1]
8Bh
1
1
0
READ_IOUT
8Ch
1
2
0
READ_TEMPERATURE_1 [2]
8Dh
1
0
0
READ_POUT
96h
1
0
0
ID
Child
Address
HEX
Recommended
Resistor R ADDR (Ω)
1
1010 000b
50h
487
MFR_VIN_MIN
A0h
1
0
0
2
1010 001b
51h
1050
MFR_VIN_MAX
A1h
1
0
0
3
1010 010b
52h
1870
MFR_VOUT_MIN
A4h
1
0
0
4
1010 011b
53h
2800
MFR_VOUT_MAX
A5h
1
0
0
5
1010 100b
54h
3920
MFR_IOUT_MAX
A6h
1
0
0
6
1010 101b
55h
5230
MFR_POUT_MAX
A7h
1
0
0
7
1010 110b
56h
6810
READ_K_FACTOR
D1h
65536
0
0
8
1010 111b
57h
8870
READ_BCM_ROUT
D4h
1
5
0
9
1011 000b
58h
11300
10
1011 001b
59h
14700
11
1011 010b
5Ah
19100
12
1011 011b
5Bh
25500
13
1011 100b
5Ch
35700
14
1011 101b
5Dh
53600
15
1011 110b
5Eh
97600
16
1011 111b
5Fh
316000
[1] Default READ LO side voltage returned when BCM unit is disabled = –300V.
[2]
No special formatting is required when lowering the supervisory
limits and warnings.
Reported DATA Formats
The BCM controller employs a direct data format where all
reported measurements are in Volts, Amperes, Degrees Celsius,
or Seconds. The host uses the following PMBus specification
to interpret received values metric prefixes. Note that the
COEFFICIENTS command is not supported:
X=
(
1
m
)
Default READ Temperature returned when BCM unit is disabled = –273°C.
• (Y • 10-R - b)
BCM® in a VIA™ Package
Rev 1.7
Page 26 of 43 08/2020
BCM4414xD1E13A2yzz
Supported Command List
Default Data Content
Data Bytes
PAGE
Command
Code
00h
Access BCM stored information
Function
00h
1
OPERATION
01h
Turn BCM on or off
80h
1
CLEAR_FAULTS
03h
Clear all faults
N/A
None
CAPABILITY
19h
PMBus® key capabilities set by factory
20h
1
OT_FAULT_LIMIT
4Fh [1]
Overtemperature protection
64h
2
OT_WARN_LIMIT
51h [1]
Overtemperature warning
64h
2
VIN_OV_FAULT_LIMIT
55h [1]
High voltage side overvoltage protection
64h
2
VIN_OV_WARN_LIMIT
57h [1]
High voltage side overvoltage warning
64h
2
IIN_OC_FAULT_LIMIT
5Bh [1]
High voltage side overcurrent protection
64h
2
IIN_OC_WARN_LIMIT
5Dh [1]
High voltage side overcurrent warning
64h
2
TON_DELAY
60h [1]
Startup delay in addition to fixed delay
00h
2
STATUS_BYTE
78h
Summary of faults
00h
1
STATUS_WORD
79h
Summary of fault conditions
00h
2
STATUS_IOUT
7Bh
Overcurrent fault status
00h
1
STATUS_INPUT
7Ch
Overvoltage and undervoltage fault status
00h
1
7Dh
Overtemperature and undertemperature
fault status
00h
1
STATUS_CML
7Eh
PMBus communication fault
00h
1
STATUS_MFR_SPECIFIC
80h
Other BCM status indicator
00h
1
READ_VIN
88h
Reads HI side voltage
FFFFh
2
READ_IIN
89h
Reads HI side current
FFFFh
2
READ_VOUT
8Bh
Reads LO side voltage
FFFFh
2
READ_IOUT
8Ch
Reads LO side current
FFFFh
2
READ_TEMPERATURE_1
8Dh
Reads internal temperature
FFFFh
2
READ_POUT
96h
Reads LO side power
FFFFh
2
PMBUS_REVISION
98h
PMBus compatible revision
22h
1
MFR_ID
99h
BCM controller ID
“VI”
2
MFR_MODEL
9Ah
Internal controller or BCM model
Part Number
18
MFR_REVISION
9Bh
Internal controller or BCM revision
FW and HW revision
18
MFR_LOCATION
9Ch
Internal controller or BCM factory location
“AP”
2
MFR_DATE
9Dh
Internal controller or BCM manufacturing date
MFR_SERIAL
9Eh
Internal controller or BCM serial number
MFR_VIN_MIN
A0h
MFR_VIN_MAX
MFR_VOUT_MIN
STATUS_TEMPERATURE
“YYWW”
4
Serial Number
16
Minimum rated high side voltage
Varies per BCM
2
A1h
Maximum rated high side voltage
Varies per BCM
2
A4h
Minimum rated low side voltage
Varies per BCM
2
MFR_VOUT_MAX
A5h
Maximum rated low side voltage
Varies per BCM
2
MFR_IOUT_MAX
A6h
Maximum rated low side current
Varies per BCM
2
MFR_POUT_MAX
A7h
Maximum rated low side power
Varies per BCM
2
READ_K_FACTOR
D1h
Reads K factor
Varies per BCM
2
READ_BCM_ROUT
D4h
Reads low voltage side output resistance
Varies per BCM
2
646464646464h
6
00h
2
SET_ALL_THRESHOLDS
D5h [1]
Set supervisory warning and protection thresholds
DISABLE_FAULT
D7h [1]
Disable overvoltage, overcurrent or
undervoltage supervisory faults
[1]
The BCM must be in a disabled state with VHI < VHI_UVLO- and VDDB applied during a write message.
BCM® in a VIA™ Package
Rev 1.7
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BCM4414xD1E13A2yzz
Command Structure Overview
Write Byte protocol:
The Host always initiates PMBus® communication with a START bit. All messages are terminated by the Host with a STOP bit. In a write
message, the parent sends the child device address followed by a write bit. Once the child acknowledges, the parent proceeds with the
command code and then similarly the data byte.
1
7
1
1
S
Child Address
Wr
A
x=0
x=0
S
Start Condition
Sr
Repeated start Condition
8
Command Code
1
8
1
1
A
Data Byte
A
P
x=0
x=0
Rd Read
Wr Write
X
Indicated that field is required to have the value of x
A
Acknowledge (bit may be 0 for an ACK or 1 for a NACK)
P
Stop Condition
From Parent to Child
From Child to Parent
…
Continued next line
Figure 1 — PAGE COMMAND (00h), WRITE BYTE PROTOCOL
Read Byte protocol:
A Read message begins by first sending a Write Command, followed by a REPEATED START Bit and a child Address. After receiving the
READ bit, the BCM controller begins transmission of the Data responding to the Command. Once the Host receives the requested Data, it
terminates the message with a NACK preceding a stop condition signifying the end of a read transfer.
1
7
1
1
S
Child Address
Wr
A
x=0
x=0
8
Command Code
1
1
7
A Sr Child Address
x=0
1
1
Rd
A
x=1
x=0
Figure 2 — ON_OFF_CONFIG COMMAND (02h), READ BYTE PROTOCOL
BCM® in a VIA™ Package
Rev 1.7
Page 28 of 43 08/2020
8
Data Byte
1
1
A
P
x=1
BCM4414xD1E13A2yzz
Write Word protocol:
When transmitting a word, the lowest order byte leads the highest order byte. Furthermore, when transmitting a Byte, the least significant
bit (LSB) is sent last. Refer to System Management Bus (SMBus) specification version 2.0 for more details.
Note: Extended command and Packet Error Checking Protocols are not supported.
1
7
1
1
S
Child Address
Wr
A
x=0
x=0
8
1
8
A
Command Code
1
Data Byte Low
x=0
8
A
Data Byte High
x=0
1
1
A
P
x=0
Figure 3 — TON_DELAY COMMAND (D6h)_WRITE WORD PROTOCOL
Read Word protocol:
1
7
1
1
S
Child Address
Wr
A
x=0
x=0
8
1
Command Code
1
7
A Sr Child Address
x=0
1
1
Rd
A
x=1
x=0
8
1
Data Byte Low
A
x=0
Figure 4 — MFR_VIN_MIN COMMAND (88h)_READ WORD PROTOCOL
Write Block protocol:
1
7
1
1
S
Child Address
Wr
A
x=0
x=0
8
Data Byte 2
1
A
x=0
...
...
...
8
1
8
Byte Count = N
A
Command Code
x=0
8
Data Byte N
1
A
8
Data Byte 1
x=0
1
1
A
P
x=0
Figure 5 — SET_ALL_THRESHOLDS COMMAND (D5h)_WRITE BLOCK PROTOCOL
BCM® in a VIA™ Package
Rev 1.7
Page 29 of 43 08/2020
1
A
x=0
...
8
Data Byte High
1
1
A
P
x=1
BCM4414xD1E13A2yzz
Read Block protocol:
1
7
1
1
S
Child Address
Wr
A
x=0
x=0
1
8
Data Byte 1
8
1
7
x=0
8
A
1
A Sr Child Address
Command Code
1
Data Byte 2
A
x=0
x=0
...
...
...
8
Data Byte N
1
1
Rd
A
x=1
x=0
1
1
A
P
8
1
Data Byte = N
A
x=0
x=1
Figure 6 — SET_ALL_THRESHOLDS COMMAND (D5h)_READ BLOCK PROTOCOL
Write Group Command protocol:
1
7
1
1
S
Child Address
Wr
A
Command Code
A
First Device
x=0
x=0
First Command
x=0
1
7
Sr Child Address
Second Device
1
7
Sr Child Address
Nth Device
8
8
1
1
1
Wr
A
Command Code
A
x=0
x=0
Second Command
x=0
8
8
Data Byte Low
1
1
1
Wr
A
Command Code
A
x=0
x=0
Nth Command
x=0
8
Data Byte Low
1
8
Data Byte Low
1
8
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
1
8
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
1
8
Data Byte High
A
x=0
One or more Data Bytes
x=0
Note that only one command per device is allowed in a group command.
BCM® in a VIA™ Package
Rev 1.7
Page 30 of 43 08/2020
...
1
A
Figure 7 — DISABLE_FAULT COMMAND (D7h)_WRITE
...
P
...
BCM4414xD1E13A2yzz
Supported Commands Transaction Type
Page Command (00h)
A direct communication to the BCM controller and a simulated
communication to non-PMBus® devices is enabled by a page
command. Supported command access privileges with a preselected PAGE are defined in the following table. Deviation from
this table generates a communication error in
STATUS_CML register.
The page command data byte of 00h prior to a command call will
address the BCM controller specific data and a page data byte
of 01h would broadcast to the BCM. The value of the Data Byte
corresponds to the pin name trailing number with the exception of
00h and FFh.
Command
Code
Data Byte
PAGE Data Byte
Access Type
00h
01h
PAGE
00h
R/W
R/W
OPERATION
01h
R
R/W
CLEAR_FAULTS
03h
W
W
CAPABILITY
19h
R
OT_FAULT_LIMIT
4Fh
R/W
OT_WARN_LIMIT
51h
R/W
VIN_OV_FAULT_LIMIT
55h
R/W
VIN_OV_WARN_LIMIT
57h
R/W
IIN_OC_FAULT_LIMIT
5Bh
R/W
IIN_OC_WARN_LIMIT
5Dh
R/W
TON_DELAY
60h
STATUS_BYTE
78h
R/W
R
STATUS_WORD
79h
R
R
STATUS_IOUT
7Bh
R
R/W
STATUS_INPUT
7Ch
R
R/W
STATUS_TEMPERATURE
7Dh
R
R/W
STATUS_CML
7Eh
R/W
STATUS_MFR_SPECIFIC
80h
R
READ_VIN
88h
READ_IIN
89h
READ_VOUT
8Bh
READ_IOUT
8Ch
R
R
READ_TEMPERATURE_1
8Dh
R
R
READ_POUT
96h
R
R
PMBUS_REVISION
98h
R
MFR_ID
99h
R
MFR_MODEL
9Ah
R
R
MFR_REVISION
9Bh
R
R
MFR_LOCATION
9Ch
R
R
MFR_DATE
9Dh
R
R
MFR_SERIAL
9Eh
R
R
MFR_VIN_MIN
A0h
R
R
MFR_VIN_MAX
A1h
R
R
MFR_VOUT_MIN
A4h
R
R
MFR_VOUT_MAX
A5h
R
R
MFR_IOUT_MAX
A6h
R
R
MFR_POUT_MAX
A7h
R
R
READ_K_FACTOR
D1h
READ_BCM_ROUT
D4h
R
SET_ALL_THRESHOLDS
D5h
R/W
DISABLE_FAULT
D7h
R/W
Description
00h
BCM controller
01h
BCM
OPERATION Command (01h)
The OPERATION command can be used to turn on and off the
connected BCM.
If synchronous startup is required in the system, it is recommended
to use the command from host PMBus in order to achieve
simultaneous array startup.
R/W
Unit is On when asserted (default)
Reserved
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
b
R/W
R
R
R
R
This command accepts only two data values: 00h and 80h. If any
other value is sent the command will be rejected and a CML Data
error will result.
R
BCM® in a VIA™ Package
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CLEAR_FAULTS Command (03h)
This command clears all status bits that have been previously set.
Persistent or active faults are re-asserted again once cleared. All
faults are latched once asserted in the BCM controller. Registered
faults will not be cleared when shutting down the BCM powertrain
by recycling the BCM high side voltage or sending the
OPERATION command.
CAPABILITY Command (19h)
The VIN_UV_WARN_LIMIT (58h) and VIN_UV_FAULT_LIMIT
(59h) are set by the factory and cannot be changed by the host.
However, a host can disable the undervoltage setting using the
DISABLE_FAULT COMMAND (D7h).
All FAULT_RESPONSE commands are unsupported. The BCM
powertrain supervisory limits and powertrain protection will behave
as described in the Electrical Specifications. In general, once a fault
is detected, the BCM powertrain will shut down and attempt to
auto-restart after a predetermined delay.
TON_DELAY Command (60h)
Packet Error Checking is not supported
Maximum supported bus speed is 400kHz
The Device does not have SMBALERT# pin and does
not support the SMBus Alert Response protocol
The value of this register word is set in non-volatile memory and
can only be written when the BCM is disabled.
The maximum possible delay is 100ms. Default value is set to
(00h). The reported value can be interpreted using the
following equation.
Reserved
TON_DELAYACTUAL = tREPORTED • 10 -3(s)
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
b
The BCM controller returns a default value of 20h. This value
indicates that the PMBus® frequency supported is up to 400kHz
and that both Packet Error Checking (PEC) and SMBALERT# are
not supported.
Staggering startup in an array is possible with the TON_DELAY
Command. This delay will be in addition to any startup delay
inherent in the BCM module. For example: startup delay from
application of VHI is typically 20ms. When TON_DELAY is greater
than zero, the set delay will be added to it.
OT_FAULT_LIMIT Command (4Fh),
OT_WARN_ LIMIT Command (51h),
VIN_OV_FAULT_ LIMIT Command (55h),
VIN_OV_WARN_ LIMIT Command (57h),
IIN_OC_FAULT_ LIMIT Command (5Bh),
IIN_OC_WARN_ LIMIT Command (5Dh)
The values of these registers are set in non-volatile memory and
can only be written when the BCM is disabled.
The values of the above mentioned faults and warnings are set by
default to 100% of the respective BCM model supervisory limits.
However, these limits can be set to a lower value. For example: In
order for a limit percentage to be set to 80%, one would send a
write command with a (50h) Data Word.
Any values outside the range of (00h – 64h) sent by a host will be
rejected, will not override the currently stored value and will set the
Unsupported Data bit in STATUS_CML.
The SET_ALL_THRESHOLDS COMMAND (D5h) combines in one
block overtemperature fault and warning limits, VHI overvoltage
fault and warning limits as well as ILO overcurrent fault and warning
limits. A delay prior to a read command of up to 200ms following a
write of new value is required.
BCM® in a VIA™ Package
Rev 1.7
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STATUS_BYTE (78h) and STATUS_WORD (79h)
STATUS_WORD
High Byte
Low Byte
STATUS_BYTE
UNIT IS BUSY
Not Supported: UNKNOWN FAULT OR WARNING
UNIT IS OFF
Not Supported: OTHER
Not Supported: FAN FAULT OR WARNING
Not Supported: VOUT_OV_FAULT
POWER_GOOD Negated*
IOUT_OC_FAULT
VIN_UV_FAULT
STATUS_MFR_SPECIFIC
TEMPERATURE FAULT OR WARNING
INPUT FAULT OR WARNING
PMBusTM COMMUNICATION EVENT
IOUT/POUT FAULT OR WARNING
Not Supported: VOUT FAULT OR WARNING
NONE OF THE ABOVE
7
6
5
4
3
2
1
0
7
0
1
1
1
1
0
0
0
1
6
1
5
0
4
1
3
2
1
1
1
0
1
0
b
* equal to POWER_GOOD#
All fault or warning flags, if set, will remain asserted until cleared
by the host or once the BCM and VDDB power is removed.
This includes undervoltage fault, overvoltage fault, overvoltage
warning, overcurrent warning, overtemperature fault,
overtemperature warning, undertemperature fault, reverse
operation, communication faults and analog controller
shutdown fault.
If the BCM controller is powered through VDDB, it will retain the
last telemetry data and this information will be available to the user
via a PMBus Status request. This is in agreement with the PMBus
standard, which requires that status bits remain set until specifically
cleared. Note that in the case where the BCM VHI is lost, the status
will always indicate an undervoltage fault, in addition to any other
fault that occurred.
Asserted status bits in all status registers, with the exception of
STATUS_WORD and STATUS_BYTE, can be individually cleared.
This is done by sending a data byte with one in the bit position
corresponding to the intended warning or fault to be cleared. Refer
to the PMBus® Power System Management Protocol Specification –
Part II – Revision 1.2 for details.
NONE OF THE ABOVE bit will be asserted if either the
STATUS_MFR_SPECIFIC (80h) or the High Byte of the
STATUS WORD is set.
STATUS_IOUT (7Bh)
The POWER_GOOD# bit reflects the state of the device and does
not reflect the state of the POWER_GOOD# signal limits. The
POWER_GOOD_ON COMMAND (5Eh) and POWER_GOOD_OFF
COMMAND (5Fh) are not supported. The POWER_GOOD# bit is
set, when the BCM is not in the active state, to indicate that the
powertrain is inactive and not switching. The POWER_GOOD#
bit is cleared, when the BCM is in the active state, 5ms after the
powertrain is activated allowing for soft-start to elapse.
POWER_GOOD# and OFF bits cannot be cleared as they always
reflect the current state of the device.
IOUT_OC_FAULT
Not Supported: IOUT_OC_LV_FAULT
IOUT_OC_WARNING
Not Supported: IOUT_UC_FAULT
Not Supported: Current Share Fault
Not Supported: In Power Limiting Mode
Not Supported: POUT_OP_FAULT
Not Supported: POUT_OP_WARNING
The Busy bit can be cleared using CLEAR_ALL Command (03h) or
by writing either data value (40h, 80h) to PAGE (00h) using the
STATUS_BYTE (78h).
Fault reporting, such as SMBALERT# signal output, and host
notification by temporarily acquiring bus parent status is
not supported.
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
b
Unsupported bits are indicated above. A one indicates a fault.
BCM® in a VIA™ Package
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BCM4414xD1E13A2yzz
STATUS_INPUT (7Ch)
STATUS_MFR_SPECIFIC (80h)
Reserved
VIN_OV_FAULT
PAGE Data Byte = (01h)
Reserved
VIN_OV_WARNING
Reserved
Not Supported: VIN_UV_WARNING
Reserved
VIN_UV_FAULT
Not Supported: Unit Off For Insufficient
Input Voltage
Reserved
BCM UART CML
Not Supported: IIN_OC_FAULT
Hardware Protections Shutdown Fault
Not Supported: IIN_OC_WARNING
BCM Reverse Operation
Not Supported: PIN_OP_WARNING
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
0
b
Unsupported bits are indicated above. A one indicates a fault.
STATUS_TEMPERATURE (7Dh)
OT_FAULT
OT_WARNING
Not Supported: UT_WARNING
UT_FAULT
Reserved
Reserved
Reserved
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
b
The reverse operation bit, if asserted, indicates that the BCM is
processing current in reverse. Reverse current reported value is
not supported.
The BCM has hardware protections and supervisory limits. The
hardware protections provide an additional layer of protection
and have the fastest response time. The Hardware Protections
Shutdown Fault, when asserted, indicates that at least one of the
powertrain protection faults is triggered. This fault will also be
asserted if a disabled fault event occurs after asserting any bit using
the DISABLE_FAULTS COMMAND.
The BCM UART is designed to operate with the controller UART.
If the BCM UART CML is asserted, it may indicate a hardware or
connection issue between both devices.
Reserved
Reserved
PAGE Data Byte = (00h)
Reserved
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
0
Reserved
b
BCM at PAGE (01h) is present
Reserved
Unsupported bits are indicated above. A one indicates a fault.
BCM UART CML
STATUS_CML (7Eh)
Hardware Protections Shutdown Fault
BCM Reverse Operation
Invalid Or Unsupported Command Received
Invalid Or Unsupported Data Received
Not Supported: Packet Error Check Failed
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
b
Not Supported: Memory Fault Detected
Not Supported: Processor Fault Detected
Reserved
Other Communication Faults
Not Supported: Other Memory Or Logic
Fault
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
0
b
When the PAGE COMMAND (00h) data byte is equal to (00h), the
BCM Reverse operation, Analog Controller Shutdown Fault, and
BCM UART CML bit will return the result of the active BCM. The
BCM UART CML will also be asserted if the active BCM
stops responding. The BCM must communicate at least once
to the internal controller in order to trigger this FAULT. The BCM
UART CML can be cleared using the PAGE (00h) CLEAR_FAULTS
(03h) Command.
Unsupported bits are indicated above. A one indicates a fault.
The STATUS_CML data byte will be asserted when an unsupported
PMBus® command or data or other communication fault occurs.
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Rev 1.7
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BCM4414xD1E13A2yzz
READ_VIN Command (88h)
READ_POUT Command (96h)
If PAGE data byte is equal to (01h), command will return the BCM’s
HI side voltage in the following format:
If PAGE data byte is equal to (01h), command will return the BCM’s
LO side power in the following format:
PLO_ACTUAL = PLO_REPORTED (W)
VHI_ACTUAL = VHI_REPORTED • 10 -1(V)
READ_IIN Command (89h)
If PAGE data byte is equal to (01h), command will return the BCM’s
HI side current in the following format:
IHI_ACTUAL = IHI_REPORTED • 10 -3(A)
If PAGE data byte is equal (00h), command will also return the
BCM’s HI side current.
READ_VOUT Command (8Bh)
If PAGE data byte is equal to (01h), command will return the BCM’s
LO side voltage in the following format:
VLO_ACTUAL = VLO_REPORTED • 10 -1(V)
If PAGE data byte is equal to (00h), command will also return the
BCM’s LO side power.
MFR_VIN_MIN Command (A0h),
MFR_VIN_MAX Command (A1h),
MFR_VOUT_MIN Command (A4h),
MFR_VOUT_MAX Command (A5h),
MFR_IOUT_MAX Command (A6h),
MFR_POUT_MAX Command (A7h)
These values are set by the factory and indicate the device
HI side/LO side voltage and LO side current range and LO side
power capacity.
If the PAGE data byte is equal to (00h - 01h), commands report the
rated BCM HI side voltage minimum and maximum in Volts, LO side
voltage minimum and maximum in Volts, LO side current maximum
in Amperes and LO side power maximum in Watts.
READ_IOUT Command (8Ch)
If PAGE data byte is equal to (01h), command will return the BCM’s
LO side current in the following format:
ILO_ACTUAL = ILO_REPORTED • 10 -2(A)
If PAGE data byte is equal (00h), command will also return the
BCM’s LO side current.
READ_TEMPERATURE_1 Command (8Dh)
If PAGE data byte is equal to (01h), command will return the BCM’s
temperature in the following format:
TACTUAL = ±TREPORTED (°C)
If PAGE data byte is equal (00h), command will also return the
BCM’s temprature.
BCM® in a VIA™ Package
Rev 1.7
Page 35 of 43 08/2020
BCM4414xD1E13A2yzz
READ_K_FACTOR Command (D1h)
DISABLE_FAULT Command (D7h)
If PAGE data byte is equal to (01h), command will return the BCM’s
K factor in the following format:
DISABLE_FAULT
MSB
K_FACTORACTUAL = K_FACTORREPORTED • 2 -16(V/V)
LSB
Reserved
Reserved
Reserved
Reserved
IOUT_OC_FAULT
Reserved
The K factor is defined in the BCM to represent the ratio of the
transformer winding and hence is equal to VLO / VHI.
Reserved
Reserved
VIN_OV_FAULT
Reserved
Reserved
READ_BCM_ROUT Command (D4h)
Reserved
VIN_UV_FAULT
Reserved
Reserved
If PAGE data byte is equal to (01h), command will return the BCM’s
LO side resistance in the following format:
Reserved
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
7
0
6
0
5
1
4
0
3
1
2
0
1
0
0
0
b
BCM_RLO_ACTUAL = BCM_RLO_REPORTED • 10 (Ω)
-5
SET_ALL_THRESHOLDS Command (D5h)
Unsupported bits are indicated above. A one indicates that the
supervisory fault associated with the asserted bit is disabled.
The values of this register block are set in non-volatile memory and
can only be written when the BCM is disabled.
SET_ALL_THRESHOLDS_BLOCK (6 Bytes)
IOUT_OC_WARN_ LIMIT
IOUT_OC_FAULT_ LIMIT
VIN_OV_WARN_ LIMIT
VIN_OV_FAULT_ LIMIT
OT_WARN_LIMIT
This command allows the host to disable the supervisory faults
and respective statuses. It does not disable the powertrain analog
protections or warnings with respect to the set limits in the
SET_ALL_THRESHOLDS Command.
The HI side undervoltage can only be disabled to a pre-set low
limit as specified in the mOnitored Telemetry Functional
Reporting Range.
OT_FAULT_LIMIT
5
4
3
2
1
0
64 64 64 64 64 64
h
The values of this register block are set in non-volatile memory and
can only be written when the BCM is disabled.
This command provides a convenient way to configure all of the
limits, or any combination of limits described previously using
one command.
VHI overvoltage, overcurrent and overtemperature values are all set
to 100% of the specified supervisory limits by default and can only
be set to a lower percentage.
To leave a particular threshold unchanged, set the corresponding
threshold data byte to a value greater than (64h).
BCM® in a VIA™ Package
Rev 1.7
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BCM4414xD1E13A2yzz
The BCM Controller Implementation vs.
PMBus® Specification Rev 1.2
3. The unsupported PMBus command code response as described
in the Fault Management and Reporting:
n Deviations from the PMBus specification:
The BCM controller is an I2C compliant, SMBus™ compatible device
and PMBus command compliant device. This section denotes some
deviation, perceived as differences from the PMBus Part I and Part II
specification Rev 1.2.
a. PMBus section 10.2.5.3, exceptions
• The busy bit of the STATUS_BYTE as implemented can
be cleared (80h). In order to maintain compatibility with
the specification, (40h) can also be used.
1. The PMBus interface meets all Part I and II PMBus specification
requirements with the following differences to the
transport requirement.
n Manufacturer Implementation of the PMBus Spec:
a. PMBus section 10.5, setting the response to a detected
fault condition
Unmet DC parameter Implementation vs SMBus™ spec
Symbol
VIL
[a]
VIH [a]
ILEAK_PIN
[a]
[b]
[b]
Parameter
PMBus
Interface
SMBus™
Rev 2.0
Min
Max
Min
Max
Input Low Voltage
-
0.99
-
0.8
V
Input High Voltage
2.31
-
2.1
VVDD_IN
V
10
22
-
±5
µA
Input Leakage per Pin
• All powertrain responses are pre-set and cannot be
changed.
Units
b. PMBus section 10.6, reporting faults and warnings
to the Host
• SMBALERT# signal and Direct PMBus Device to Host
Communication are not supported. However, the
PMBus interface will set the corresponding fault status
bits and will wait for the host to poll.
VVDD_IN = 3.3V
VBUS = 5V
c. PMBus section 10.7, clearing a shutdown due to a fault
2. The BCM controller accepts 38 PMBus command codes.
Implemented commands execute functions as described in the
PMBus specification.
• There is no RESET pin or EN pin in the BCM. Cycling
power to the BCM will not clear a BCM Shutdown. The
BCM will clear itself once the fault condition is removed.
n Deviations from the PMBus specification:
d. PMBus Section 10.8.1, corrupted data transmission faults:
a. Section 15, fault related commands
• Packet error checking is not supported.
• The Limits and Warnings unit is implemented as a
percentage (%) range from decimal (0-100) of the
factory set limits.
Data Transmission Faults Implementation
This section describes data transmission faults as implemented in the BCM controller.
Response to Host
Section
Description
NAK
FFh
STATUS_BYTE
CML
STATUS_CML
Other Fault
10.8.1
Corrupted data
10.8.2
Sending too few bits
X
X
10.8.3
Reading too few bits
X
X
10.8.4
Host sends or reads too
few bytes
X
X
10.8.5
Host sends too many
bytes
10.8.6
Reading too many bytes
10.8.7
Device busy
Unsupported
Data
Notes
No response; PEC not supported
X
X
X
X
X
X
BCM® in a VIA™ Package
Rev 1.7
Page 37 of 43 08/2020
X
X
Device will ACK own address
BUSY bit in STATUS_BYTE even if
STATUS_WORD is set
BCM4414xD1E13A2yzz
Data Content Faults Implementation
This section describes data content fault as implemented in the BCM controller.
Response
Section
Description
to Host
STATUS_BYTE
STATUS_CML
NAK
CML
Other
Fault
X
Unsupported
Command
Unsupported
Data
10.9.1
Improperly set read bit
in the address byte
X
X
10.9.2
Unsupported
command code
X
X
10.9.3
Invalid or
unsupported data
X
X
10.9.4
Data out of range
X
X
10.9.5
Reserved bits
BCM® in a VIA™ Package
Rev 1.7
Page 38 of 43 08/2020
Notes
X
No response; not a fault
BCM® in a VIA™ Package
Rev 1.7
Page 39 of 43 08/2020
DIM 'B'
1.150 [29.200]
1.277 [32.430]
1.277 [32.430]
1.757 [44.625]
1.02 [25.96]
1.61 [40.93]
1.61 [40.93]
1.61 [40.93]
1.02 [25.96]
1.02 [25.96]
1.61 [40.93]
1.61 [40.93]
1.65 [41.93]
1.61 [40.93]
2.17 [55.12]
2.17 [55.12]
1.61 [40.93]
2.17 [55.12]
2814 (1 STAGE) 2223
3414 (1 STAGE) 3623
3714 (1 STAGE) 4623
3814 (0 STAGE) 2361
3814 (0 STAGE) 2361 NBM
4414 (1 STAGE) 2361
4414 (1 STAGE) 6123
4414 (1 STAGE) 6123 UHV
4414 (1 STAGE) 6123 3kV
4914 (2 STAGE) 2361
4914 (2 STAGE) 6123
5614 (1 STAGE) 9223
6114 (2 STAGE) 9223
2.970 [75.445]
2.970 [75.445]
1.757 [44.625]
1.277 [32.430]
1.658 [42.110]
1.718 [43.625]
1.277 [32.430]
.788 [20.005]
NA
.788 [20.005]
NA
2814 (0 STAGE) 3623
DIM ‘B’
DIM ‘A’
1.02 [25.96]
6.13 [155.57]
5.57 [141.37]
4.91 [124.75]
4.91 [124.75]
4.35 [110.55]
4.35 [110.55]
4.35 [110.55]
4.35 [110.55]
3.76 [95.59]
3.76 [95.59]
3.75 [95.13]
3.38 [85.93]
2.84 [72.05]
2.80 [71.00]
2.25 [57.12]
DIM ‘C’
DIM 'C'
86(7
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湘ICP备2023018690号
