VTM48ET020T080A00

VTM48 E x 020 y 080A00 VTM Current Multiplier TM S ® C US C NRTL US FEATURES • 48 Vdc to 2 Vdc 80 A current multiplier - Operating from standard 48 V or 24 V PRMTM regulators • High efficiency (>92%) reduces system power consumption • High density (272 A/in3) • “Full Chip” V• I Chip package enables surface mount, low impedance interconnect to system board • Contains built-in protection features: Overvoltage Lockout Overcurrent Short Circuit Overtemperature • Provides enable / disable control, internal temperature monitoring • ZVS / ZCS resonant Sine Amplitude Converter topology • Less than 50ºC temperature rise at full load in typical applications TYPICAL APPLICATIONS DESCRIPTION The V• I ChipTM current multiplier is a high efficiency (>92%) Sine Amplitude ConverterTM (SACTM) operating from a 26 to 55 Vdc primary bus to deliver an isolated output. The Sine Amplitude Converter offers a low AC impedance beyond the bandwidth of most downstream regulators; therefore capacitance normally at the load can be located at the input to the Sine Amplitude Converter. Since the K factor of the VTM48EF020T080A00 is 1/24, the capacitance value can be reduced by a factor of 576, resulting in savings of board area, materials and total system cost. The VTM48EF020T080A00 is provided in a V• I Chip package compatible with standard pick-and-place and surface mount assembly processes. The co-molded V•I Chip package provides enhanced thermal management due to a large thermal interface area and superior thermal conductivity. The high conversion efficiency of the VTM48EF020T080A00 increases overall system efficiency and lowers operating costs compared to conventional approaches. The VTM48EF020T080A00 enables the utilization of Factorized Power ArchitectureTM which provides efficiency and size benefits by lowering conversion and distribution losses and promoting high density point of load conversion. VIN = 26 to 55 V VOUT = 0.5 to 2.3 V (NO LOAD) PART NUMBERING PART NUMBER PACKAGE STYLE PRODUCT GRADE • High End Computing Systems • Automated Test Equipment • High Density Power Supplies • Communications Systems IOUT = 80 A (NOM) K = 1/24 VTM48 E x 020 y 080A00 F = J-Lead T = Through hole T = -40 to 125°C M = -55 to 125°C For Storage and Operating Temperatures see Section 6.0 General Characteristics TYPICAL APPLICATION Regulator PR PC TM IL VC SG OS CD Voltage Transformer TM VC PC PRM Regulator +In +Out TM VTM Transformer +In +Out TM VIN -In -Out -In -Out L O A D (See Application Note AN:024) Factorized Power ArchitectureTM V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 1 of 18 VTM48 E x 020 y 080A00 1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. MIN MAX UNIT MIN MAX UNIT + IN to - IN . . . . . . . . . . . . . . . . . . . . . . . PC to - IN . . . . . . . . . . . . . . . . . . . . . . . . TM to -IN . . . . . . . . . . . . . . . . . . . . . . . . VC to - IN . . . . . . . . . . . . . . . . . . . . . . . . -1.0 -0.3 -0.3 -0.3 60 20 7 20 VDC VDC VDC VDC + IN / - IN to + OUT / - OUT (hipot) ........ + IN / - IN to + OUT / - OUT (working)... + OUT to - OUT....................................... -1.0 2250 60 4 VDC VDC VDC 2.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25ºC unless otherwise noted. ATTRIBUTE Input voltage range VIN slew rate VIN UV turn off SYMBOL VIN dVIN /dt VIN_UV Module latched shutdown, No external VC applied, IOUT = 80A VIN = 48 V VIN = 26 V to 55 V VIN = 48 V, TC = 25ºC VIN = 26 V to 55 V, TC = 25ºC VC enable, VIN = 48 V, COUT = 27000 µF, RLOAD = 24 mΩ K = VOUT / VIN, IOUT = 0 A VOUT = VIN • K - IOUT • ROUT, Section 11 TPEAK < 10 ms, IOUT_AVG ≤ 80 A IOUT_AVG ≤ 80 A VIN = 48 V, IOUT = 80 A VIN = 26 V to 55 V, IOUT = 80 A VIN = 48 V, IOUT = 40 A VIN = 48 V, TC = 100°C, IOUT = 80 A 16 A < IOUT < 80 A TC = -40°C, IOUT = 80 A TC = 25°C, IOUT = 80 A TC = 100°C, IOUT = 80 A 24 1.5 4.2 CONDITIONS / NOTES No external VC applied VC applied MIN 26 0 TYP MAX 55 55 1 26 8.7 9.5 5.7 8 UNIT VDC V/µs V No Load power dissipation PNL W Inrush current peak DC input current Transfer ratio Output voltage Output current (average) Output current (peak) Output power (average) Efficiency (ambient) Efficiency (hot) Efficiency (over load range) Output resistance (cold) Output resistance (ambient) Output resistance (hot) Switching frequency Output ripple frequency Output voltage ripple Output inductance (parasitic) Output capacitance (internal) Output capacitance (external) PROTECTION Overvoltage lockout Overvoltage lockout response time constant Output overcurrent trip Short circuit protection trip current Output overcurrent response time constant Short circuit protection response time Thermal shutdown setpoint Reverse inrush current protection IINRP IIN_DC K VOUT IOUT_AVG IOUT_PK POUT_AVG 10 1/24 20 4 A A V/V V A A W % 80 120 300 91.2 87.3 90.5 91.2 80 0.40 0.55 0.65 1.50 3.00 92.4 92.1 92.2 0.76 0.98 1.18 1.60 3.20 189 600 250 27000 1.0 1.2 1.5 1.70 3.40 295 ηAMB ηHOT η20% ROUT_COLD ROUT_AMB ROUT_HOT FSW FSW_RP VOUT_PP LOUT_PAR COUT_INT COUT_EXT % % mΩ mΩ mΩ MHz MHz mV pH µF µF COUT = 0 F, IOUT = 80 A, VIN = 48 V, 20 MHz BW, Section 12 Frequency up to 30 MHz, Simulated J-lead model Effective Value at 2 VOUT VTM Standalone Operation. VIN pre-applied, VC enable VIN_OVLO+ TOVLO IOCP ISCP TOCP TSCP TJ_OTP Module latched shutdown Effective internal RC filter 55.1 58.5 8 60 V µs 100 160 Effective internal RC filter (Integrative). From detection to cessation of switching (Instantaneous) 125 Reverse Inrush protection disabled for this product 120 4.3 1 130 160 A A ms µs 135 ºC V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 2 of 18 VTM48 E x 020 y 080A00 3.0 SIGNAL CHARACTERISTICS Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25°C unless otherwise noted. • Used to wake up powertrain circuit. • A minimum of 11.5 V must be applied indefinitely for VIN < 26 V to ensure normal operation. • VC slew rate must be within range for a succesful start. SIGNAL TYPE STATE ATTRIBUTE External VC voltage VTM CONTROL : VC • PRM VC can be used as valid wake-up signal source. • Internal Resistance used in “Adaptive Loop” compensation • VC voltage may be continuously applied SYMBOL VVC_EXT CONDITIONS / NOTES Required for start up, and operation below 26 V. See Section 7. VC = 11.5 V, VIN = 0 V VC = 11.5 V, VIN > 26 V VC = 16.5 V, VIN > 26 V Fault mode. VC > 11.5 V MIN 11.5 115 0 0 60 100 2 TYP MAX UNIT 16.5 150 mA V kΩ 900 ppm/°C V V/µs A µs µs µF V VC current draw Steady VC internal diode rating VC internal resistor VC internal resistor temperature coefficient VC start up pulse VC slew rate VC inrush current IVC DVC_INT RVC-INT TVC_COEFF VVC_SP dVC/dt IINR_VC ANALOG INPUT Tpeak 26 V or VC > 11.5 V. • PC pin cannot sink current and will not disable other modules • After successful start up and under no fault condition, PC can be used as during fault mode. a 5 V regulated voltage source with a 2 mA maximum current. Start Up SIGNAL TYPE STATE Steady ATTRIBUTE PC voltage PC source current PC resistance (internal) PC source current PC capacitance (internal) PC resistance (external) PC voltage PC voltage (disable) PC pull down current PC disable time PC fault response time SYMBOL VPC IPC_OP RPC_INT IPC_EN CPC_INT RPC_S VPC_EN VPC_DIS IPC_PD TPC_DIS_T TFR_PC Internal pull down resistor Section 7 60 2 5.1 From fault to PC = 2 V 5 100 2.5 CONDITIONS / NOTES MIN 4.7 50 50 TYP 5 150 100 MAX UNIT 5.3 2 400 300 1000 3 2 V mA kΩ µA pF kΩ V V mA µs µs ANALOG OUTPUT Start Up Enable DIGITAL INPUT / OUPUT Disable Transitional V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 3 of 18 VTM48 E x 020 y 080A00 TEMPERATURE MONITOR : TM • The TM pin monitors the internal temperature of the VTM controller IC • The TM pin has a room temperature setpoint of 3 V within an accuracy of ±5°C. and approximate gain of 10 mV/°C. • Can be used as a "Power Good" flag to verify that the VTM is operating. • Output drives Temperature Shutdown comparator SIGNAL TYPE STATE ATTRIBUTE TM voltage TM source current TM gain TM voltage ripple Disable DIGITAL OUTPUT (FAULT FLAG) Transitional TM voltage TM resistance (internal) TM capacitance (external) TM fault response time SYMBOL VTM_AMB ITM ATM VTM_PP VTM_DIS RTM_INT CTM_EXT TFR_TM CONDITIONS / NOTES TJ controller = 27°C MIN 2.95 TYP 3.00 10 CTM = 0 F, VIN = 48 V, IOUT = 80 A Internal pull down resistor From fault to TM = 1.5 V 25 120 0 40 10 200 50 50 MAX UNIT 3.05 100 V µA mV/°C mV V kΩ pF µs ANALOG OUTPUT Steady 4.0 TIMING DIAGRAM IOUT ISSP IOCP 1 23 b 6 7 4 5 d 8 VC VVC-EXT a VOVLO VIN NL ≥ 26 V c e f VOUT TM VTM-AMB PC 5V 3V g a: VC slew rate (dVC/dt) b: Minimum VC pulse rate c: TOVLO d: TOCP e: Output turn on delay (TON) f: PC disable time (TPC_DIS_T) g: VC to PC delay (TVC_PC) 1. Initiated VC pulse 2. Controller start 3. VIN ramp up 4. VIN = VOVLO 5. VIN ramp down no VC pulse 6. Overcurrent 7. Start up on short circuit 8. PC driven low Notes: – Timing and voltage is not to scale – Error pulse width is load dependent V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 4 of 18 VTM48 E x 020 y 080A00 5.0 APPLICATION CHARACTERISTICS The following values, typical of an application environment, are collected at TC = 25ºC unless otherwise noted. See associated figures for general trend data. ATTRIBUTE No load power dissipation Efficiency (ambient) Efficiency (hot) Output resistance (cold) Output resistance (ambient) Output resistance (hot) Output voltage ripple VOUT transient (positive) VOUT transient (negative) SYMBOL PNL ηAMB ηHOT ROUT_COLD ROUT_AMB ROUT_HOT VOUT_PP VOUT_TRAN+ VOUT_TRANCONDITIONS / NOTES VIN = 48 V, PC enabled VIN = 48 V, IOUT = 80 A VIN = 48 V, IOUT = 80 A, TC = 100ºC VIN = 48 V, IOUT = 80 A, TC = -40ºC VIN = 48 V, IOUT = 80 A VIN = 48 V, IOUT = 80 A, TC = 100ºC COUT = 0 F, IOUT = 80 A, VIN = 48 V, 20 MHz BW, Section 12 IOUT_STEP = 0 A TO 80A, VIN = 48 V, ISLEW = 19 A /us IOUT_STEP = 80 A to 0 A, VIN = 48 V ISLEW = 59 A /us TYP 4.4 92.1 91.7 0.8 1.1 1.4 279 30 110 UNIT W % % mΩ mΩ mΩ mV mV mV No Load Power Dissipation vs. Line No Load Power Dissipation (W) 11 9 7 5 3 1 26 29 32 35 38 41 43 46 49 52 55 Full Load Efficiency vs. Case Temperature 94 Full Load Efficiency (%) 92 90 88 86 -40 -20 0 20 40 60 80 100 Input Voltage (V) TCASE: -40°C 25°C 100°C Case Temperature (°C) VIN : 26 V 48 V 55 V Figure 1 – No load power dissipation vs. VIN Figure 2 – Full load efficiency vs. temperature Efficiency & Power Dissipation -40°C Case 96 92 88 45 96 Efficiency & Power Dissipation 25°C Case 28 Power Dissipation (W) Efficiency (%) 84 80 76 72 68 64 60 0 8 16 24 32 30 25 20 Efficiency (%) η 35 88 84 80 76 72 68 0 8 16 24 32 η 20 16 12 PD 15 10 5 0 PD 8 4 0 40 48 56 64 72 80 40 48 56 64 72 80 Load Current (A) VIN: 26 V 48 V 55 V 26 V 48 V 55 V VIN: 26 V Load Current (A) 48 V 55 V 26 V 48 V 55 V Figure 3 – Efficiency and power dissipation at –40°C Figure 4 – Efficiency and power dissipation at 25°C V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 5 of 18 Power Dissipation (W) 40 92 24 VTM48 E x 020 y 080A00 Efficiency & Power Dissipation 100°C Case 96 92 28 24 2.0 ROUT vs. TCASE at VIN = 48 V Power Dissipation (W) Efficiency (%) 84 80 76 72 68 0 8 26 V 16 24 48 V 32 40 55 V 48 56 26 V 64 72 48 V 80 16 12 Rout (mΩ) 88 η 20 1.5 1.0 PD 8 4 0 0.5 0.0 -40 -20 I OUT : 0 20 40A 40 80A 60 80 100 Load Current (A) VIN: 55 V Case Temperature (°C) Figure 5 – Efficiency and power dissipation at 100°C Figure 6 – ROUT vs. temperature Output Voltage Ripple vs. Load 300 275 140 120 Safe Operating Area Ripple (mV pk-pk) 250 225 200 175 150 125 100 75 50 0 8 16 24 32 40 48 56 64 72 80 Output Current (A) 10 ms Max 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 Continuous Load Current (A) VIN : 26 V 48 V 55 V Output Voltage (V) Figure 7 – VRIPPLE vs. IOUT ; No external COUT. Board mounted module, scope setting : 20 MHz analog BW Figure 8 – Safe operating area Figure 9 – Full load ripple, 100 µF CIN; No external COUT. Board mounted module, scope setting : 20 MHz analog BW Figure 10 –Start up from application of VIN; VC pre-applied COUT = 27000 µF Rev. 3.1 2/2011 Page 6 of 18 V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m VTM48 E x 020 y 080A00 Figure 11 – Start up from application of VC; VIN pre-applied COUT = 27000 µF Figure 12 – 0 A– 80 A transient response: CIN = 100 µF, no external COUT Figure 13 – 80 A – 0 A transient response: CIN = 100 µF, no external COUT V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 7 of 18 VTM48 E x 020 y 080A00 6.0 GENERAL CHARACTERISTICS Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40ºC < TJ < 125ºC (T-Grade); All Other specifications are at TJ = 25°C unless otherwise noted. ATTRIBUTE MECHANICAL Length Width Height Volume Weight Lead finish SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT L W H Vol W 32.25 / [1.270] 21.75 / [0.856] 6.48 / [0.255] No heat sink Nickel Palladium Gold 0.51 0.02 0.003 32.5 / [1.280] 22.0 / [0.866] 6.73 / [0.265] 4.81 / [0.294] 15.0/ [0.53 ] 32.75 / [1.289] 22.25 / [0.876] 6.98 / [0.275] mm/[in] mm/[in] mm/[in] cm3/[in3] g/[oz] µm 2.03 0.15 0.051 THERMAL VTM48EF020T080A00 (T-Grade) VTM48EF020M080A00 (M-Grade) VTM48ET020T080A00 (T-Grade) VTM48ET020M080A00 (M-Grade) Isothermal heat sink and isothermal internal PCB -40 -55 -40 -55 1 5 125 125 125 125 °C °C °C °C °C/W Ws/°C Operating temperature TJ Thermal resistance Thermal capacity ASSEMBLY Peak compressive force applied to case (Z-axis) Storage temperature φJC Supported by J-lead only VTM48EF020T080A00 (T-Grade) VTM48EF020M080A00 (M-Grade) VTM48ET020T080A00 (T-Grade) VTM48ET020M080A00 ( M-Grade) MSL 6, TOB = 4 hrs MSL 5 Human Body Model, "JEDEC JESD 22-A114-F" Charge Device Model, "JEDEC JESD 22-C101-D" -40 -65 -40 -65 TST 6 5.41 125 125 125 125 lbs lbs / in2 °C °C °C °C Moisture sensitivity level MSL ESDHBM 1000 VDC 400 ESD withstand ESDCDM SOLDERING Peak temperature during reflow Peak time above 245°C Peak heating rate during reflow Peak cooling rate post reflow SAFETY Working voltage (IN – OUT) Isolation voltage (hipot) Isolation capacitance Isolation resistance MSL 6, TOB = 4 hrs MSL 5 60 1.5 1.5 245 225 90 3 6 °C °C s °C/s °C/s VIN_OUT VHIPOT CIN_OUT RIN_OUT 60 Unpowered unit MIL-HDBK-217 Plus Parts Count; 25ºC Ground Benign, Stationary, Indoors / Computer Profile Telcordia Issue 2 - Method I Case 1; Ground Benign, Controlled cTUVus cURus CE Mark RoHS 6 of 6 2250 2500 10 3200 3800 VDC VDC pF MΩ MHrs MHrs 1.93 5.58 MTBF Agency approvals / standards V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 8 of 18 VTM48 E x 020 y 080A00 7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM The VTM Control (VC) pin is an input pin which powers the internal VCC circuitry when within the specified voltage range of 11.5 V to 16.5 V. This voltage is required for VTMTM current multiplier start up and must be applied as long as the input is below 26 V. In order to ensure a proper start, the slew rate of the applied voltage must be within the specified range. Some additional notes on the using the VC pin: • In most applications, the VTM module will be powered by an upstream PRMTM regulator which provides a 10 ms VC pulse during start up. In these applications the VC pins of the PRM regulator and VTM current multiplier should be tied together. • The VC voltage can be applied indefinitely allowing for continuous operation down to 0 VIN. • The fault response of the VTM module is latching. A positive edge on VC is required in order to restart the unit. If VC is continuously applied the PC pin may be toggled to restart the VTM module. Primary Control (PC) pin can be used to accomplish the following functions: • Delayed start: Upon the application of VC, the PC pin will source a constant 100 µA current to the internal RC network. Adding an external capacitor will allow further delay in reaching the 2.5 V threshold for module start. • Auxiliary voltage source: Once enabled in regular operational conditions (no fault), each VTM PC provides a regulated 5 V, 2 mA voltage source. • Output disable: PC pin can be actively pulled down in order to disable the module. Pull down impedance shall be lower than 400 Ω. • Fault detection flag: The PC 5 V voltage source is internally turned off as soon as a fault is detected. It is important to notice that PC doesn’t have current sink capability. Therefore, in an array, PC line will not be capable of disabling neighboring modules if a fault is detected. • Fault reset: PC may be toggled to restart the unit if VC is continuously applied. Temperature Monitor (TM) pin provides a voltage proportional to the absolute temperature of the converter control IC. It can be used to accomplish the following functions: • Monitor the control IC temperature: The temperature in Kelvin is equal to the voltage on the TM pin scaled by 100. (i.e. 3.0 V = 300 K = 27ºC). If a heat sink is applied, TM can be used to thermally protect the system. • Fault detection flag: The TM voltage source is internally turned off as soon as a fault is detected. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of TM signal. 8.0 START UP BEHAVIOR Depending on the sequencing of the VC with respect to the input voltage, the behavior during start up will vary as follows: • Normal operation (VC applied prior to VIN): In this case the controller is active prior to ramping the input. When the input voltage is applied, the VTM output voltage will track the input (See Figure 10). The inrush current is determined by the input voltage rate of rise and output capacitance. If the VC voltage is removed prior to the input reaching 26 V, the VTM may shut down. • Stand-alone operation (VC applied after VIN): In this case the VTM output will begin to rise upon the application of the VC voltage (See Figure 11). The Adaptive Soft Start Circuit (See Section 11) may vary the ouput rate of rise in order to limit the inrush current to its maximum level. When starting into high capacitance, or a short, the output current will be limited for a maximum of 120 µ/sec. After this period, the Adaptive Soft Start Circuit will time out and the VTM module may shut down. No restart will be attempted until VC is re-applied or PC is toggled. The maximum output capacitance is limited to 27000 µF in this mode of operation to ensure a sucessful start. 9.0 THERMAL CONSIDERATIONS V• I ChipTM products are multi-chip modules whose temperature distribution varies greatly for each part number as well as with the input / output conditions, thermal management and environmental conditions. Maintaining the top of the VTM48EF020T080A00 case to less than 100ºC will keep all junctions within the V• I Chip module below 125ºC for most applications. The percent of total heat dissipated through the top surface versus through the J-lead is entirely dependent on the particular mechanical and thermal environment. The heat dissipated through the top surface is typically 60%. The heat dissipated through the J-lead onto the PCB board surface is typically 40%. Use 100% top surface dissipation when designing for a conservative cooling solution. It is not recommended to use a V• I Chip module for an extended period of time at full load without proper heat sinking. V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 9 of 18 +V IN V DD Q3 Power Transformer 10.0 VTM48EF020T080A00 BLOCK DIAGRAM v i c o r p o w e r. c o m Q5 Enable Q1 Primary Stage & Resonant Tank +V OUT C OUT -V OUT Cr Lr Q2 V DD Q4 Synchronous Rectification Q6 Gate Drive Supply Primary Gate Drive 18 V 10.5 V Modulator Enable Secondary Gate Drive Adaptive Soft Start Differential Primary Current Sensing 1.5 K 5V 2 mA V IN Enable OVLO UVLO C IN Regulator Supply D VC_INT VC R VC_INT -V IN V DD PC Pull-Up & Source 100 A 2.5 V Over Current Protection Slow Current Limit Fast Current Limit Fault Logic V REF V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 Enable Overtemperature Protection Temperature Dependent Voltage Source 1K 150 K 2.5 V V REF 40 K 0.01 F PC TM 1000 pF VTM48 E x 020 y 080A00 Page 10 of 18 Rev. 3.1 2/2011 VTM48 E x 020 y 080A00 11.0 SINE AMPLITUDE CONVERTERTM POINT OF LOAD CONVERSION The Sine Amplitude Converter (SACTM) uses a high frequency resonant tank to move energy from input to output. (The resonant tank is formed by Cr and leakage inductance Lr in the power transformer windings as shown in the VTMTM module Block Diagram. See Section 10). The resonant LC tank, operated at high frequency, is amplitude modulated as a function of input voltage and output current. A small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionality and is key to achieving power density. The VTM48EF020T080A00 SAC can be simplified into the following model: 146 pH LIN == 5 nH L IN 0.6 nH OUT IIOUT R OUT ROUT 0.98 mΩ LOUT = 600 pH + RCIN RCIN 0.57 mΩ V IN VIN CIN CIN 3.2 µF Q IIQ V• I 1/24 • IOUT 0.1 Ω RCOUT RCOUT + 160 µΩ 250 µF V OUT VOUT 94 mA + – K + – 1/24 • VIN COUT COUT – Figure 14 – V•I ChipTM AC model – At no load: VOUT = VIN • K K represents the “turns ratio” of the SAC. Rearranging Eq (1): K= VOUT VIN (2) (1) interesting attributes. Assuming that ROUT = 0 Ω and IQ = 0 A, Eq. (3) now becomes Eq. (1) and is essentially load independent, resistor R is now placed in series with VIN as shown in Figure 15. R VIN Vin + – SACTM SAC K = 1/32 K = 1/32 Vout VOUT In the presence of load, VOUT is represented by: VOUT = VIN • K – IOUT • ROUT and IOUT is represented by: IOUT = IIN – IQ K (4) (3) Figure 15 – K = 1/32 Sine Amplitude Converter with series input resistor The relationship between VIN and VOUT becomes: VOUT = (VIN – IIN • R) • K Substituting the simplified version of Eq. (4) (IQ is assumed = 0 A) into Eq. (5) yields: VOUT = VIN • K – IOUT • R • K2 (6) (5) ROUT represents the impedance of the SAC, and is a function of the RDSON of the input and output MOSFETs and the winding resistance of the power transformer. IQ represents the quiescent current of the SAC control and gate drive circuitry. The use of DC voltage transformation provides additional V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 11 of 18 VTM48 E x 020 y 080A00 This is similar in form to Eq. (3), where ROUT is used to represent the characteristic impedance of the SACTM. However, in this case a real R on the input side of the SAC is effectively scaled by K2 with respect to the output. Assuming that R = 1 Ω, the effective R as seen from the secondary side is 0.98 mΩ, with K = 1/32 as shown in Figure 15. A similar exercise should be performed with the additon of a capacitor or shunt impedance at the input to the SAC. A switch in series with VIN is added to the circuit. This is depicted in Figure 16. Low impedance is a key requirement for powering a highcurrent, low voltage load efficiently. A switching regulation stage should have minimal impedance while simultaneously providing appropriate filtering for any switched current. The use of a SAC between the regulation stage and the point of load provides a dual benefit of scaling down series impedance leading back to the source and scaling up shunt capacitance or energy storage as a function of its K factor squared. However, the benefits are not useful if the series impedance of the SAC is too high. The impedance of the SAC must be low, i.e. well beyond the crossover frequency of the system. A solution for keeping the impedance of the SAC low involves switching at a high frequency. This enables small magnetic components because magnetizing currents remain low. Small magnetics mean small path lengths for turns. Use of low loss core material at high frequencies also reduces core losses. The two main terms of power loss in the VTMTM module are: - No load power dissipation (PNL): defined as the power used to power up the module with an enabled powertrain at no load. - Resistive loss (ROUT): refers to the power loss across the VTM modeled as pure resistive impedance. PDISSIPATED = PNL + PROUT Therefore, (7) POUT = PIN – PDISSIPATED = PIN – PNL – PROUT (11) (10) S VIN Vin + – C SACTM SAC K = 1/32 K = 1/32 VVout OUT Figure 16 – Sine Amplitude ConverterTM with input capacitor A change in VIN with the switch closed would result in a change in capacitor current according to the following equation: IC(t) = C dVIN dt Assume that with the capacitor charged to VIN, the switch is opened and the capacitor is discharged through the idealized SAC. In this case, IC = IOUT • K Substituting Eq. (1) and (8) into Eq. (7) reveals: IOUT = C K2 • The above relations can be combined to calculate the overall module efficiency: η= POUT = PIN – PNL – PROUT PIN PIN (12) (8) dVOUT dt = (9) VIN • IIN – PNL – (IOUT)2 • ROUT VIN • IIN The equation in terms of the output has yielded a K2 scaling factor for C, specified in the denominator of the equation. A K factor less than unity, results in an effectively larger capacitance on the output when expressed in terms of the input. With a K= 1/32 as shown in Figure 16, C=1 µF would appear as C=1024 µF when viewed from the output. = 1– ( PNL + (IOUT)2 • ROUT VIN • IIN ) V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 12 of 18 VTM48 E x 020 y 080A00 12.0 INPUT AND OUTPUT FILTER DESIGN A major advantage of a SACTM system versus a conventional PWM converter is that the former does not require large functional filters. The resonant LC tank, operated at extreme high frequency, is amplitude modulated as a function of input voltage and output current and efficiently transfers charge through the isolation transformer. A small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionality and is key to achieving high power density. This paradigm shift requires system design to carefully evaluate external filters in order to: 1.Guarantee low source impedance. To take full advantage of the VTMTM module dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. Input capacitance may be added to improve transient performance or compensate for high source impedance. 2.Further reduce input and/or output voltage ripple without sacrificing dynamic response. Given the wide bandwidth of the VTM module, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the VTM module multiplied by its K factor. 3.Protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures. The V•I ChipTM module input/output voltage ranges must not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it. 13.0 CAPACITIVE FILTERING CONSIDERATIONS FOR A SINE AMPLITUDE CONVERTERTM It is important to consider the impact of adding input and output capacitance to a Sine Amplitude Converter on the system as a whole. Both the capacitance value and the effective impedance of the capacitor must be considered. A Sine Amplitude Converter has a DC ROUT value which has already been discussed in section 11. The AC ROUT of the SAC contains several terms: • Resonant tank impedance • Input lead inductance and internal capacitance • Output lead inductance and internal capacitance The values of these terms are shown in the behavioral model in section 11. It is important to note on which side of the transformer these impedances appear and how they reflect across the transformer given the K factor. The overall AC impedance varies from model to model. For most models it is dominated by DC ROUT value from DC to beyond 500 KHz. The behavioral model in section 11 should be used to approximate the AC impedance of the specific model. Any capacitors placed at the output of the VTM module reflect back to the input of the module by the square of the K factor (Eq. 9) with the impedance of the module appearing in series. It is very important to keep this in mind when using a PRMTM regulator to power the VTM module. Most PRM modules have a limit on the maximum amount of capacitance that can be applied to the output. This capacitance includes both the PRM output capacitance and the VTM output capacitance reflected back to the input. In PRM remote sense applications, it is important to consider the reflected value of VTM output capacitance when designing and compensating the PRM control loop. Capacitance placed at the input of the VTM module appear to the load reflected by the K factor with the impedance of the VTM module in series. In step-down ratios, the effective capacitance is increased by the K factor. The effective ESR of the capacitor is decreased by the square of the K factor, but the impedance of the module appears in series. Still, in most step-down VTM modules an electrolytic capacitor placed at the input of the module will have a lower effective impedance compared to an electrolytic capacitor placed at the output. This is important to consider when placing capacitors at the output of the module. Even though the capacitor may be placed at the output, the majority of the AC current will be sourced from the lower impedance, which in most cases will be the module. This should be studied carefully in any system design using a module. In most cases, it should be clear that electrolytic output capacitors are not necessary to design a stable, well-bypassed system. V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 13 of 18 VTM48 E x 020 y 080A00 14.0 CURRENT SHARING The SACTM topology bases its performance on efficient transfer of energy through a transformer without the need of closed loop control. For this reason, the transfer characteristic can be approximated by an ideal transformer with some resistive drop and positive temperature coefficient. This type of characteristic is close to the impedance characteristic of a DC power distribution system, both in behavior (AC dynamic) and absolute value (DC dynamic). When connected in an array with the same K factor, the VTM module will inherently share the load current (typically 5%) with parallel units according to the equivalent impedance divider that the system implements from the power source to the point of load. Some general recommendations to achieve matched array impedances: • Dedicate common copper planes within the PCB to deliver and return the current to the modules. • Provide the PCB layout as symmetric as possible. • Apply same input / output filters (if present) to each unit. For further details see AN:016 Using BCM™ Bus Converters in High Power Arrays. 16.0 REVERSE OPERATION The VTM48EF020T080A00 is capable of reverse operation. If a voltage is present at the output which satisfies the condition VOUT > VIN • K at the time the VC voltage is applied, or after the unit has started, then energy will be transferred from secondary to primary. The input to output ratio will be maintained. The VTM48EF020T080A00 will continue to operate in reverse as long as the input and output are within the specified limits. The VTM48EF020T080A00 has not been qualified for continuous operation (>10 ms) in the reverse direction. VIN ZIN_EQ1 VTM1 RO_1 ZOUT_EQ1 VOUT ZIN_EQ2 + – VTM2 RO_2 ZOUT_EQ2 DC Load ZIN_EQn VTMn RO_n ZOUT_EQn Figure 17 – VTM TM current multiplier array 15.0 FUSE SELECTION In order to provide flexibility in configuring power systems V• I ChipTM products are not internally fused. Input line fusing of V• I Chip products is recommended at system level to provide thermal protection in case of catastrophic failure. The fuse shall be selected by closely matching system requirements with the following characteristics: • Current rating (usually greater than maximum current of VTM module) • Maximum voltage rating (usually greater than the maximum possible input voltage) • Ambient temperature • Nominal melting I2t Rev. 3.1 2/2011 Page 14 of 18 v i c o r p o w e r. c o m V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 VTM48 E x 020 y 080A00 17.1 J-LEAD PACKAGE MECHANICAL DRAWING Click here to view original mechanical drawings on the Vicor website. mm (inch) NOTES: mm 2. DIMENSIONS ARE inch . UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: 3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 4. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com 17.2 J-LEAD PACKAGE RECOMMENDED LAND PATTERN 3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] mm 2. DIMENSIONS ARE inch . UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: 4. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 15 of 18 VTM48 E x 020 y 080A00 17.3 THROUGH HOLE PACKAGE MECHANICAL DRAWING Click here to view original mechanical drawings on the Vicor website. mm (inch) NOTES: mm 2. DIMENSIONS ARE inch . UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: 3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 4. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com 17.4 THROUGH HOLE PACKAGE RECOMMENDED LAND PATTERN 3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] mm 2. DIMENSIONS ARE inch . UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: 4. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 16 of 18 VTM48 E x 020 y 080A00 17.5 RECOMMENDED HEAT SINK PUSH PIN LOCATION Click here to view original mechanical drawings on the Vicor website. (NO GROUNDING CLIPS) (WITH GROUNDING CLIPS) Notes: 1. Maintain 3.50 (0.138) Dia. keep-out zone free of copper, all PCB layers. 2. (A) minimum recommended pitch is 39.50 (1.555) this provides 7.00 (0.275) component edge-to-edge spacing, and 0.50 (0.020) clearance between Vicor heat sinks. (B) Minimum recommended pitch is 41.00 (1.614). This provides 8.50 (0.334) component edge-to-edge spacing, and 2.00 (0.079) clearance between Vicor heat sinks. 3. V•I ChipTM module land pattern shown for reference only, actual land pattern may differ. Dimensions from edges of land pattern to push–pin holes will be the same for all full size V•I Chip products. 4. RoHS compliant per CST–0001 latest revision. 5. Unless otherwise specified: Dimensions are mm (inches) tolerances are: x.x (x.xx) = ±0.3 (0.01) x.xx (x.xxx) = ±0.13 (0.005) 6. Plated through holes for grounding clips (33855) shown for reference, heat sink orientation and device pitch will dictate final grounding solution. 17.6 VTMTM MODULE PIN CONFIGURATION 4 A 3 2 1 A B C D E +Out B C D E +In -Out F G H H J J K K TM VC PC +Out L M N P L M N P R T -In -Out R T Signal Name +In –In TM VC PC +Out –Out Pin Designation A1-E1, A2-E2 L1-T1, L2-T2 H1, H2 J1, J2 K1, K2 A3-D3, A4-D4, J3-M3, J4-M4 E3-H3, E4-H4, N3-T3, N4-T4 Bottom View V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 17 of 18 VTM48 E x 020 y 080A00 Warranty Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 3.1 2/2011 Page 18 of 18