73120

SPICE Device Model Si1404DH Vishay Siliconix N-Channel 25-V (D-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73120 27-Aug-04 www.vishay.com 1 SPICE Device Model Si1404DH Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 1 11 0.28 0.33 2.3 0.76 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 µA VDS = 5 V, VGS = 4.5 V VGS = 4.5 V, ID = 1.57 A VGS = 2.5 V, ID = 1.39 A VDS = 15 V, ID = 0.75 A IS = 1.23 A, VGS = 0 V V A 0.28 0.36 1.5 0.85 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea b Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf VDD = 15 V, RL = 20 Ω ID ≅ 0.75 A, VGEN = 4.5 V, RG = 6 Ω VDS = 15 V, VGS = 4.5 V, ID = 1.57 A 1 0.31 0.49 12 15 19 21 1.3 0.31 0.49 11 18 17 11 ns nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 73120 27-Aug-04 SPICE Device Model Si1404DH Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 73120 27-Aug-04 www.vishay.com 3