AN701

AN701 Vishay Siliconix Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller INTRODUCTION Vishay Siliconix’s Si9100 monolithic switchmode PWM controller established the standard for low-power, highefficiency dc-to-dc converters. This versatile device integrates a number of useful features, including a power MOSFET, high-voltage start circuitry, and low power consumption. The Si9114A controller pushes the limits for high-frequency power conversion by further reducing delay times and adding additional features. As a result, dc-to-dc converters can be designed for frequencies up to 1 MHz with simple PWM topologies instead of the complex resonant ones. S reduce the size of energy storage components S increase reliability by using ceramic capacitors S produce an all-surface-mount assembly solution S lower system costs S simplify the implementation of a distributed power architecture. Traditionally, distributed power has been regarded as costly and impractical to implement due to the high cost of local power conversion and the perceived complexity of resonant power supplies. But these decision criteria are now being changed by the availability of small-outline control ICs, LITTLE FOOTr MOSFETs, ceramic capacitors, and new magnetic components. The Si9114A uses constant frequency current mode control. By increasing the conversion frequency, power supply designers will be able to: FB 5 COMP 6 Error Amplifier CURRENT SENSE 13 SYNC 10 ROSC 8 COSC 9 B2 Enable 2V + – – + 4.6 V 20 mA R Q S + – 1.25 V –VIN Substrate 20 mA OSC Out OSC 4 NI 3 VREF – + Ref Gen 12 DRIVER OUTPUT 11 –VIN VCC 7 SS VCC 14 Q 2 S R SHUTDOWN 1 +VIN – – + 0.2 V + 9.2 V – + Undervoltage Lockout Figure 1 Si9114A Block Diagram Document Number: 70575 16-Jan-01 www.vishay.com 1 AN701 Vishay Siliconix FUNCTIONAL DESCRIPTION OF THE SI9114A BID/CMOS PWM CONTROLLER The Si9114A controller is similar in configuration to the Si9110. It uses a traditional constant frequency current mode control, the most commonly used architecture. The duty cycle is limited to less than 50% to avoid problems with core reset. Current mode control is presently the de-facto standard for PWM control circuits. Indeed, it is the only candidate that should be considered, given its many advantages: S Cycle by cycle current limit protection S Simple loop compensation, eliminating effect of output inductor S Excellent fast transient response due to inner control loop S Automatic input voltage feed-forward compensation depletion mode MOSFET. The 9.2-V threshold has a hysteresis of 300 mV to prevent oscillations when the transition voltage is not clearly defined or when high-line supply impedance is encountered. For applications where the input dc voltage is not high, and the chip power consumption is not excessive, the feedback winding can be eliminated. In such cases, the pre-regulator circuit will behave just like a linear regulator with 9.2-V output and 10-kW series resistance. In this case, the parameters to be considered are the dropout voltage at lowest line condition and the power dissipation at highest voltage. The high-voltage depletion mode MOSFET contains an internal body diode, and in situations where the VCC is being powered from a laboratory supply, care must be taken to avoid loading the +VIN rail beyond the current rating of this device. Typically, the reverse characteristics of the device will generate a voltage of 3.4 V on Pin 1 with 10-kW load when powering VCC from a lab supply. In some applications it is necessary to inhibit the start of a converter until a high enough voltage is present on the supply bus. This is the case for the following reasons: S Circuitry fed from a high line impedance such as a telephone line will have difficulty starting, since the converter will behave like a negative impedance. As the dc voltage decreases, the input current increases because constant power is drawn. This causes severe oscillations, and can in some instances have a destructive effect on the converter. [4] S During start-up, the Si9114A will begin operation as soon as the UVLO threshold is reached. Since the converter is designed to operate over a much higher range—for example, from 36 to 72 V—then between 10- and 36-V input the output voltage will be out of regulation and undefined. In some cases, digital circuitry will not accept this mode of operation, and system faults will be encountered without a RESET watchdog circuit. To overcome these problems, a Zener diode of suitable value VZ can be placed in series with the +Vin pin, preventing start-up until VZ + 9.2 V is reached. To Internal Circuits VCC +VIN Transformer Winding PIN 1 HIGH VOLTAGE PRE REGULATOR All switchmode power supplies face a start-up problem caused by the large difference between dc bus voltage and the VCC power rail for supplying the control circuit. The traditional technique has been to keep the control circuit in “sleep mode,” while a small amount of energy is used to “top up” a large enough electrolytic capacitor to get the circuit started. When the circuit starts operating, a winding on the transformer is then used to power the control circuit. Disadvantages with this type of circuit include delayed start-up and large required capacitances for guaranteed operation over the full voltage range. The Si9114A overcomes these problems by using low power consumption, BiC/DMOS circuitry, and a unique high-voltage depletion mode MOSFET. (See 2) When power is first applied, the depletion transistor is on, and current flows from the input capacitor CIN into the VCC capacitor CVCC until VCC reaches 9.2 V. The converter transformer will then supply the VCC through a bias winding, which will raise VCC to a level higher than 9.2 V. Ideally this will be between 11 and 13 V, thus turning off the high-voltage 300 mV – CIN + 0.2 V – + UVLO 9.2 V –VIN CVCC Figure 2 Start Circuit www.vishay.com Document Number: 70575 16-Jan-01 2 AN701 Vishay Siliconix VCC +OP Vout SHUTDOWN S Q R 6 5 4 UV-Low Si9114A NC 2 3 TL431 1 20 mA –OP Figure 3 Shutdown PIN 2: SHUTDOWN The shutdown pin is configured to allow fast latched termination of the output pulse. The delay from shutdown to output is typically 300 ns. This delay is short enough to allow this pin to be used for over-voltage applications where fast orderly shutdown is desirable: for example, when control of the feedback loop is lost. Using an opto-coupler and a TL431, interface is easy. (See 3) Once latched, the shutdown can only be reset from the UVLO circuit by re-cycling the power. In the event of an over-voltage, the latch can be reset by momentarily pulling the VCC to a value lower than the UVLO threshold. This approach will generally be acceptable, since the feedback winding will not be supplying power, and the only power maintaining the latch will be supplied by the depletion start transistor. Note, however, that this action will still be subject to the power dissipation limits of the Si9114A package and should ideally be applied as a short fast pulse. An internal 20-mA current source pull-up on SHUTDOWN pin is provided. However, if the Si9114A is used in a potentially noisy environment, a 10-kW pull-up is recommended from SHUTDOWN to VCC to prevent fault triggering, and to prevent a start-up problem when a fast slew rate power supply (dv/dt > 100 V/ms) is used for +VIN (pin 1). Soft Star t FBK NINV 1.5 kW + – Comp PIN 3: REFERENCE The reference voltage is a fully buffered band gap type which can source 5 mA over the specified voltage tolerance range. The reference should be well de-coupled to prevent instability and jitter. A ceramic 100 nF or small tantalum is recommended, depending on the de-coupling present on the supply pins. Document Number: 70575 16-Jan-01 Figure 4 Operational Amplifier PINS 4, 5 AND 6: ERROR AMPLIFIER The error amplifier consists of a PMOS input folded cascade gain stage followed by a class AB unity gain amplifier. www.vishay.com 3 AN701 Vishay Siliconix Typical open loop voltage gain is 77 dB, and unity gain bandwidth is typically 2.7 MHz. The soft-start circuit (see Pin 7 description) forces the output to within 0.7 V above ground, and additional clamp diodes limit the positive output excursion to within 2xVBE above VREF . Operation at high frequency allows high closed loop bandwidths and permits excellent transient response to both input and output changes. Under normal operation, a small 100 pF bypass capacitor is recommended from NINV to Comp to increase high-frequency noise rejection. This should be calculated, however, in conjunction with the loop dynamics. oscillations may occur. These can be prevented with the use of long soft-start times. The soft-start pin can also be used as a non-latching shutdown pin by connecting it to –VIN. This approach allows a shutdown with soft re-start. PINS 8 AND 9 - OSCILLATOR The oscillator circuit uses external timing components RT and CT. An internal divide-by-two prevents pulses with greater than 50% duty cycle, so that core saturation can be avoided. When the RT terminal is connected to VCC, comparator C2 disconnects the oscillator output from the SYNC terminal using SW1, and allows an external oscillator circuit to take control of the current mode comparator circuit. The current programmed by RT defines the charging current of CT and the on and off times with the following design equations: 1.025 x RT x CT 8 where Rql = 25 W (2) (1) PIN 7: SOFT START The soft-start circuit is designed to help dc-to-dc converters start in an orderly manner and reduce component stress. The output of the error amplifier is clamped by a PNP transistor. The external capacitor CSS is supplied by a 20-mA current source and will charge linearly to 4.6 V. In the event of an under-voltage lockout (or during start-up), this capacitor is held low. tON + tOFF + 5 x Rql x CT 1 1 fOSC + 2 x t ) tOFF ON Feedback Error Amp (3) VREF Actual values taken from a prototype board have been plotted (Figure 6), and are a close match (except for 47 pF, where stray parasitics have more significant effect). Comparator 4.6 V 20 mA 1000 47 pF 100 pF 150 pF 200 pF f OUT (kHz) CSS 100 UV-low Figure 5 Soft-Start Note: These curves were measured in a board with 3.5 pF of external parasitic capacitance. Soft-start is a very important feature and has many beneficial effects, especially in applications connecting to telecom lines where source impedances are high. In such cases, there is an initial start-up current caused by the input capacitor, followed by a secondary peak caused by the converter running at maximum duty cycle while trying to reach regulation. Where large output capacitances and peak loads are encountered, www.vishay.com 10 10 100 ROSC (kW) 1000 Figure 6 Oscillator Frequency Selection 4 Document Number: 70575 16-Jan-01 AN701 Vishay Siliconix I1 C1 VREF Q2 C2 B1 B2 U1 D Q SW1 Q I2 B3 SYNC CLK RT CT Q1 Figure 7 Oscillator IC1 1 2 3 4 5 6 7 +VIN SHD VREF NI FB COMP SS VCC Sense Out –VIN SYNC COSC ROSC 14 13 12 11 10 9 8 Rt Ct 1 2 3 4 5 6 7 IC2 +VIN SHD VREF NI FB COMP SS VCC Sense Out –VIN SYNC COSC ROSC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 IC3 +VIN SHD VREF NI FB COMP SS VCC Sense Out –VIN SYNC COSC ROSC 14 13 12 11 10 9 8 Si9114A Si9114A Si9114A Figure 8 Oscillator Synchronization VCC R1 120 k D1 SW1 RT 68 k CVCC 1 mF Rt Ct CT –VIN The current in RT is set by V = IR where V = 4 V and R = RT. Using a diode, and some type of switch, the frequency can be easily changed: when SW1 is closed, D1 is reverse biased, and has no effect on RT. When SW1 is open, current flows through R1 and D1 into RT and removes some of the current supplied by the internal emitter follower. PIN 10 SYNCHRONIZATION SW1 Closed = Frequency High SW1 Open = Frequency Low Figure 9 Frequency Shifting Using Rt Current Change In certain circumstances, such as current limiting, it may be desirable to change the frequency of the converter for a period of time to overcome current tails (see Figure 16 for further explanation). With the Si9114A, this is easily done by adding or subtracting some current into the RT terminal: S The charging current in CT is set by 8 RT. S The voltage at the RT terminal is 4 V, as supplied by an internal emitter follower from the reference. The frequency can be changed easily by supplying some of the current into RT from the VCC rail, thus “starving ” the internal current source, and slowing the frequency down. Document Number: 70575 16-Jan-01 The SYNC input allows operation from a master clock as the connection is made after the divide-by-two. As a result, synchronization in both frequency and phase is possible. This unique feature is important to systems designers who use multiple converters, where noise caused by an unsynchronized “beating” effect is present and causes difficult EMI/EMC problems. If an external clock is used, duty cycles of >50% are possible due to the position of the SYNC pin , after the divide-by-two. Where >50% conduction is used, core reset must be allowed, in order to prevent core saturation. Synchronization is in master/slave mode, with one device (the “master”) setting the switching frequency and others (the “slaves”) with disabled oscillators locked to it. Alternatively, all devices can be clocked using a master oscillator. During slave mode, the unused CT pin should be connected to ground, and the RT to VCC. www.vishay.com 5 AN701 Vishay Siliconix PIN 11 & PIN 14 -VIN & VDD These pins are used for powering the Si9114A and should consequently be well de-coupled. In selecting the right de-coupling, the MOSFET gate drive requirements should be considered, as the de-coupling capacitor will also have to supply the required peak current. Generally speaking, the best combination would be a 1- to 10-mF electrolytic for bulk energy and a 100-nF ceramic for high-frequency bypass. The VCC rail should be carefully observed at the switch on and off occurrences using ac de-coupling, and the peak voltage spikes should be measured. These should be less than 200 mV. Excessive noise on the VCC will appear on other pins and may cause instability or jitter on the control waveforms. considered. In practice, most manufacturers are unable to publish this data for all voltages, so designers should use the curve nearest to the actual voltage applied. The Si9420DY LITTLE FOOT MOSFET is designed specifically for converters in the 5- to 25-W power range. It has a 200-V VDS rating with 1-W rDS(on). Using the Gate charge curve, for a gate drive of 12 V from the Si9114A, the total gate charge for 100-V VDS will be 10 nC. From Q = i x t, it is easy to deduce that with 400 mA gate drive, a time of 50 ns will be obtained—which is more than adequate for this size MOSFET. To supply 400 mA, the gate drive circuit resistor will need to be 12 V/400 mA = 30 W (Figure 11). PIN 13 PIN 12 OUTPUT DRIVER CURRENT SENSE The output driver uses complementary n- and p-channel output stages, with break-before-make capability, preventing shoot-through conduction. The output is typically capable of sourcing 400 mA and sinking 700 mA. When driving power MOSFETs, remember that the relevant parameter for sizing the drive requirements is the total gate charge for the applied voltage, not the commonly used input capacitance, CISS. When driving a MOSFET in common source mode, the Miller effect will significantly affect the drive waveform applied to the gate: in particular, when the driving source impedance is high enough (Figure 10). As the voltage is applied to the gate, the previously charged Cgd will need to discharge, and will thus oppose the application of any voltage to Vgs. Many designers commonly overestimate the drive requirements of the MOSFET and cause excessive noise in the converter by overdriving the MOSFET. To prevent this, designs typically require snubbers or other additional noise attenuation devices. The voltage that will be applied to the drain just prior to driving of the gate will need to be Drain The current sense comparator performs the current mode control function by comparing the output of the error amplifier (VC) with the current in the output inductor. It is impractical to measure the output inductor current, but the rising slope of the current can supply all the necessary information if sampled in the MOSFET as a scaled equivalent. Certain precautions are necessary, however, due to data distortion, noise, and the rarity of ideal operating conditions. Sensed current waveforms often have leading-edge spikes or noise caused by reverse recovery of rectifiers, equivalent capacitive loading on the secondary, and inductive circuit effects. Inductive sense resistors must not be used, as they cause large damaging spikes and distort the sensed waveforms. These spikes can confuse the PWM comparator into believing that an overload condition is present. In addition, the Si9114A uses a single pin (–Vin) for all the return current requirements, including the output driver. As a result, the current pulse from the gate charge transfer into the MOSFET will appear on the sense pin and be filtered out. 20 VDS = 100 V Gate-to-Source Voltage (V) 16 Cgd Rgate Drive CDS 12 8 Cgs 4 0 Source 0 4 8 Total Gate Charge (Qg) 12 16 Figure 10 www.vishay.com Figure 11 Si9420DY Gate Charge Document Number: 70575 16-Jan-01 6 AN701 Vishay Siliconix L VOUT iL OSC 1 VC 2 3 iL iDC ID VC RSENSE ID Figure 12. Constant Frequency Current Mode Control Waveform A has an ideal textbook appearance, but is in fact rarely encountered. Waveforms B and C are typical yet close to the threshold limit, and thus could lead to instability. The addition of a simple RC network on the sensed waveform suppresses this leading-edge spike. The low pass filter should be selected so that only the leading-edge spike is suppressed and the overall waveform is not distorted. The waveform must contain a clean rising slope for the error amplifier to intersect. If the RC time constant is too long, then the waveform will be distorted and lead to falling-edge jitter on the turn-off edge. Slope compensation can also be used to eliminate noise or jitter. A sample of the oscillator voltage is superimposed on the error amplifier to produce a clean crossing of the thresholds and to avoid any hunting. The Si9114A has built-in leading-edge blanking/ suppression to eliminate some of the effects of these spikes. The two comparators used to operate the circuit have different delay times as follows: S The current mode comparator needs more noise immunity, and therefore has a deliberately slower delay time to block out noise and spikes which are present on the leading edge. Typical delay times should be around 100 ns. S The peak current limiting comparator has the fastest response time, since it is used only to protect the circuit in the event of an overload. The delay times for this comparator should be around 70 ns. HIGH FREQUENCY DESIGN REQUIREMENTS When designing converters for high switching frequency, a certain discipline is required to determine the right choice of components. This process should be an iterative choice and the board layout should be properly planned before CAD layout is undertaken. A B C Figure 13 Current Waveforms Document Number: 70575 16-Jan-01 Figure 14 Current Sense Filtering Network www.vishay.com 7 AN701 Vishay Siliconix + Tx1 Volts Si9114ADY 1 2 3 4 5 6 7 +Vin Vref NI FB COMP SS VCC Output –Vin SYNC COSC ROSC 14 13 12 11 10 9 8 Cfilt Rsense Amps 100% 105% 115% Document Number: 70575 16-Jan-01 Rfilt Current Tail Q1 SHUTDOWN Sense Cin – Cref Css Figure 15 Figure 16 LAYOUT CONSIDERATIONS The main current loop flows from the input capacitor—through the transformer, MOSFET, and sense resistor—and returns to the capacitor. This current will have high rates of change and associated fast voltage and current edges. It is essential to avoid the injection of noise into the other circuitry. To prevent this result, a “fishbone” type arrangement is recommended (Figure 15). Designers are encouraged to separate different grounds with “imaginary” dummy resistors. These can be removed at a later stage. Main current loops must be designed to be as short as possible: from CIN to the transformer, through the MOSFET and Sense resistor, and back into CIN. It is obvious that signals switching 50 V or 1 A in 25 ns should not be mixed with signals that are controlling a closed-loop, high-gain feedback system which is capable of regulating the output voltage to less than 1 mV. be 70 ns/2 ms = 3.5%. This minimum should be considered when the short circuit current is determined. Designers should note that a shunt placed across the output of the converter is probably not a realistic load in the event of a failure, and the real circuit impedance will probably be substantially lower. In such circumstances, it may be necessary to shift the frequency of the converter to a lower value during overload. Frequency shifting can be accomplished by altering the steady state values of the oscillator programming components (see oscillator section, Figure 8). SHORT CIRCUIT BEHAVIOR Short circuit behavior is different for both common topologies, and must be paid special attention. S In flyback converters, all windings appear in “parallel” with each other. When one winding is shorted, all other flyback windings are also shorted though it. In multiple output converters, therefore, any single winding without a separate secondary current-limiting protection will “drag down” all the other windings. As a result, if a bias winding is used to power the control circuit, it will stop delivering power. When this occurs, the Si9114A depletion device will turn on and regulate the supply rail to 9.2 V, as in its normal starting mode. In this event, designers should calculate the worst-case power dissipation caused by the voltage drop across the depletion transistor at the highest applied voltage across it and with the current flowing through it. S In forward converters, traditionally the bias winding is also taken in forward conduction mode, but without any series inductance. In the event of a short circuit, the pulse width is reduced to minimum, but it is sufficient to supply enough power to the control circuit. This is an advantage, and avoids the problems encountered with flyback converters. Power may also be taken in flyback mode, however, when the duty cycle is low. There will be very little flyback voltage present, since the applied volt/microseconds is low and the core need not, therefore, fly back very far to reset. CHOOSING THE SWITCHING FREQUENCY When selecting the switching frequency, it is usually best to choose the lowest possible frequency that the design solution will accept. In PWM control topologies, the maximum switching frequency will be strongly governed by short circuit behavior. When a short circuit is applied to the output, the control circuit is required to reduce the duty cycle to the smallest possible value to maintain constant current operation (Figure 16). Ideally, the converter should deliver 105% of the output current within regulation and no more than 115% under short circuit. At 500 kHz, the period of conversion is 2 ms and the maximum on time is 1 ms. High minimum duty ratios will result in current tails and require rectifier oversizing to avoid destructive currents under overload conditions. The Si9114A has a sync-to-output delay of less than 70 ns, so the minimum duty cycle for operation at 500 kHz would www.vishay.com 8 AN701 Vishay Siliconix CHOOSING THE TOPOLOGY The choice of topology is usually based on the designer’s previous experience. The two best candidates for the Si9114A are the forward and flyback types, although other types, such as Cuk, are also possible. In general, forward converters are best for higher-power applications, and flyback converters are best for lower-power applications. Both topologies have their merits, and the designer will have to select the one most suited to his or her own application. See appendices A and B for brief descriptions of topologies and magnetic design equations. the Philips 3F3 and 3F4, designed for operation up to 500 kHz and 2 MHz respectively. Many different geometries and good supporting data are now available. Appropriate choices for low-profile and surface-mount capability include devices in the EFD series, which have been extended down to 10 mm. It is better to choose core geometries with shallow and wide bobbins, since these permit good coupling from winding to winding when using high frequencies. CHOOSING CERAMIC CAPACITORS High-frequency operation allows the use of very low-value capacitances not generally associated with switchmode power supply output stages. As substantially lower energy storage is required, multilayer ceramic capacitors can be used, and suppliers have made good advances in quality and manufacturing to supply low-cost, high-performance designs. In the sub-25-mF area, a number of good dielectric devices are now available, such as X7R, Z5U, and Y5T. From manufacturers’ data sheets, the following observations were made: S Z5U has the lowest cost, highest unit capacity, and worst dynamic variations S X7R has the highest cost, lowest unit capacity, and best dynamic stability S Y5T has an average of each of the above. The recently introduced Marcon TCCR series uses the Y5T dielectric, which offers good all-around volumetric, cost, and high-frequency impedance performance, and is available in a surface-mount package with values such as 10 mF at 25 V and 3.3 mF at 100 V. For input and output energy storage, two of each of these devices were selected with the following considerations: S Realistic market price. S Voltage variation with applied dc voltage and temperature. Most ceramic capacitors suffer from a drop of capacitance with applied voltage and with temperature. The device needs to be selected so that at the extremes of operation the minimum energy storage is present. S Equivalent Series Resistance (ESR). ESR will determine the output ripple voltage, and the heating of the device. This should be selected on the basis of the value of output choke, insofar as its design sets the ripple current present in the output capacitor. The following data was obtained from commercially obtained samples: At 70oC, the 10-mF device has dropped to 75% of its nominal value. With 5 V applied, the same device has retained 110% of its nominal value. Care should be taken in selecting these devices to consider worst case requirements and minimum/ maximum operating conditions. www.vishay.com SELECTING THE SEMICONDUCTORS For power switching, the recommended device is the Si9420DY. The Si9420DY is a 200-V, 1-W MOSFET housed in an industry-standard SO-8 package. Since the die is mounted on a copper header, cooling can be accomplished using the PCB area directly below the Drain pins. The combined performance of the Si9420DY’s features makes it the best low-profile device available on the market. It is suitable for designing power supplies ranging from 10 to 25 W. Other such single and dual LITTLE FOOT devices are available in both nand p-channel versions with voltages starting from 12 V. Rectification for low-voltage outputs (< 5 V) is accomplished using Schottky diodes. In this case, the rectifier selected exhibited forward voltage drops of 0.4 V at 4 A. A 5-V output will require a rectifier with a 40-V reverse voltage rating. Where lower voltages, such as 3 V, are required, devices with lower reverse blocking should be used, since these will have lower forward voltage drops. Designers should avoid using an oversized Schottky diode, since all such devices have parasitic capacitances that need to be charged and discharged to the applied voltages. Driving and commutating oversize devices will not necessarily yield better efficiency, especially at higher frequencies. Rectification for voltages above 12 V is generally accomplished using fast or ultra-fast rectifiers. Look for devices that have recovery times below 50 ns. An excellent example is Telefunken Semiconductors’ BYG22B rated for 100 V and 2 A with 25 ns recovery, and Forward voltage of 0.7 V for 0.5 A current. This device is available in a DO-214 surface-mount package. Opto-isolators are now available in SO-8 packages with 3000 Vrms isolation rating. These are by far the least expensive and simplest isolated feedback devices now available. Their reliability, once considered questionable, has been greatly improved, and manufacturers now have quality data demonstrating their suitability under the correct operating conditions. A typical device would be the Telefunken Semiconductors’ TCMT1020. CHOOSING FERRITE MATERIALS Ferrites suitable for operation at high frequencies have recently been introduced to the market. Two such offerings are Document Number: 70575 16-Jan-01 9 AN701 Vishay Siliconix 11 12 10 Capacitance ( m F) Capacitance ( m F) 11 9 10 8 9 7 25 35 45 55 65 75 8 0 1 2 3 4 5 6 7 8 9 10 11 Temperature (_C) Voltage (V) Figure 17. Marcon 10 mF 25 V, Capacitance Versus Temperature Figure 18. Marcon 10 mF 25 V, Capacitance Change with Voltage DESIGN EXAMPLE: A 15 W, 500 KHZ, 48 V/5 V DC TO DC CONVERTER Resonant Reset Forward Converter Most forward converters are designed using a clamp circuit. While at low frequencies this technique may be acceptable, at high frequencies it becomes unnecessary: the parasitic elements of the circuit will reset the transformer flux automatically, provided a few precautions are taken. It has been shown that [1] the resonant reset concept is dominated by the parasitic capacitance of the MOSFET and the magnetizing inductance of the transformer. Yet the capacitance of the output diode should also be considered. The correct equivalent circuit of the converter the approximates to Figure 19. During the off time, D2 is conducting and CD1 appears connected across the primary of the transformer, in parallel with LMAG. The leakage inductance has a small and insignificant effect on the waveform—as the primary current has ceased flowing—and the only remaining current is the current that is charging COUT . CD1 Lout N=1 Lmag Cin CAP Q1 Cout Vds D1 D2 Cout at a frequency determined by the parasitic elements. The reset period needs to be short enough to allow full reset of the core, before the next switching interval occurs. This will be governed by the selection of the MOSFET and the Schottky diode. Component Selection The following information is supplied in order to help designer select correct components for use with the Si9114A. Vishay Siliconix does not necessarily recommend or approve these components for specific applications. Designers should contact manufacturers directly to obtain correct and current data sheets. Capacitor Selection As stated previously, ceramic capacitors are a good choice when operating at high frequency, due to the extremely low ESR, and high reliability, and long operating lifetimes. In the design example, the required size of capacitors was defined as follows: Input capacitor: A 15-W output converter with 85% efficiency will require 15/0@85 = 17.65 W of input power. Assuming that operation at nominal conditions is 48 V, with duty cycle of δ =0.376 (measured), the switching current will be governed by the size of the output inductor (Figure 20). lA Figure 19 Resonant Reset Forward Converter lDC In effect, the magnetizing inductance of the transformer forms a parallel tuned circuit across the transformer and resonates www.vishay.com Figure 20 Document Number: 70575 16-Jan-01 10 AN701 Vishay Siliconix The average input current will be determined by: Pin 17.65 IDC + V + 48 + 0.358 A in Pin 17.65 IA + V x d + 48 x 0.376 + 0.98 A in From this equation the RMS value can also be calculated to be approximately 0.475 A. The Marcon TCCR70E2A335 3.3-mF, 100-Vdc capacitor has an ESR rating of 20 mΩ at 500 kHz. This type will therefore dissipate P = 0.4752 x 0.020 = 4.5 mW due to the switching current. The ripple produced across this device will be governed by the discharging current of the capacitor less the input dc voltage in accordance with: Q=ixt=CxV NVripple + NVripple + IC x t C where t + tsw x d and I C + IA–I DC order to guarantee the ESR over temperature or age, it might have been necessary to use a radial 1000-mF, 6.3-V Aluminum Electrolytic in a 10x16 mm case (1257 mm2) to get an ESR value below 100 mW. It would also be necessary to check the ESR with frequency at 500 kHz, as this data is seldom offered for electrolytics. By comparison, the Marcon TCCR70E1E106 10-mF, 25-Vdc is available in 7.5 x 6.3 x 2.75 (130 mm2) and has an ESR of less than 15 mW at 500 kHz. This will be ideal for low output ripple an noise. Recently introduced organic semiconductor electrolytics offer substantial improvements and could also be considered. In this example, it was decided to use 2 x 10-mF capacitors in order to obtain low output ripple. OUTPUT INDUCTOR DESIGN The output inductor limits the rate at which the current flows into the output capacitor when the voltage is applied from the primary through the transformer (Figure 21). Lout Ein Eout iL Cout 0.612 A x 2 ms x 0.376 + 0.14 V 3.3 mF 140 mV of ripple is probably acceptable as a first stage of filtering. If lower ripple is required at the input, then a two stage filter will yield better results. Output capacitor: DIout Cout + 8fDV whereDIout + 0.1 x I out out DVout f Cout = maximum output ripple voltage = operating frequency Figure 21 From simple circuit theory, the voltage applied across an inductor is: di VL + L dt where VL + Ein–Eout and di + DI L then L + Ein–E out xDt DIL 0.3 A + 8 x 500 kHz x 50 mV + 1.5 mF The required ESR for obtaining 50 mV of ripple would be defined by: ESRmax + DI out DVout In forward converters, at maximum duty cycle, Ein = 2xEout, and: 1 toff + 2 x F SW In this case, substituting gives: toff + 1mS and L + Eout x t off DI L 50 mV ESRmax + 0.3 A + 167 mW In practice, it is impossible to precisely match the value of a capacitor with the required ESR, and the values of the capacitors must often be selected to cover all operating conditions including voltage and temperature. The above equations and calculations are meant to help the designer select the approximate size of the components required, with the final selection based on practical values that meet the minimum required. In designs operating below 500 kHz, the choice of the capacitor is dictated by the ESR, and the best high-frequency electrolytics often require large-size and micro-farad values to meet these requirements. When operating at 500 kHz, the choice becomes more based on the practical value closest to the size and voltage rating required. For example, with electrolytics, in Document Number: 70575 16-Jan-01 Therefore L+ 5 V x 1 mS + 16.7 mH 0.3 A In practice, an inductor between 5 and 10 mH would be an acceptable choice, allowing for manufacturing tolerances and variations. The core selected is the EF12.6, which is identical to the core selected for the transformer design. The EF12.6 is a cheap, low-profile design available from many suppliers in all parts of the world. A surface-mounted version of this bobbin was selected for a design that could be entirely machine wound and terminated. This implies that larger wire sizes are not possible, due to automated winding restrictions. www.vishay.com 11 AN701 Vishay Siliconix L1 EF12.6 9.7 mH D5SC4M + D1 35 T C2 3.3 mF 100 V R1, 1 W – – R2, 1 W C5 2.2 mF 25 V D3 C8 22 pF R7 390 k TCMT1020 6 5 2 4 NC SHUTDOWN C3 220 pF 3 R11 1 kW C12 2.2 nF 1 kW R12 1 kW IC2 1 47 W IC1 Si9420DY 11 T 11 T D5SC4M D2 C10 10 mF 25 V 5V 4A C11 10 mF 25 V TX1 PL-25 + 36–72 V DC C1 3.3 mF 100 V R3 220 W R4 10 W Si9114A 14 13 12 11 10 9 8 R5 68 kW VCC SENSE OUT –VIN SYNC COSC ROSC +VIN SHD VREF NI FB COMP SS C7 100 nF 1 2 3 4 5 6 7 1 kW C6 100 nF R6 IC4 TL431 SYNC C4 100 pF R10 1 kW D3, D4 LS4148 Figure 22 DC-to-DC Converter Block Diagram Since this choke must carry the full output current, the minimum number of turns required on this core is given by: Lchoke x IChoke Nmin + B max x A min The result yields a choke having a dc resistance of 22 mW and therefore a dc copper loss of P = I2RDC = 9 x 0.022 = 200 mW with 3 A dc. Using a core set with an AL value of 45, a transformer of L = Nmin2 x AL = 122 x 45 x 10-9 = 6.48mH was calculated. Measured value was 9.73 mH: slightly higher, but acceptable. where Bmax is the maximum flux density used, and Amin is the minimum core area. In this case Bmax = 200 mT and Amin = 13 mm2 . Substituting in this equation yields: 8 mH x 3 A 200 mT x 13 mm2 TRANSFORMER DESIGN See appendix A for a design using these specifications. Nmin + + 9.2 T PERFORMANCE RESULTS The switching waveforms in Figure 23 show that the resonant reset is limiting the peak voltage to 120 V, well below the maximum rating of 200 V. Note the leading edge spike caused mainly by the peak gate current. Document Number: 70575 16-Jan-01 In this case it was decided to wind 3 layers of 12 turns of 0.315 mm in one layer each across the bobbin. This allowed the best fill factor of the bobbin, maximizing copper area. www.vishay.com 12 AN701 Vishay Siliconix ➀ ➁ ➂ ➀ ➁ ➀ VDS of MOSFET 50 V/div ➁ Output ripple 10 mV/div ➀ VDS of MOSFET 50 V/div ➁ Voltage across sense resistor 1 V/div ➂ Voltage across gate 5 V/div Figure 23 Time Base 500 ns/div. Figure 24 Time Base 500 ns/div. ➀ ➀ ➀ Output transient response for 1.5 to 3 A. ➀ Output transient response for 1.5 to 3 A. Figure 25 Time Base 200 ms/div. Figure 26 Time Base 5 ms/div. 100 90 Efficiency (%) In Figure 24, the low output ripple (