SI3586DV

SPICE Device Model Si3586DV Vishay Siliconix N- and P-Channel 20-V (D-S) MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72435 S-50836Rev. B, 16-May-05 www.vishay.com 1 SPICE Device Model Si3586DV Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA VDS = VGS, ID = −250 µA VDS ≥ 5 V, VGS = 4.5 V VDS ≤ −5 V, VGS = −4.5 V VGS = 4.5 V, ID = 3.4 A VGS = −4.5 V, ID = −2.5 A Drain-Source On-State Resistancea rDS(on) VGS = 2.5 V, ID = 3.2 A VGS = −2.5 V, ID = −2 A VGS = −1.8 V, ID = −1 A Forward Transconductancea gfs VDS = 5 V, ID = 3.4 A VDS = −5 V, ID = −2.5 A IS = 1.05 A, VGS = 0 V IS = −1.05 A, VGS = 0 V N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 0.70 0.78 111 47 0.048 0.088 0.056 0.120 0.165 12 6.4 0.80 −0.78 0.047 0.086 0.054 0.116 0.170 13 6 0.80 −0.80 S Ω V Symbol Test Condition Simulated Data Measured Data Unit On-State Drain Currenta ID(on) A Diode Forward Voltagea VSD V Dynamicb Total Gate Charge Qg N-Channel VDS = 10 V, VGS = 4.5 V, ID = 3.4 A P-Channel VDS = −10 V, VGS = −4.5 V, ID = −2.5 A N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch N-Channel VDD =10 V, RL = 10 Ω ID ≅ 1 A, VGEN = 4.5 V, RG = 6 Ω P-Channel VDD = −10 V, RL = 10 Ω ID ≅ −1 A, VGEN = −4.5 V, RG = 6 Ω P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 4.1 4 0.65 0.68 0.90 0.90 29 45 52 53 27 69 27 11 4.1 5 0.65 0.68 0.90 0.90 30 28 52 55 25 55 20 32 Ns Nc Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time tr Turn-Off Delay Time td(off) Fall Time tf Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 72435 S-50836Rev. B, 16-May-05 SPICE Device Model Si3586DV Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-Channel MOSFET Document Number: 72435 S-50836Rev. B, 16-May-05 www.vishay.com 3 SPICE Device Model Si3586DV Vishay Siliconix P-Channel MOSFET www.vishay.com 4 Document Number: 72435 S-50836Rev. B, 16-May-05