SI6955ADQ

SPICE Device Model Si6955ADQ Vishay Siliconix Dual P-Channel 30-V (D-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70550 S-60142Rev. B, 13-Feb-06 www.vishay.com 1 SPICE Device Model Si6955ADQ Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage a Symbol VGS(th) ID(on) rDS(on) gfs VSD Test Condition VDS = VGS, ID = −250 µA VDS = −5 V, VGS = −10 V VGS = −10 V, ID = −2.9 A VGS = −4.5 V, ID = −2.2 A VDS = −15 V, ID = −2.9 A IS = −1 A, VGS = 0 V Typical 2.2 61 0.070 0.108 5.5 0.8 Unit V A Ω S V Dynamic b Total Gate Chargeb Gate-Source Charge Gate-Drain Charge b b Qg Qgs Qgd td(on) tr td(off) tf trr IF = −1 A, di/dt = 100 A/µs VDD = −10 V, RL = 10 Ω ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω VDS = −10 V, VGS = −5 V, ID = −2.9 A 4.5 2 1.9 9 12 18 24 29 ns nC Turn-On Delay Timeb Rise Time b Turn-Off Delay Timeb Fall Timeb Source-Drain Reverse Recovery Time Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70550 S-60142Rev. B, 13-Feb-06 SPICE Device Model Si6955ADQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 70550 S-60142Rev. B, 13-Feb-06 www.vishay.com 3