SI9165DB

Si9165 Vishay Siliconix High Frequency 600-mA Synchronous Buck/Boost Converter DESCRIPTION The Si9165 provides fully integrated synchronous buck or boost converter solution for the latest one cell Lithium Ion cellular phones. Capable of delivering up to 600 mA of output current at + 3.3 V, the Si9165 provides ample power for various baseband circuits as well as for some PAs. It combines the 2 MHz switching controller with fully integrated high-frequency MOSFETs to deliver the smallest and most efficient converter available today. The 2 MHz switching frequency reduces the inductor height to new level of 2 mm and minimizes the output capacitance requirement to less than 10 µF with peak-to-peak output ripple as low as 10 mV. Combined with low-gate charge high-frequency MOSFETs, the Si9165 delivers efficiency up to 95 %. The programmable pulse skipping mode maintains this high efficiency even during the standby and idle modes to increase overall battery life and talktime. In order to extract the last ounce of power from the battery, the Si9165 is designed with 100 % duty cycle control for buck mode. With 100 % duty cycle, the Si9165 operates like a saturated linear regulator to deliver the highest potential output voltage for longer talktime. The Si9165 is available in lead (Pb)-free TSSOP-20 pin packages. In order to satisfy the stringent ambient temperature requirements, the Si9165 is rated to handle the industrial temperature range of - 25 °C to 85 °C. FEATURES • • • • Voltage Mode Control Fully Integrated MOSFET Switches RoHS 2.7 V to 6 V Input Voltage Range COMPLIANT Programmable PWM/PSM Control - Up to 600 mA Output Current at 3.3 V in PWM - Up to 2 MHz Adjustable Switching Frequency in PWM - Less than 200 µA Quiescent Current in PSM Integrated UVLO and POR Integrated Soft-Start Synchronization Shutdown Current < 1 µA • • • • STANDARD APPLICATION CIRCUITS VIN 2.7 to 6 V VOUT 0 to 600 mA VIN 2.7 to 6 V VDD MODE COIL VO VS VIN/OUT FB SHUTDOWN PWM/PSM SYNC PGND COMP ROSC REF GND SHUTDOWN PWM/PSM SYNC PGND VDD MODE VS VIN/OUT VO COIL PGND FB COMP ROSC REF GND VOUT 0 to 600 mA Boost Configuration Document Number: 70845 S-72058-Rev. D, 08-Oct-07 Buck Configuration www.vishay.com 1 Si9165 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Voltages Referenced to GND VDD MODE, PWM/PSM, SYNC, SD, VREF, ROSC, COMP, FB VO PGND Voltages Referenced to PGND VS, VIN/OUT COIL Peak Output Current Continuous Output Current Storage Temperature Range Operating Junction Temperature Power Dissipation (Package)a 20-Pin TSSOP (Q Suffix)b 20-Pin TSSOP Thermal Impedance (ΘJA) Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 8.0 mW/°C above 25 °C. Limit 6.5 - 0.3 V to VDD + 0.3 V - 0.3 V to VS + 0.3 V ± 0.3 6.5 - 0.4 V to VIN/OUT + 0.4 V 3 1 - 65 to 150 150 1.0 125 Unit V V A °C W °C/W Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Voltages Referenced to GND VDD MODE, PWM/PSM, SYNC, SD Voltages Referenced to PGND VS, VIN/OUT FOSC ROSC VREF Capacitor Limit 2.7 V to 6 V V 0 V to VDD 2.7 V to 6 V 200 kHz to 2 MHz 25 kΩ to 300 kΩ 0.1 Unit V V kΩ µF SPECIFICATIONS Test Conditions Unless Otherwise Specified 2.7 V < VDD < 6 V, VIN/OUT = 3.3 V, VS = 3.3 V IREF = 0 A TA = 25 °C, IREF = 0 VDD = 3.3 V, - 500 µA < IREF < 0 Limits Mina 1.268 1.280 Typb 1.3 1.3 3 60 2.3 VUVLOLH - VUVLOHL 2.4 0.1 6 0.7 VDD 0.3 VDD - 1.0 1.0 2.5 Maxa 1.332 1.320 Unit Parameter Reference Output Voltage Load Regulation Power Supply Rejection UVLO Under Voltage Lockout (turn-on) Hysteresis Soft-Start Time SS Time Mode Logic High Logic Low Input Current Symbol VREF ΔVREF PSRR VUVLO/LH VHYS tSS VIH VIL IL V mV dB V ms V µA www.vishay.com 2 Document Number: 70845 S-72058-Rev. D, 08-Oct-07 Si9165 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Otherwise Specified 2.7 V < VDD < 6 V, VIN/OUT = 3.3 V, VS = 3.3 V Limits Mina 2.4 0.8 - 1.0 2 Nominal 1.60 MHz, ROSC = 30 kΩ DMAX FSYNC/FOSC FSW = 2 MHz - 20 75 50 1.2 50 50 50 IBIAS AVOL VFB BW IEA Source (VFB = 1.05 V), VCOMP = 0.75 V Sink (VFB = 1.55 V), VCOMP = 0.75 V VIN ≤ VOUT = 2.7 to 5.0 V IOUT VIN ≥ VOUT = 2.7 to 6.0 V VIN = 3.3 V, VOUT = 3.6 V VIN = 3.6 V, VOUT = 2.7 V rDS(on) VS ≥ 3.3 V 1 600 600 150 150 130 160 165 25 VDD = 3.3 V, FOSC = 2 MHz IDD VDD = 3.3 V VDD = 3.3 V, SD = 0 V 500 180 750 250 1 µA 300 330 mΩ mA TA = 25 °C VFB = 1.5 V -1 50 1.270 1.258 60 1.30 1.30 2 -3 3 -1 1.330 1.342 1 µA dB V MHz mA ns 85 65 1.5 20 % 1.0 Typb Maxa Unit Parameter SD, SYNC, PWM/PSM Logic High Logic Low Input Current Oscillator Maximum Frequency Accuracy Maximum Duty Cycle (Buck, Non LDO Mode) Maximum Duty Cycle (Boost) SYNC Range SYNC Low Pulse Width SYNC High Pulse Width SYNC tr, tf Error Amplifier Input Bias Current Open Loop Voltage Gain FB Threshold Unity Gain BW Output Current Output Current Output Current (PWM) Boost Modec Buck Output Current (PSM) rDS(on) N-Channel rDS(on) P-Channel Over temperature protection Trip Point Hysteresis Supply Current Normal Mode PSM Mode Shutdown Mode Moded Modec Symbol VIH VIL IL FMAX V µA MHz Boost Buck Moded Rising Temperature °C Notes: a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. VIN = VDD, VOUT = VIN/OUT = VS = VO, L = 1.5 µH. d. VIN = VDD = VS = VIN/OUT, VOUT = VO, L = 1.5 µH. Document Number: 70845 S-72058-Rev. D, 08-Oct-07 www.vishay.com 3 Si9165 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1.310 1.32 1.305 V REF (V) V REF (V) 2.5 3.0 3.5 4.0 VDD - (V) 4.5 5.0 5.5 6.0 1.31 1.300 1.30 1.295 1.29 1.290 2.0 1.28 - 50 0 50 Temperature (°C) 100 150 VREF vs. VDD 2.00 10000 VREF vs. Temperature 1.95 ROSC = 25 kΩ Frequency (MHz) 1.85 Frequency (kHz) - 50 0 50 100 150 1.90 1000 1.80 1.75 1.70 - 100 100 10 100 ROSC (kΩ) 1000 Temperature (°C) Frequency vs. Temperature 100 95 90 PSM - 3.6 V PSM - 3 V Frequency vs. ROSC 95 90 85 Efficiency (%) PWM - 2.7 V PWM - 3.3 V PSM - 3.3 V Efficiency (%) 85 PSM - 4.2 V PWM - 3 V PWM - 3.6 V 80 PSM - 2.7 V 80 75 70 65 60 1 10 100 1000 Load Current (mA) PWM - 4.2 V 75 70 65 60 1 10 100 1000 Load Current (mA) Buck Mode Efficiency, VO = 2.7 V Boost Mode Efficiency, VO = 3.6 V www.vishay.com 4 Document Number: 70845 S-72058-Rev. D, 08-Oct-07 Si9165 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 800 250 700 200 600 I DD (mA) I DD (mA) 2 3 4 VDD - (V) 5 6 7 500 150 400 100 300 200 50 2 3 4 5 VDD - (V) 6 7 PWM Supply Current PSM Supply Current PIN CONFIGURATION AND ORDERING INFORMATION TSSOP-20 NC SD PWM/PSM VIN/OUT VIN/OUT VIN/OUT SYNC GND VREF FB 1 20 2 19 3 18 4 17 5 16 Si9165BQ 6 15 7 14 8 13 9 12 10 11 Top View COIL COIL MODE PGND PGND VS VO VDD ROSC COMP ORDERING INFORMATION Part Number Si9165BQ-T1-E3 Eval Kit Si9165DB Temperature Range - 25 to 85 °C Temperature Range - 25 to 85 °C Package Tape and Reel Board Type Surface Mount PIN DESCRIPTION Pin Number 1 2 3 4, 5, 6 7 8 9 10 11 12 13 14 15 16, 17 18 19, 20 Name N/C SD VIN/OUT SYNC GND VREF FB COMP Rosc VDD VO VS PGND MODE COIL Not Used Shuts down the IC completely and decreases current consumed by the IC to < 1 µA. Input node for buck mode and output node for boost mode. Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used, the pin must be connected to VDD, or logic high. Low power controller ground 1.3 V reference. Decoupled with 0.1 µF capacitor. Output voltage feedback connected to the inverting input of an error amplifier. Error amplifier output for external compensation network. External resistor to determine the switching frequency. Input supply voltage for the analog circuitry. Input voltage range is 2.7 V to 6 V. Direct output voltage sensing to control peak inductor current in PSM mode. Supply voltage for the internal MOSFET drive circuit. Power ground. Determines the converter topology. Connect to AGND for buck or VDD for boost. Inductor connection node Function PWM/PSM Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled. Document Number: 70845 S-72058-Rev. D, 08-Oct-07 www.vishay.com 5 Si9165 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VDD Positive Supply Reference Threshold Generator Soft-Start Timer UVLO POR Bias Generator OTP SD VS VIN/OUT VREF FB COMP 1.0 V Ramp SYNC Oscillator ROSC COSC VO PSM Modulator PWM Modulator PWMIN 0.5 V PWMEN PWM/PSM Select PSMEN Drivers N PSMIN P COIL PWM/PSM MODE Negative Return and Substrate GND PGND DETAIL OPERATIONAL DESCRIPTION Start-Up The UVLO circuit prevents the internal MOSFET switches and oscillator circuit from turning on, if the voltage on VDD pin is less than 2.5 V. With typical UVLO hysteresis of 0.1 V, controller is continuously powered on until the VDD voltage drops below 2.4 V. This hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. Once the VDD voltage exceeds the UVLO threshold, and with no other shutdown condition detected, an internal Power-On-Reset timer is activated while most circuitry, except the output driver, are turned on. After the POR timeout of about 1 ms, the internal soft-start capacitor is allowed to charge. When the soft-start capacitor voltage reaches 0.5 V, the PWM circuit is enabled. Thereafter, the constant current charging the soft-start capacitor will force the output voltage to rise gradually without overshooting. To prevent negative undershoot, the synchronous switch is tri-stated until the duty cycle reaches about 10 %. In tri-state, the high-side P-Channel MOSFET is turned off by pulling up the gate voltage to VS potential. The low-side N-Channel MOSFET is turned off by pulling down the gate voltage to PGND potential. Note that the Si9165 will always soft starts in the PWM mode regardless of the voltage level on the PWM/PSM pin. Shutdown The Si9165 is designed to conserve as much battery life as possible by decreasing current consumption of IC during normal operation as well as the shutdown mode. With logic low level on the SD pin, current consumption of the Si9165 is decreased to less than 1 µA by shutting off most of the circuits. The logic high enables the controller and starts up as described in "Start-Up" section above. www.vishay.com 6 Document Number: 70845 S-72058-Rev. D, 08-Oct-07 Si9165 Vishay Siliconix DETAIL OPERATIONAL DESCRIPTION (CONT’D) Over Temperature Protection The Si9165 is designed with over temperature protection circuit to prevent MOSFET switches from running away. If the temperature reaches 165 °C, internal soft-start capacitor is discharged, shutting down the output stage. Converter remains in the disabled mode until the temperature in the IC decreases below 140 °C. PWM Mode With PWM/PSM mode pin in logic high condition, the Si9165 operates in constant frequency (PWM) mode. As the load and line varies, switching frequency remain constant. The switching frequency is programmed by the Rosc value as shown by the Oscillator curve. In the PWM mode, the synchronous drive is always enabled, even when the output current reaches 0 A. In continuous current mode, transfer function of the converter remain constant, providing fast transient response. If the converter operates in discontinuous current mode, overall loop gain decreases and transient response time can be ten times longer than if the converter remain in continuous current mode. This transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc-dc converter to meet the transient voltage regulation. Therefore, the PWM/PSM pin is available to dynamically program the controller. The maximum duty cycle of the Si9165 can reach 100 % in buck mode. This allows the system designers to extract out the maximum stored energy from the battery. Once the controller delivers 100 % duty cycle, converter operates like a saturated linear regulator. At 100 % duty cycle, synchronous rectification is completely turned off. Up to a maximum duty cycle of 80 % at 2 MHz switching frequency, controller maintains perfect output voltage regulation. If the input voltage drops below the level where the converter requires greater than 80 % duty cycle, controller will deliver 100 % duty cycle. This instantaneous jump in duty cycle is due to fixed BBM time, MOSFET delay/rise/fall time, and the internal propagational delays. In order to maintain regulation, controller might fluctuate its duty cycle back and forth from 100 % to something less than maximum duty cycle while the converter is operating in this input voltage range. If the input voltage drops further, controller will remain on 100 %. If the input voltage increases to a point where it requires less than 80 % duty cycle, synchronous rectification is once again activated. The maximum duty cycle under boost mode is internally limited to 75 % to prevent inductor saturation. If the converter is turned on for 100 % duty cycle, inductor never gets a chance to discharge its energy and eventually saturates. In boost mode, synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been Document Number: 70845 S-72058-Rev. D, 08-Oct-07 www.vishay.com 7 turned on. The controller will deliver 0 % duty cycle, if the input voltage is greater than the programmed output voltage. Because of signal propagation time and MOSFET delay/rise/ fall time, controller will not transition smoothly from minimum controllable duty cycle to 0 % duty cycle. For example, controller may decrease its duty cycle from 5 % to 0 % abruptly, instead of gradual decrease you see from 75 % to 5 %. Pulse Skipping Mode The gate charge losses produced from the Miller capacitance of MOSFETs are the dominant power dissipation parameter during light load (i.e. < 10 mA). Therefore, less gate switching will improve overall converter efficiency. This is exactly why the Si9165 is designed with pulse skipping mode. If the PWM/PSM pin is connected to logic low level, converter operates in pulse skipping modulation (PSM) mode. During the pulse skipping mode, quiescent current of the controller is decreased to approximately 200 µA, instead of 500 µA during the PWM mode. This is accomplished by turning off most of internal control circuitry and utilizing a simple constant on-time control with feedback comparator. The controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blanking time. If the output voltage drops below the desired level, the main switch is first turned on and then off. If the applied on-time is insufficient to provide the desired voltage, the controller will force another on and off sequence, until the desired voltage is accomplished. If the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. The excess energy is delivered to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. The on-time and off-time are set internally based on inductor used (1.5 µH typical), mode pin selection and maximum load current. Wide duty cycle range can be achieved in both buck and boost configurations. In pulse skipping mode, synchronous rectifier drive is also disabled to further decrease the gate charge loss, which in turn improves overall converter efficiency. Reference The reference voltage of the Si9165 is set at 1.3 V. The reference voltage is internally connected to the non-inverting inputs of the error amplifier. The reference is decoupled with 0.1 µF capacitor. Si9165 Vishay Siliconix DETAIL OPERATIONAL DESCRIPTION (CONT’D) Error Amplifier The error amplifier gain-bandwidth product and slew rate is critical parameters which determines the transient response of converter. The transient response is function of both small and large signal response. The small signal is the converter closed loop bandwidth and phase margin while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. Besides the inductance value, error amplifier determines the converter response time. In order to minimize the response time, the Si9165 is designed with 2 MHz error amplifier gain-bandwidth product to generate the widest converter bandwidth and 3.5 V/µs slew rate for ultrafast large signal response. Oscillator The oscillator is designed to operate up to 2 MHz minimal. The 2 MHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. Even with 2 MHz switching frequency, quiescent current is only 500 µA with unique power saving circuit design. The switching frequency is easily programmed by attaching a resistor to ROSC pin. See oscillator frequency versus ROSC curve to select the proper values for desired operating frequency. The tolerance on the operating frequency is ± 20 % with 1 % tolerance resistors. Synchronization The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin. A logic high to low transition synchronizes the clock. The external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. Break-Before-Make Timing A proper BBM time is essential in order to prevent shootthrough current and maintain high efficiency. The breakbefore-make time is set internally at 20 ns at VS = 3.6 V. The high and low-side MOSFET drain voltages are monitored and when the drain voltage reaches the 1.75 V below or above its initial starting voltage, 20 ns BBM time is set before the other switch turns on. The maximum controllable duty cycle is limited by the BBM time. Since the BBM time is fixed, maximum controllable duty cycle will vary depending on the switching frequency. Output MOSFET Stage The high- and low-side switches are integrated to provide optimum performance and to minimize the overall converter size. Both, high and low-side switches are designed to handle up to 600 mA of continuous current. The MOSFET switches were designed to minimize the gate charge loss as well as the conduction loss. For the high frequency operation, switching losses can exceed conduction loss, if the switches are designed incorrectly. Under full load, efficiency of 90 % is accomplished with 3.6 V battery voltage in both buck and boost modes (+ 2.7 V output voltage for buck mode and + 5 V output voltage for boost mode). Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70845. www.vishay.com 8 Document Number: 70845 S-72058-Rev. D, 08-Oct-07 Package Information Vishay Siliconix TSSOP: 20-LEAD (POWER IC ONLY) B D N 4X 0.20 C A−B 0.20 H A−B E1 E 1.00 2X N/2 TIPS D D b bbb M C A−B D 9 0.05 C E/2 A2 A C 123 1.00 DIA. 1.00 (14_) A H e aaa A1 D SIDE VIEW SEATING PLANE C MILLIMETERS 0.25 + + H L 6 c 1.00 (14_) DETAIL ‘A’ (SCALE: 30/1) (VIEW ROTATED 90_ C.W.) C L B B PARTING LINE (∝) e/2 X X = A and B Dim A A1 A2 aaa b b1 bbb c c1 D E E1 e L N P P1 ∝ Min — 0.05 0.85 0.19 0.19 0.09 0.09 Nom — — 0.90 0.076 − 0.22 0.10 − 0.127 6.50 BSC 6.40 BSC Max 1.10 0.15 0.95 0.30 0.25 0.20 0.16 4.30 0.50 4.40 0.65 BSC 0.60 20 4.2 3.0 4.50 0.70 0_ — 8_ SEE DETAIL ‘A’ END VIEW ECN: S-40082—Rev. A, 02-Feb-04 DWG: 5923 LEAD SIDES TOP VIEW Document Number: 72818 28-Jan-04 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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