VSC3144

DATA INTERCONNECT VSC3144 6.5 Gbps 144 × 144 Asynchronous Crosspoint Switch BLOCK DIAGRAM: Switch Core Inputs [143:0] EQ EQ Outputs [143:0] VSC3144 Programming Interface F E AT U R E S : 6.5 Gbps 144 × 144 strictly nonblocking switch matrix with multicast and output striping programming modes Input signal equalization (ISE) with programmable control globally or on a per-channel basis Adjustable output pre-emphasis EQ Differential current mode logic (CML) data output driver Protocol-independent switching and data transmission 16 W typical power dissipation 45 mm × 45 mm, 1.27 mm pin pitch, 1072-pin BGA package Parallel and serial programming modes for configuration and monitoring Software control to optimize power dissipation BENEFITS: 936 Gbps aggregate bandwidth in a single chip for high-density network switching and video systems Addresses system-level and board-level signal integrity (SI) and intersymbol interface (ISI) jitter issues EQ and drive flexibility for driving boards, cables, and circuit traces Convenient I/O flexibility for interfacing with multiple standards Can be used with latest storage, Ethernet, and networking standards Low per-channel power Layout-friendly package and pinout for easier PCB design Programming and control convenience Control and lower overall power when ports are not in use A P P L I C AT I O N S : Core and metro transport Enterprise High-speed automated test equipment Broadcast video systems Storage, Ethernet, and networking equipment VPPD-01551 Revision 1.0 VSC3144 6.5 Gbps 144 × 144 Asynchronous Crosspoint Switch GENERAL DESCRIPTION: The fully nonblocking switch core of the VSC3144 device is programmed using a multimode port interface that allows random access programming of each I/O port. Each VSC3144 data output can be VSC3144 programmed to connect to any of its inputs. The signal path through the device uses no registers and is fully asynchronous. This means there are no restrictions on the phase, frequency, or signal pattern of any input. A high degree of signal integrity is maintained throughout the VSC3144 device because each high-speed output is a fully differential, switched-current driver with on-die terminations. Data inputs are terminated on-die using 100 Ω resistors between true and complement inputs, with a common connection to an internal bias source, which facilitates AC coupling to the switch inputs. Core programming for the VSC3144 device can be sequential on a port-by-port basis, or multiple program assignments can be queued and issued simultaneously using the CONFIG bit. The entire device can be initialized for straight-through, multicast, or other configurations. Unused channels can be powered down to allow efficient use of the switch in applications that require only a subset of the available I/O channels. Power-down is enabled in the software by programming individual unused outputs with a power-down code. B A C K P L A N E A P P L I C AT I O N : Line Cards OE FPGA/ ASIC B a c k p l a n e Central Switch VSC3144 S P E C I F I C AT I O N S : 6.5 Gbps NRZ per-channel data rate 2.5 V power supply (2.5 V or 3.3 V program port power supply) 2.5 V or 3.3 V CMOS TTL-compatible I/O Differential CML I/O with integrated termination impedance 0 °C to 85 °C operating temperature range Trademarks TM Vitesse, ASIC-Friendly, FibreTimer, TimeStream, Snoop Loop, Super FEC, FOCUSConnect, Meigs-II, Meigs-IIe, Lansing, Campbell-I, Barrington, PaceMaker, HOVCAT48, HOVCAT48e, HOVCAT192, HOVCAT192e, Micro PHY, FOCUS32, FOCUS16, IQ2200, NexSAS, VersaCAT, GigaStream, HawX, SparX, StaX, VstaX, SimpliPHY,VeriPHY, ActiPHY, XFP PRO, SFP PRO, Smart-LINK, OctalMAC, EQ Technology are trademarks in the United States and/or other jurisdictions of Vitesse Semiconductor Corporation. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. Copyright © 2006 Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. 741 Calle Plano Camarillo, CA 93012, USA Tel: +1 805.388.3700 Fax: +1 805.987.5896 www.vitesse.com sales@vitesse.com