VSC6511RC

VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 Features • Compliant with SMPTE-292M @ 1.485Gb/s • Multiple Functions: Serializer, Deserializer, and Deserializer with Reclocker • 20 Bit TTL Interface @ 74.25 MHz • Scrambler / Descrambler with ENABLE • CRC Generator/Checker with ENABLE SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s • Data Framer aligns data and provides TRS on SAV/EAV events • Clock Multiplier and Recovery Units • 2 or 4 configurable 75ohm cable driver o/ps • 3.3V, Low power -- 700-1500mW typical • 64-pin, 10x10x1.0mm Exposed Pad TQFP General Description The VSC6511 multi function SMPTE-292M compatible IC with Serializer, Deserializeror, or Deserializer with reclocker modes which operate at 1.485Gb/s. As a Serializer, 20-bits of data (D19:0) are latched into the part on the rising edge of REFCLK then scrambled and serialized out SDO0/SDO0 and/or SDO1/SDO1. An optional CRC Generator may be enabled. As a Deserializer, serial data on SDI/SDI is recovered, de-scrambled and deserialized onto D[19:0]. Frame alignment on SAV/EAV, line detection and frame detection outputs are provided. As a Deserializer with reclocker, the device functions as ain the deserializer mode above and serial data on SDI/SDI is recovered and retransmitted on SDO0/SDO0 and/or SDO1/SDO1. Draft Copy VSC6511 Block Diagram OE0 SDO0 SDO0 ISET0 OE1 SDO1 SDO1 ISET1 CABLE DRIVER OUTPUTS D[19:0] DQ CRC Gen Scrambler Serializer SCREN CRC SIGDET IP IN Clock/ Recovery Unit Deserializer 1.485 GHz NRZI Decoder Descrambler CRC Check DQ /20 Framer MODE0 MODE1 REFCLK 74.25 MHz Clock Multiply x20 1001 LINE FRAME HANC RCLK /20 1.485 GHz G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Functional Description The VSC6511 is a multifunction SMPTE-292M device which can be configured for different modes of operation: Serializer, Deserializer, or Deserializer/Reclocker. Only one mode is available at a time. A discussion of the individual building blocks of the device will be followed with specific configurations. Clock Multiplier Unit (CMU) The CMU generates the internal 1.485 GHz baud rate clock from the 74.25 MHz TTL REFCLK input. The rising edges of the REFCLK are used by a PLL which multiplies the frequency by a factor of 20. This internal baud rate clock is used by the Serializer, Deserializer and Reclocker. An off-chip 0.1uF capacitor sets the loop bandwidth of the CMU. REFCLK should be a high quality, low jitter signal with sharp rise times in order to minimize the amount of jitter transferred from the REFCLK through the CMU to the serializer. This optimizes the signal quality at the output of the serializer. A secondary function of the CMU is to divide the baud rate clock by 20 to produce an internal 74.25 MHz clock which is frequency locked and phase aligned to REFCLK. This internal clock is used to latch the 20-bit data bus D[19:0] into the input register of the Serializer. REFCLK is also buffered onto the RCLK output when in Serializer or Reclocker mode. This allows multiple devices to be daisy-chained in order to simplify REFCLK distribution to an array of devices. CRC Generator The twenty bits of transmit data from the input register is fed into a CRC Generator which calculates the CRC and substitutes the value into the proper location within the video line. The CRC polynomial is CRC(X)= (X18 + X5 + X4 + 1). A controller monitors SAV/EAV position and uses this to control the CRC generator and insertion of the CRC result into the line. The CRC Generator is enabled only in Serializer Mode when CRC is HIGH. In other modes, or if CRC is LOW, the CRC Generator is disabled and powered down. CRC is a bidirectional pin. Scrambler and NRZI Encoder The twenty bits out of the CRC Generator are sent to the parallel Scrambler where the data is scrambled and NRZI encoded using the combined generator polynomial of G(x)=(x9 + x4 +1)(x+1). Scrambling is enabled only when in Serializer Mode if SCREN is HIGH. Scrambling is disabled when SCREN is LOW and in other modes. Serializer The data from the Scrambler is converted from 20-bits at 74.25 Mb/s to 1 bit at 1.485 Gb/s by the Serializer with D0 being transmitted first. Two differential PECL-style serial outputs are provided for transporting the 1.485 Gb/s signal. These outputs SDO0/SDO0 and SDO1/SDO1 are supplied data from the serializer (in Serializer mode) or the CRU of the Reclocker (in Deserializer/Reclocker mode). Each output, SDO0 and SDO1, have independent TTL inputs, OE0 and OE1, which when HIGH enable the outputs and when LOW disable the outputs. When disabled, the output buffer will be powered down and both legs will float HIGH. Each output is compliant with the SMPTE-292M cable driver specification when driving 75 ohm loads. In this application, a TBD ohm resistor should be connected from the ISET0/ISET1 pin to ground in order to control the current in the differential output amplifier. By lowering the ISET resistor, higher output swings may be realized. Draft Copy Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Serial Input The differential PECL-style input, SDI/SDI, is the input source for 1.485 Gb/s SMPTE-292M data in the Deserializer and Reclocker modes. This input is ignored in Serializer mode. Clock Recovery Unit The serial data on the SDI/SDI input is sent to the digital Clock Recovery Unit (CRU) which extracts the clock and retimes the data. This digital CRU is completely monolithic and requires no external components. Furthermore, it automatically locks onto data when present and locks to REFCLK when data is not present. This eliminates the need for the system to control the CRU. The CRU is enabled only in the Deserializer and Deserializer/Reclocker modes. Deserializer The reclocked serial bit stream is deserialized into a 20-bit parallel character. D0 is serially received prior to D1. The VSC6511 provides a TTL recovered clock, RCLK at one twentieth of the serial baud rate. This clock is generated by dividing down the high-speed clock from the CRU which is phase locked to the serial data. The deserializer is enabled only in the Deserializer and Deserializer/Reclocker modes. If serial input data is not present, or does not meet the required baud rate, the VSC6511 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK output frequency under these circumstances will differ from their expected frequency by less than +1%. Descrambler and NRZI Decoder The VSC7152 contains a descrambler/NRZI Decoder which processes the recovered serial data and outputs unscrambled and NRZI decoded serial data from the deserializer. The serial scrambled data is descrambled/ NRZI decoded assuming data has been scrambled/NRZI encoded with the following combined generator polynomial: G(x)=(x9+x4+1)(x+1). Descrambling is enabled with the SCREN input is HIGH and disabled when LOW. The descrambler is enabled only in the Deserializer mode. CRC Checker The 20-bit data from the Descrambler is sent to the CRC Checker where a running CRC checksum is continuously calculated. As 20-bit data is sent out of the chip, the CRC output pin is asserted if the checksum did not meet the value expected. This error is asserted from the first CRC Error until the end of the line. A controller monitors the 20-bit data out of the serializer for SAV/EAV frames in order to control the CRC Checker. The CRC Checker is enabled only in Deserializer and Deserializer/Reclocker modes. Frame Aligner The VSC6511 monitors the serial data stream for SAV/EAV characters. These characters should be located within each line of video data. If SAV/EAV is not detected within the period of one line, the Framer sends a signal to the Deserializer to shift the data one bit. The Framer then looks for SAV/EAV and the process repeats until properly detected. Without these patterns, serial data is not aligned in any way with the parallel outputs. The Framer outputs a once-per-line (LINE), Horizontal ANCilliary period (HANC), 1.001/1.000 output (1.001) and a once-per-frame (FRAME) signal indicating the detection of the proper synchronization pulse in the data. Framing is enabled only in Deserializer mode. The Frame Aligner also outputs the LINE, FRAME and HANC outputs signals. The timing of these signals is indicated below. Draft Copy G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Table 1: Frame Aligner Output Timing D10-19 ACTIVE VIDEO DATA --DATA 3FF EAV 000 000 XYZ LINE LN0 LN1 CRC0 CRC1 DATA --DATA 3FF SAV 000 000 XYZ ACTIVE VIDEO DATA DATA --- Advance Product Information VSC6511 D0-9 DATA --DATA 3FF 000 000 XYZ LN0 LN1 CRC0 CRC1 DATA --DATA 3FF 000 000 XYZ DATA DATA --- LINE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 FRAME 0 0 0 0 0 0 0 0 1* 0 0 0 0 0 0 0 0 0 0 0 0 HANC 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 CRCERR 0 0 0 0 0 0 0 0 0 0 0 or 1 0 0 0 0 0 0 0 0 0 0 Draft Copy HORIZ BLANK CRC * FRAME is HIGH only if LN0/LN1 indicates the first line of a frame. ** CRCERR is HIGH only during CRC1 if the CRC is incorrect. D[19:0] Databus As mentioned previously, in Serializer mode D[19:0] is configured as a input. In Deserializer mode, D[19:0] is configured as an output. Application Information The VSC6511 cable driver output is intended to fully comply with the SMPTE-292M cable driver specifications. This includes an 800mV swing and a return loss of more than 15dB. The circuit shown below shows how to connect the output of the VSC6511 to the 75 ohm cable and downstream device. The output of the VSC6511 is actually 1200mV. The output termination circuit shown below attenuates the output signal to 800mV and ensures a return loss better than -15dB. The ISET resistor is 1.78K Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Figure 1: High Speed Interconnect Example (Differential) VDD 75 10nH 75 6511 75 1.78K ISETx 10nH 75 VDD 75 ohm Cables Draft Copy VSS NOTE: All resistors are 1% WARNING: SUBJECT TO CHANGE Figure 2: High Speed Interconnect Example (Single Ended) VDD 75 10nH 75 6511 75 1.78K ISETx VSS 75 ohm Coax 10nH 75 VDD or 75 VDD 37.5 VDD NOTE: All resistors are 1% Optional use of external Voltage Reference provides tighter swing tolerance G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 The output swing of the VSC6511 is controlled through the ISETx pins and a VREF input. By connecting an 1.78K ohm resistor, 1%, between VSS and ISETx the output swing will be controlled to within 800mV +/7%. An optional bandpass voltage reference may be used to further tighten the output swings by accurately driving the VREF input. Configuration Modes: The MODE(1:0) inputs configure the VSC6511 into its different modes of operation. The table below summarizes the different signals and circuits in the VSC6511 that change function in the different modes. Table 2: Mode Configuration Features: Serializer Mode SIGNAL/CIRCUIT MODE1 MODE0 D[19:0] Data Bus SDO0/SDO1 Serial Outputs RCLK Output CRU Bypass Mux SDI Serial Input CRC SIGDET Output 1.001 Output FRAME Output LINE Output HANC Output DESERIALIZER MODE HIGH HIGH 20-BIT OUTPUT NOT USED, DISABLED RECOVERED CLOCK FROM CRU NOT ACTIVE ACTIVE CRC is an error output ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE DESERIALIZER/ RECLOCKER MODE LOW HIGH 20-BIT OUTPUT SOURCE IS CRU OUTPUT OR SDI/SDI RECOVERED CLOCK FROM CRU CRU OUTPUT GOES TO SDO0/SDO1 ACTIVE CRC is an error output ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE SERIALIZER MODE LOW LOW 20-BIT INPUT SOURCE IS SERIALIZER BUFFERED REFCLK CRU NOT ACTIVE IGNORED Enables CRC Generator DISABLED LOW DISABLED LOW DISABLED LOW DISABLED LOW DISABLED LOW Draft Copy Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 Features: Serializer Mode 1. 20 Bit TTL Interface @ 74.25 MHz 2. On-chip Clock Multiplier Unit 3. On-Chip Scrambler and NRZI Encoder with ENABLE 4. CRC Generator with ENABLE 5. 2 or 4 user configurable 75ohm cable driver outputs 6. Output Signal Detect indicators 7. Buffered REFCLK output for easy clock distribution 8. 700 mW Typical Power SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Description The VSC6511 can be configured as a 20-bit HDTV Serializer using the MODE[1:0] pins. A 74.25 MHz TTL REFCLK is multiplied by 20 in the Clock Multiplier Unit (CMU) to generate a 1.485 GHz bit rate clock. The CMU aligns a divided-by-20 clock with REFCLK in order to latch the 20-bit TTL data bus D[19:0] into the Input Register. When enabled by CRC being HIGH, the data is monitored for SAV/EAV and a CRC checksum is calculated and inserted into the data stream at the appropriate point in each video line. The data is then scrambled and NRZI encoded, only if this stage is enabled by SCREN=HIGH. The data is then serialized and output on the differential outputs, SDO0/SDO0 and SDO1/SDO1, which are compliant with the SMPTE 292M cable driving specifications. The scrambler and NRZI encoder can be disabled by setting the TTL input, SCREN to LOW. The SDO0/SDO0 output can be disabled and forced HIGH by setting the TTL input OE0 to LOW. Similarly, the SDO1/SDO1 output can be disabled and forced HIGH by setting the TTL input OE1 to LOW. Figure 3: Serializer Mode OE0 SDO0 SDO0 ISET0 OE1 SDO1 SDO1 ISET1 CABLE DRIVER OUTPUTS Clock Multiply x20 Draft Copy D[19:0] DQ Scrambler CRC Gen * NRZI Encoder Serializer CRCEN SCREN REFCLK 74.25 MHz /20 1.485 GHz RCLK G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Functional Description: Serializer Mode The following functional blocks are used in the Serializer mode of operation. Please refer to the Functional Description at the beginning of this document for the a description of each of these blocks. Clock Multiplier Unit (CMU) CRC Generator Scrambler and NRZI Encoder Serializer Cable Driver Outputs Table 3: Transmit AC Characteristics (Serializer Mode) Parameters Description D[0:19] Setup time to the rising edge of REFCLK D[0:19] hold time after the rising edge of REFCLK SDO0, SDO1 rise/fall time SDO0/SDO1 output jitter Min 2.0 Max — Units ns. Conditions Measured from the valid data level of D[0:19] to the crossing of REFCLK Draft Copy T1 T2 TR,TF TRJ 1.5 150 — — 270 0.20 ns. ps. UI 20% to 80%, 75 Ohm load to Vdd, Tested on a sample basis Figure 4: Transmit Timing Waveforms (Serializer mode) REFCLK T1 T2 D[19:0] Data Valid Data Valid Data Valid Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 Table 4: Transmit AC Characteristics (Serializer Mode) Parameters T1 T2 TR,TF TRJ SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Description D[0:19] Setup time to the rising edge of REFCLK D[0:19] hold time after the rising edge of REFCLK SDO0, SDO1 rise/fall time SDO0/SDO1 output jitter Min 2.0 Max — Units ns. Conditions Measured from the valid data level of D[0:19] to the crossing of REFCLK 1.5 150 — — 270 0.20 ns. ps. UI 20% to 80%, 75 Ohm load to Vdd, Tested on a sample basis Draft Copy G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Features: Deserializer Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Compliant with SMPTE-292M @ 1.485Gb/s Clock and Data Recovery 1:20 Deserializer Descrambler and NRZI Decoder with ENABLE Data Framer aligns data to SAV/EAV On-chip Clock Multiplier Unit CRC Checker LINE, FRAME, HANC Indication 3.3V, 800 mW -- typical power 20 Bit TTL Interface @ 74.25 MHz General Description Draft Copy The VSC6511 can be configured as a 20-bit HDTV Deserializer using the MODE[1:0] pins. Serial data from SDI/SDI is sent to the Clock Recovery Unit (CRU) for clock extraction and data resynchronization. Then the serial data is descrambled/NRZI decoded, deserialized and output on D[19:0] synchronously by a dividedby-twenty recovered clock, RCLK. A CRC Checker monitors the output data and indicates any CRC errors on the CRC pin. Descrambling is enabled by SCREN being HIGH. Data framing aligns the SAV/EAV patterns in the data with the data bus and RCLK and generates a once-per-line and once-per-frame synchronization output. A signal detect function on SDI/SDI monitors the quality of the serial input. Figure 5: Deserializer Mode D[19:0] SCREN SIGDET SDI SDI Clock Recovery Unit Deserializer 1.485 GHz NRZI Decoder Descrambler CRC Check DQ /20 Framer REFCLK 74.25 MHz Clock Multiply x20 CRCERR LINE FRAME HANC 1001 RCLK 1.485 GHz Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Functional Description: Deserializer Mode The following functional blocks are used in the Deserializer mode of operation. Please refer to the Functional Description at the beginning of this document for the a description of each of these blocks. Clock Multiplier Unit (CMU) Serial Input Clock Recovery Unit Deserializer Descrambler and NRZI Decoder CRC Checker Frame Aligner and SAV/EAV output Figure 6: Receive Timing Waveforms (Deserializer Mode) Draft Copy RCLK D[0:19] LINE FRAME CRCERR T1 Data Valid T2 Table 5: Receive AC Characteristics (Deserializer Mode) Parameters T1 T2 TR, TF TLOCK Description TTL Outputs alid prior to RCLK rise TTL Outputs valid after RCLK rise TTL Output rise and fall time Data acquisition lock time @ 1.485 Gb/s Min. 3.0 2.0 — — Max. — — 2.0 TBC Units ns. ns. ns. ms. Conditions Between VIL(MAX) and VIH(MIN), into 10 pf. load. Note: The RCLK output from the CRU is 40% high and 60% low by design. G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Features: Deserializer / Reclocker Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Compliant with SMPTE-292M @ 1.485Gb/s Clock and Data Recovery 1:20 Deserializer Descrambler and NRZI Decoder with ENABLE Data Framer aligns data to SAV/EAV 2 or 4 User Configurable 75 ohm cable driver outputs On-chip Clock Multiplier Unit LINE, FRAME, HANC Indication CRC Checker 20 Bit TTL Interface @ 74.25 MHz On-chip Clock Multiplier and Recovery Unit 3.3V, 900mW -- typical power. General Description Draft Copy In the Deserializer/Reclocker Mode, both the Deserializer and the Reclocker are active. All the features of each function are available with the exception of the reclocker status/control pins on the databus D0 and D2. In this mode, D[0:19] is used solely for the deserialized recovered data. Also, RCLK is used for the deserializer’s recovered clock and will not provide a buffered version of REFCLK and the BYPASS capability is also not available. Figure 7: Block Diagram: Deserializer/Reclocker Mode OE0 SDO0 SDO0 ISET0 OE1 SDO1 SDO1 ISET1 CABLE DRIVER OUTPUTS D[19:0] SCREN SIGDET SDI SDI Clock Recovery Unit Deserializer 1.485 GHz NRZI Decoder Descrambler CRC Check DQ /20 Framer REFCLK 74.25 MHz Clock Multiply x20 CRCERR LINE FRAME HANC RCLK 1.485 GHz Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 TL REFCLK SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Figure 8: REFCLK Timing Waveforms: All Modes TH VIH(MIN) VIL(MAX) TR Table 6: Reference Clock Requirements * Parameters FR FO Description Frequency Range Frequency Offset REFCLK duty cycle REFCLK high/low times REFCLK rise Min 73.75 -1000 -15 3.0 — Max 74.50 1000 +15 — 2.0 Units MHz ppm. % ns. ns. Conditions Will accept both 74.176/74.25MHz Difference in REFCLK frequencies between the transmitting and receiving VSC6511s. Measured at 1.5V Measured between VIL(MAX) to VIL(MAX) or VIH(MIN) to VIH(MIN) Between VIL(MAX) and VIH(MIN) Draft Copy DC T H, TL TR Note: The PLL locks to the rising edge of REFCLK. Figure 9: RCLK Timing Waveforms* TL RCLK TR TH VIH(MIN) VIL(MAX) Table 7: RCLK Performance - Deserializer and Deserializer/Reclocker Mode Parameters FOFFSET DC TH TL TR Description RCLK Frequency offset from REFCLK RCLK duty cycle - 40% / 60% RCLK high times RCLK low times RCLK rise/fall time Min -1.0 -5 3 5.9 — Max +1.0 +5 — — 1.5 Units % % ns. ns. ns. Conditions Maximum deviation when the CRU is not locked. Deserializer Mode. Measured at 1.5V. Deserializer Mode and Deserializer/Reclocker Mode. Measured between VIH(MIN) to VIH(MIN) Measured between VIL(MAX) to VIL(MAX) Between VIL(MAX) and VIH(MIN) Note: The RCLK output from the CRU is 40% high and 60% low by design. G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Table 8: RCLK Performance - Serializer & Reclocker Modes Parameters DC T H, TL Description RCLK duty cycle - 50% / 50% RCLK high/low times Min -5 3.5 Advance Product Information VSC6511 Max +5 — Units % ns. Conditions Measured at 1.5V. Serializer & Reclocker Modes (REFCLK=50/50) Measured between VIL(MAX) to VIL(MAX) or VIH(MIN) to VIH(MIN) — 1.5 ns. TR RCLK rise/fall time Between VIL(MAX) and VIH(MIN) Note: The RCLK output is a buffered version of the REFCLK input. The above specifications assume a 50% duty cycle on the REFCLK input. Absolute Maximum Ratings (1) Power Supply Voltage (VDD) .............................................................................................................-0.5V to +4V PECL DC Input Voltage ......................................................................................................... -0.5V to VDD +0.5V TTL DC Input Voltage....................................................................................................................... -0.5V to 5.5V DC Voltage Applied to TTL Outputs ................................................................................... -0.5V to VDD + 0.5V TTL Output Current ..................................................................................................................................+/-50mA PECL Output Current ................................................................................................................................+/-50mA Case Temperature Under Bias .........................................................................................................-55° to +125oC Storage Temperature.......................................................................................................................-65° to + 150oC Maximum Input ESD (Human Body Model).............................................................................................. 1500 V Draft Copy Recommended Operating Conditions Power Supply Voltage.................................................................................................... ....... ...... ........3.3V +/- 5% Ambient Operating Temperature Range...............................................................0 °C Ambient to +95°C Case Notes: 1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Page 14 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s DC Characteristics (Over recommended operating conditions). Parameters VIH VIL IIH IIL VOH VOL VDD Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH Voltage (TTL) Output LOW Voltage (TTL) Supply voltage Power Dissipation: (Estimated) Serializer Mode Deserializer Mode Deserializer/Reclocker Mode PECL input swing: PECL output swing: Min 2.0 0 — — 2.4 — 3.14 Typ — — — — — — — Max 5.5 0.8 500 -500 — 0.5 3.47 Units V V µA µA V V V Conditions — VIN = 2.4 V, 6.8Kohm Pullup resistor on all inputs. VIN = 0.5 V, 6.8Kohm Pullup resistor on all inputs. IOH = -1.0mA IOL= +1.0mA VDD = 3.3V + 5% Outputs open, VDD = VDD max (These are estimates) AC Coupled. Internally biased at VDD/2 Using appropriate matching network Draft Copy PD — — — 700 800 900 mW ∆VIN ∆VOUT75 200 750 — — 1200 850 mVp-p mVp-p G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Package Pin Descriptions Figure 10: Pin Diagram MODE1 MODE0 63 V53 D0 D1 D2 VDDT 5 3 1 61 59 57 55 53 51 49 VSST 47 D10 D11 45 D12 VDDT 43 D13 D14 Draft Copy D3 D4 D5 D6 VDDT D7 D8 D9 VSST VSSA CAP0 15 17 19 21 23 25 27 29 31 13 11 9 7 TEST1 VDDD VDDD ISET1 ISET0 VREF SDO1 SDO1 SDO0 SDO0 VSSP VSSP OE1 OE0 VSC6511 41 D15 D16 39 VDDT D17 37 D18 D19 35 VSST LINE 33 SIGDET (Top View) CAP1 SCREN HANC FRAME TEST2 VDDD REFCLK VDDA VDDD VDDD RCLK 1.001 CRC SDI VSST SDI Table 9: Pin Identification Pin # 2,3,4,6 7,8,9,11 12,13,47,46 45,43,42,41 40,38,37,36 50 64 24 Name D0-D3 D4-D7 D8-D11 D12-D15 D16-D19 MODE0 MODE1 SCREN Description INPUT/OUTPUT - TTL Bidirectional data bus. In Serializer mode, this is a 20-bit input bus timed to REFCLK. In Deserializer mode, this is a 20-bit output bus timed to RCLK. In Reclocker and Cable Driver mode, several of these bits are defined as status outputs. INPUT - TTL: Mode select inputs. See Table #2. INPUT - TTL: When HIGH, enables scrambling in Serializer/Deserializer modes Page 16 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 Pin # Name SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Description 30 CRC BIDIRECTIONAL - TTL: In Serializer Mode, CRC Generation is enabled when this input is HIGH and disabled when LOW. In Deserializer Mode and Deserializer/Reclocker Mode, this is an output which indicates a CRC error has occurred. OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an output which, when HIGH, indicates that a FRAME synchronization event is on D[0:19]. OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an output which, when HIGH, indicates that a LINE synchronization event is on D[0:19]. OUTPUT- TTL: Output which is HIGH during the Horizontal Blanking period between EAV and SAV. OUTPUT - TTL: When HIGH, indicates that a valid receive signal is present on SDI/SDI and that the SMPTE-292M incoming data is greater than 500ppm from 20xREFCLK. INPUT - Differential. Serial input to CRU. OUTPUT - Differential. High Speed Cable Driver output. Serial output from the Serializer, Reclocker or SDI/SDI input buffer. Connect resistor to ground to set the output swing of SDO0, and SDO1 INPUT - TTL. Output enable pins for SDO0, and SDO1. Enabled when high for each output. INPUT - TTL. REFerence CLocK at 74.25 MHz. This is the input to the CMU and times D(19:0) in Serializer Mode. OUTPUT - TTL: Output clock. In Serializer and Reclocker Mode, this is a buffered version of REFCLK. In Deserializer Mode, this is the recovered clock used to time D(19:0). OUTPUT - TTL. An analog signal detect output which, when HIGH, indicates that the IP/IN input contains a valid SMPTE-292M amplitude signal. Analog I/O: Loop Filter Capacitor, 0.1uF nominal, 3V swing maximum INPUT - POWER: This power supply would normally be 3.3V. If 5V tolerance is required, this pin should be connected to 5V supply. Power Supply. 3.3V Supply for digital logic. TTL I/O Power Supply. Voltage Reference Input. If used, this is biased to 1.25V. Analog Power Supply. 3.3V for Clock Multiplier PLL. Bypass to pin 15. Ground for High Speed Outputs TTL I/O Ground Analog Ground Bypass to pin 18. 26 FRAME 34 LINE 27 HANC Draft Copy 25 21,22 56,54 60,58 52,62 53,61 29 1.001 SDI, SDI SDO0, SDO0 SDO1, SDO1 ISET0, ISET1 OE0, OE1 REFCLK 31 RCLK 33 16,17 49,19 1 20,23,28,57,51 5,10,39,44 63 18 55,59 14,32,35,48 15 SIGDET CAP0, CAP1 TEST1, TEST2 INPUT - TTL. LOW for factory test, HIGH for normal operation. V53 VDDD VDDT VREF VDDA VSSP VSST VSSA G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Package Thermal Characteristics The VSC6511 is packaged in an exposed pad, thin quad flat pack (TQFP) which adheres to industry standard EIAJ footprints for a 10x10x1.0mm body, 64 lead TQFP. The package construction is shown below. The bottom of the lead frame is exposed so that it can be soldered to the printed circuit board and connected to the ground plane. This provides excellent thermal characteristics and reduces electrical parasitics as well. Figure 11: Package Cross Section Wire Bond Die Die Attach Epoxy Plastic Molding Compound Copper Lead Frame Draft Copy Ground Bond Exposed Pad Table 10: 64-pin, Exposed Pad TQFP Thermal Resistance Symbol θca-0 θca-100 θca-200 θca-400 θca-600 Description Thermal resistance from case to ambient, still air Thermal resistance from case to ambient, 100 LFPM air Thermal resistance from case to ambient, 200 LFPM air Thermal resistance from case to ambient, 400 LFPM air Thermal resistance from case to ambient, 600 LFPM air Value 30 25 23 21 20 Units oC/W oC/W oC/W oC/W oC/W The VSC6511 is designed to operate with a case temperature up to 95oC. The user must guarantee that the case temperature specification is not violated. With the thermal resistances shown above, the VS6511 can operate in still air ambient temperatures of 70oC [~70oC = 95oC - 0.8W * 30]. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided. Additional heat can be transferred to the printed circuit board by not using thermal reliefs on the power and ground plane vias as well as using multiple vias to the power and ground planes. If the exposed pad is not soldered to the printed circuit board and grounded, both thermal and electrical performance will be degraded significantly. Moisture Sensitivity Level This device is rated with a Moisture Sensitivity Level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures. Page 18 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 F G 64 49 SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Package Information: 64-pin Exposed Pad TQFP Item A A1 1 48 mm 1.20 0.10 1.00 0.22 12.00 10.00 12.00 10.00 0.60 0.50 x.xx x.xx Tolerance MAX ±0.05 ±0.05 ±0.05 ±0.40 ±0.10 ±0.40 ±0.10 ±0.15 BSC ±0.xx ±0.xx N A2 E F M I H G H I J Draft Copy 16 33 K M N 17 32 11/13o Exposed Pad (Bottom Side) A A2 11/130 K A1 0.08/0.20 R 0.08 R. MIN. 0o-7o 0.09/0.20 E J 0.xxx MAX. LEAD NONPLANARITY NOTES: Drawing not to scale. Exposed Pad Electrically Grounded All dimensions in millimeters G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 19 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Ordering Information The order number for this product is formed by a combination of the device number, and package type. VSC6511 Device Type VSC6511 - SMPTE-292M Multifunction Chip Package Type RC: 64-Pin, 10x10x1.0mm, Exposed Pad TQFP RC Marking Information The package is marked with three lines of text as shown below. Figure 12: Package Marking Information Draft Copy Pin 1 Identifier VITESSE Part Number Date Code VSC6511 RC ####AAAA Package Suffix Lot Tracking Code Notice This document contains information about a product during its fabrication or early sampling phase of development. The information contained in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this data sheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 20 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC6511 Revision History 2.0 New Document. SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Draft Copy G52311-0, Rev. 2.0 4/10/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 21 VITESSE SEMICONDUCTOR CORPORATION SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s Advance Product Information VSC6511 Draft Copy Page 22 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52311-0, Rev 2.0 4/10/00