VSC7121

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7121 Description • Supports ANSI X3T11 1.0625 Gbit/sec FC-AL Disk Attach for Resiliency • Fully Differential for Minimum Jitter Accumulation. • Quad PBC’s in Single Package Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays • TTL Bypass Select • High Speed, PECL I/O’s Referenced to VDD. • 0.5W Typical Power Dissipation • 3.3V Power Supply • 44-Pin, 10mm PQFP The VSC7121 is a Quad Port Bypass Circuit (PBC). Four Fibre Channel PBC’s are cascaded into a single part to minimize part count, cost, high frequency routing, and jitter accumulation. Port Bypass Circuits are used to provide resiliency in Fibre Channel Arbitrated Loop (FC-AL) architectures. PBC’s are used within FC-AL disk arrays to allow for resiliency and hot swapping of FC-AL drives. A Port Bypass Circuit is a 2:1 Multiplexer with two modes of operation: NORMAL and BYPASS. In NORMAL mode, the disk drive is connected to the loop. Data goes from the 7121’s L_SOn pin to the Disk Drive RX input and data from the disk drive TX output goes to the 7121’s L_SIn pin. Refer to Figure 2 for disk drive application. In BYPASS mode, the disk drive is either absent or non-functional and data bypasses to the next available disk drive. Normal mode is enabled with a HIGH on the SEL pin and BYPASS mode is enabled by a LOW on the SEL pin. Direct Attach Fibre Channel Disk Drives have an “LRC Interlock” signal defined to control the SEL function. Using a VSC7121 in a single loop of a disk array is illustrated in Figure 2: “Disk Array Application”. FCAL drives are all expected to be dual loop. The VSC7121 is cascaded in a manner such that all the 7121’s internal PBC’s are used in the same loop. For dual loop implementations, two or more VSC7121’s should be used. Allocating each VSC7121 to only one of two loops preserves redundancy, prevents a single point of failure and lends itself to on-line maintainability. 7121 Block Diagram LSO1+ LSO1LSO2+ LSO2LSO3+ LSO3LSO4+ LSO4LSI1+ LSI1LSI2+ LSI2LSI3+ LSI3LSI4+ LSI4SEL1 SEL2 SEL3 SEL4 1 0 OUT+ OUT- 1 IN+ IN0 1 0 1 0 PBC1 PBC2 PBC3 PBC4 The VSC7121 can be cascaded through the IN and OUT pins for arrays of disk drives greater than 4. For disk arrays with a noninteger multiple of 4 disk drives, the unused PBC’s can be hardwired to bypass with a external pulldown resistor. G52110-0, Rev. 4.1 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Data Sheet VSC7121 Table 1 is a truth table detailing the data flow through the VSC7121. Figure 1 shows a timing diagram of the data relationship in the VSC7121. There are no critical timing (setup, hold, or delay) parameters for the VSC7121 as this part routes the serial data encoded with the baud clock that is extracted by a Fibre Channel receiver. The primary AC parameter of importance is the jitter or data eye degradation inserted by the port bypass circuit. The design of the VSC7121 minimizes jitter accumulation by using fully differential circuits. This provides for symmetric rise and fall delays as well as noise rejection. Table 1: Truth Table SELECT STATE SEL1 L L L L H H DATA OUTPUTS SEL4 L H L L L H SEL2 L L L H L H SEL3 L L H L L H OUT IN SI4 SI3 SI2 SI1 SI4 SO4 IN IN SI3 SI2 SI1 SI3 SO3 IN IN IN SI2 SI1 SI2 SO2 IN IN IN IN SI1 SI1 SO1 IN IN IN IN IN IN Figure 1: Timing Waveforms IN+/LSI1+/LSI2+/LSI3+/LSI4+/- OUT+/LSO1+/LSO2+/LSO3+/LSO4+/T1 T2 Tjitter Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52110-0, Rev. 4.1 8/31/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7121 Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Figure 2: Disk Array Application 7120 VSC7121 QUAD PORT BYPASS CIRCUIT Dual SC or DB-9 Optics or Copper 7120 normal LRC Interlock FC-AL DISK DRIVE 0 1 TX E_STORE RX normal LRC Interlock FC-AL DISK DRIVE 0 1 TX E_STORE RX bypass 0 1 Pulldown for Bypass in Absense of Disk Drive normal 0 LRC Interlock FC-AL DISK DRIVE 1 TX E_STORE RX JBOD G52110-0, Rev. 4.1 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Table 2: AC Characteristics (Over recommended operating conditions). Parameters T1 T2 TSDR, TSDF Data Sheet VSC7121 Description Flow-Through Propagation Delay Rising Edge to Rising Edge Flow through Propagation Delay Falling Edge to Falling Edge Serial data rise and fall time Min. Max. 7.0 7.0 Units ns ns ps. Conditions Delay with all circuits bypassed. 75 Ohm Load Delay with all circuits bypassed. 75 Ohm load. 20% to 80%, tested on a sample basis — 300 Table 3: DC Characteristics (Over recommended operating conditions). Parameters Description Min Typ Max Units Conditions VIH(TTL) VIL(TTL) IIH(TTL) IIL(TTL) VDD IDD PD ∆VIN(DF) ∆VOUT(L_SO) ∆VOUT(OUT) Input HIGH voltage (SEL - TTL) Input LOW voltage (SEL - TTL) Input HIGH current (SEL- TTL) Input LOW current (SEL - TTL) Supply voltage Supply current Power Dissipation Receiver differential peak-to-peak Input Sensitivity, IN+/- & L_SIn+/L_SOn+/- output differential peakto-peak voltage swing OUT+/- output differential peak-topeak voltage swing 2.0 0 — — 3.10 — — — 50 — — — 5.5 0.8 500 -500 3.50 170 0.6 V V µA µA V mA W mVp-p mVp-p mVp-p IIH < 6.6 mA @ VIH = 5.5 V — VIN = 2.4 V VIN = 0.5 V VDD = 3.30V + 5% Outputs open, VDD = VDD max Outputs open, VDD = VDD max AC Coupled. Internally biased at VDD/2 50Ω to VDD – 2.0 V 50Ω to VDD – 2.0 V 300 1000 1200 — 2600 2200 2200 Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52110-0, Rev. 4.1 8/31/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7121 Absolute Maximum Ratings (1) Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays TTL Power Supply Voltage, (VDD) ..................................................................................................... 0.5V to +4V PECL DC Input Voltage, (VINP) ............................................................................................. -0.5V to VDD +0.5V TTL DC Input Voltage, (VINT) ..........................................................................................................-0.5V to 5.5V DC Voltage Applied to Outputs for High Output State, (VIN TTL) ........................................ -0.5V to VDD + 0.5V TTL Output Current (IOUT), (DC, Output High)........................................................................................... 50mA PECL Output Current, (IOUT), (DC, Output High) ......................................................................................-50mA Case Temperature Under Bias, (TC) ............................................................................................... -55° to +125oC Storage Temperature, (TSTG) ......................................................................................................... -65° to + 150oC Maximum Input ESD .................................................................................................................................. 1500 V Recommended Operating Conditions(2) Power Supply Voltage, (VDD) ...........................................................................................................+3.1V to 3.5V Ambient Operating Temperature Range, (T) .....................................................................................0°C to +70°C Notes: 1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. 2) Vitesse guarantees the functional and parametric operation of the part under “Recommended Operating Conditions: except where specifically noted in the AC and DC Parametric Tables G52110-0, Rev. 4.1 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Data Sheet VSC7121 Input Structures Two input structures exists in this part; TTL and High Speed, Differential Inputs. The TTL Inputs will interface with any TTL or 3.3V or 5V CMOS outputs. The High Speed, Differential Inputs are intended to be AC Coupled per the FC-PH specification. Being AC Coupled, the High Speed, Differential Input buffers are biased at VDD/2. Refer to Figure 3 for High Speed, Differential Input structure. Figure 3: High Speed, Differential Inputs (L_SIn/IN) VDD 3.3K +3.3 V INPUT+ 3.3K VDD/2 3.3K INPUT3.3K GND 0V Because the VSC7121 output buffers are PECL outputs referenced to VDD, the High Speed Differential outputs may not be direct coupled to the high speed differential inputs. One example of how to differentially cascade the two VSC7121 is shown in Figure 4. This circuit only applies if trace lengths are less than three inches. Figure 4: Cascading Two VSC7121 VDD VSC7121 191 191 .01 VSC7121 OUT+ OUT 124 124 .01 IN+ IN - 75 Ohm Board/Termination Example Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52110-0, Rev. 4.1 8/31/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7121 Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Figure 5: Pin Diagram L_SO2+ L_SO2- L_SO3+ L_SI2+ L_SO3- L_SI2- L_SI3+ 35 VDDP 43 VSS VDD L_SI1L_SI1+ VDDP L_SO1L_SO1+ VSS ININ+ VSS 11 13 9 7 5 3 1 41 39 VSS 37 VDDP L_SI333 VSS VDD 31 L_SO4+ L_SO4- 29 VDDP L_SI4+ VSC7121 27 L_SI4VDDP 25 OUTOUT+ 23 15 17 19 21 VSS SEL1 SEL2 SEL3 SEL4 VDD VDD VDD VSS VSS G52110-0, Rev. 4.1 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VSS VSS Page 7 VITESSE SEMICONDUCTOR CORPORATION Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Data Sheet VSC7121 Package Pin Description Table 4: Pin Description Pin # 9, 10 3, 4 40, 41 34, 35 27, 28 Name IN-, IN+ L_SI1-, L_SI1+ L_SI2-, L_SI2+ L_SI3-, L_SI3+ L_SI4-, L_SI4+ SEL1, SEL2, SEL3, SEL4 L_SO1-, L_SO1+ L_SO2-, L_SO2+ L_SO3-, L_SO3+ L_SO4-, L_SO4+ OUT-, OUT+ VDD VDDP VSS Description INPUT - Differential (Biased at VDD/2). Differential inputs from the downstream PBC port. INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC port 1. INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC port 2. INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC port 3. INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC port 4. INPUT - TTL. A LOW selects the “BYPASS” mode causing the output of the previous port to propagate to next port or OUT. When HIGH, this signal selects “NORMAL” mode which routes the previous port to the local output, L_SOn, and routes the local input, L_SIn, to the next port or OUT . OUTPUT - Differential (Biased at VDD-1.32V). Serial output driving the local receiver corresponding to PBC port 1. OUTPUT - Differential (Biased at VDD-1.32V) Serial output driving the local receiver corresponding to PBC port 2. OUTPUT - Differential (Biased at VDD-1.32V) Serial output driving the local receiver corresponding to PBC port 3. OUTPUT - Differential (Biased at VDD-1.32V) Serial output driving the local receiver corresponding to PBC port 4. OUTPUT - Differential (Biased at VDD - 1.32V) Serial output driving the upstream PBC port. Digital Logic Power Supply. 3.3V Supply for digital logic. High-Speed Output Power Supply. 3.3V Supply for PECL drivers. Ground. Ground pins are physically attached to the die mounting surface, and are an important part of the thermal path. For best thermal performance, all ground pins should be connected to a ground plane, using multiple vias if possible. 15-18 6, 7 43, 44 37, 38 30, 31 25, 24 2, 14, 20-21, 32 5, 26, 29 36, 42 1, 8, 11-13, 19, 22-23, 33, 39 Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52110-0, Rev. 4.1 8/31/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7121 Package Information Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays 44-Pin PQFP 10 x 10 mm F G 44 34 Item A 1 33 mm 2.45 2.00 0.35 13.20 10.00 13.20 10.00 0.88 0.80 Tol. MAX +0.10 +.05 +.25 +.10 +.25 +.10 +.15 / -.10 BASIC D E F I H G H I J 11 23 K 12 22 12o TYP D 12o TYP K 0.30 RAD. TYP. A 0.20 RAD. TYP. 0.25 MAX. NOTES: Drawing not to scale. Cavity up All units in mm unless otherwise noted. 0.17 MAX. 0.25 0 o- 8 o J1 E J 0.102 MAX. LEAD COPLANARITY G52110-0, Rev. 4.1 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Data Sheet VSC7121 Package Thermal Characteristics The VSC7121 is packaged into a standard plastic quad flatpack with an embedded, but unexposed thermal slug. This package adheres to industry standard EIAJ footprints for a 10x10mm body, 44 lead PQFP. The package construction is as shown in Figure 6. The 44 PQFP with embedded slug has the thermal properties shown in Table 5. This package allows the VSC7121 to operate with ambient temperatures up to 70oC in still air. Figure 6: Package Cross Reference Wire Bond Die Plastic Molding Compound Lead Insulator Copper Heat Spreader Table 5: 44 PQFP Thermal Resistance Symbol θca-0 θca-100 θca-200 θca-400 θca-600 Description Thermal resistance from case to ambient, still air Thermal resistance from case to ambient, 100 LFPM air Thermal resistance from case to ambient, 200 LFPM air Thermal resistance from case to ambient, 400 LFPM air Thermal resistance from case to ambient, 600 LFPM air Value 50 43 39 36 34 Units oC/W oC/W oC/W oC/W oC/W Moisture Sensitivity Level This device is rated with a moisture sensitivity level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures. Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52110-0, Rev. 4.1 8/31/98 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7121 Ordering Information Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays The order number for this product is formed by a combination of the device number and package type. VSC71XX QM Device Type VSC7121 - 1.0625 Gbits/sec Port Bypass Circuit Package Type QM: 44 Pin PQFP, 10x10mm Body Marking Information The package is marked with three lines of text as shown below (QM Package): Pin Identifier VITESSE VSC7121QM Package Suffix Part Number ####AAAA Date Code Lot Tracking Code Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore, the reader is cautioned to confirm that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52110-0, Rev. 4.1 8/31/98 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays Data Sheet VSC7121 Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52110-0, Rev. 4.1 8/31/98