VSC8021

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8021/VSC8022 Features • Serial Data Rates up to 2.5Gb/s • Parallel Data Rates up to 312.5Mb/s • ECL 100K Compatible Parallel Data I/Os • Divide-by-8 Clock for Synchronization of Parallel Data to Interfacing Chips • SONET Frame Recovery Circuitry (VSC8022) • Compatible with STS-3 to STS-48 SONET Applications 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset • Differential or Single-Ended Inputs and Outputs • Low Power Dissipation: 2.3W (Typ Per Chip) • Standard ECL Power Supplies: VEE = -5.2V, VTT = -2.0V • Available in Commercial (0°C to +70°C) or Industrial (-40°C to +85°C) Temperature Ranges • Proven E/D Mode GaAs Technology • 52-Pin Leaded Ceramic Chip Carrier Functional Description The VSC8021 and VSC8022 are high-speed SONET interface devices capable of handling serial data at rates up to 2.5Gb/s. These devices can be used for STS-3 through STS-48 SONET applications. These products are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process which achieves high-speed and low power dissipation. These products are packaged in a ceramic 52-pin leaded ceramic chip carrier. VSC8021 The VSC8021 contains an 8:1 multiplexer and a self-positioning timer. The 8:1 multiplexer accepts 8 parallel differential ECL data inputs (D1-D8, D1N-D8N) at rates up to 312.5Mb/s and multiplexes them into a serial differential bit stream output (DO, DON) at rates up to 2.5Gb/s. The internal timing of the VSC8021 is built around the high-speed clock (up to 2.5GHz) delivered onto the chip through a differential input (CLKI, CLKIN). This signal is subsequently echoed at the high-speed differential output (CO, CON). The parallel data inputs are clocked to on-chip input registers with an externally supplied differential ECL input (BYCLK, BYCLKN) operating at the same rate as the data inputs. An internal byte clock, which is a divide-by-8 version of the high-speed clock, is used to transfer the data to a set of buffer registers. This internal byte clock is brought off chip at the ECL output CLK8, CLK8N. Internal circuitry monitors the internal and external byte clocks and generates an ERR signal if a timing violation is detected. This signal can be gated to the SYNC input which is edge sensitive high. An active SYNC input allows the VSC8021 timing to shift, positioning it properly against the external byte clock, CLK8, CLK8N. When a CLK8 timing switch is made, normal data flow will be invalid for 1 byte. There are two clock inputs, CLKI and BYCLK, going into the VSC8021. These two clocks serve as timing references for different parts of the VSC8021. The BYCLK is used to trigger the input registers for the parallel data inputs, while the CLKI is used to trigger the high-speed serial output register as well as some of the timing circuitry for the parallel to serial conversion. Furthermore, in order to make this part easy to use, the user is not required to assume a known phase relationship between CLKI and the BYCLK. G52028-0, Rev 4.1 05/25/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset Data Sheet VSC8021/VSC8022 An internal Phase Detector and Phase Adjust Circuit are used to facilitate the two asynchronous circuits to work with each other. The Phase Detector and the Phase Adjust Circuit work together to adjust the internal clock CLK8 to make sure the set up and hold conditions are met for the internal registers. CLK8 is derived from CLKI and the RCLK is a non-phase varying byte clock output. The edge sensitive SYNC signal is simply the control signal that enables the Phase Detector circuitry. As a summary, the CLKI is the high-speed clock input. The BYCLK is the external byte clock. The CLK8 is the internal byte clock derived from CLKI, phase-adjusted if SYNC is enabled. The RCLK is a non-phaseadjusted divided-by-8 clock generated from CLKI. The phase of RCLK, RCLKN is not affected by the selfadjusting circuitry, therefore it can be used as a system reference clock. RCLK, RCLKN can be used by the system designer to generate BYCLK, BYCLKN. The self-positioning timer and RCLK, RCLKN allow for the creation of very tight parallel data timing for the VSC8021. Figure 1: VSC8021 Block Diagram D1 D1N Parallel Data D8 D8N CLK8 SYNC Phase Adjust 8 8 8:1 Multiplexer DO DON Serial Data Output CLK8N Phase Adjustable Byte Clock Output Byte Clock Inputs BYCLK BYCLKN Timing Generator RCLK RCLKN CO CON ERR Independent Byte Clock Output High Speed Clock Inputs CLKI CLKIN High Speed Clock Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52028-0, Rev 4.1 05/25/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8021/VSC8022 VSC8022 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset The VSC8022 contains both a 1:8 demultiplexer and SONET frame recovery circuitry. The 1:8 demultiplexer accepts a serial data input (DI, DIN) at rates up to 2.5Gb/s and converts it into 8 parallel differential ECL data outputs (D1-D8, D1N-D8N) at rates up to 312.5Mb/s. Valid parallel data outputs are indicated by the divide by 8 differential clock outputs BYCKO, BYCKON. The VSC8022 also contains a SONET frame recovery circuit. The frame recovery circuits are enabled by a falling edge on the OOFN ECL input when the FDIS input is low. Once enabled, the frame recovery circuit starts looking for the SONET framing sequence. Once the frame is detected, the word boundary is realigned, a confirmation signal is sent off-chip through the FP ECL output and the frame recovery circuits are disabled. While the frame aligner is hunting for the frame, BYCKO, BYCKON and parallel data are invalid. Figure 2: VSC8022 Block Diagram D1 D1N Serial Data In DI DIN 1:8 Demultiplexer D8 D8N Parallel Data Outputs High Speed Clock Inputs CLKI CLKIN Timing Generator Frame Recovery Disable — FDIS Frame Recovery Clock — OOFN SONET Frame Detection & Recovery FP — Frame Detection Signal BYCKO BYCKON Byte Clock Out Frame recovery circuits are disabled by frame detection (resulting in FP) or by a falling edge on the OOFN input while FDIS is high. G52028-0, Rev 4.1 05/25/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset Data Sheet VSC8021/VSC8022 VSC8021 Multiplexer AC Characteristics (Over recommended operating conditions) Figure 3: VSC8021 Multiplexer Waveforms tC CLKI (1), CLKIN High speed differential clock input tD BYCLK (BYCLKN) Byte clock input (1) CLK8 (2) Phase adjustable ÷8 output tDSU tDH tBCLK8 D1-D8, D1N-D8N Parallel differential data inputs VALID DATA(1) VALID DATA(2) tCMD CO, CON High speed differential clock outputs DO,DON High speed differential data outputs D01 D02 D03 D04 D05 D06 D07 D08 SYNC CLK8 adjustment input NOTES: (1) Negative edge is active edge. (2) BYCLK/CLK8 timing required when SYNC not connected to ERR. CLKI (CLKIN) period x 8 = BYCLK (BYCLKN) period. = Don’t care. Serialized Byte 1 Table 1: VSC8021 Multiplexer AC Characteristics (over recommended operating conditions) Parameter tC tD tDSU tDH tCMD tBCLK8 Jitter (p-p) Clock period(1) BYTE clock period (tD = tC x 8) Parallel data set-up time Data hold time High-speed clock output (CO, CON) timing, falling edge of CO to muxed data output, (DO, DON) timing Byte clock to CLK8 timing(2) CLKI, CLKIN to DO, DON (max-min), (HI to LO), same part, same pin at constant conditions Description Min 400 3.2 0.6 1.4 220 0.5 Typ Max Units ps ns ns ns Conditions 350 1.0