VSC8122QP

VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8122 Features • Multi-Rate OC-3, OC-12, OC-24, OC-48 Clock and Data Recovery • Supports Gigabit Ethernet • Differential Back Terminated I/O • Maintains Clock Output in the Absence of Data • Selectable Reference Clock Multi-Rate SONET/SDH Clock and Data Recovery IC • Loss of Lock Indicator • Exceeds SONET/SDH Requirements for Jitter Tolerance, Jitter Transfer and Jitter Generation. • 3.3V Supply Operation • 1W Typical Power • 64-pin , 10x10mm PQFP Packaging General Description The VSC8122 is a single-chip clock recovery IC for use in SONET OC-48, OC-24, OC-12, OC-3, or Gigabit Ethernet systems operating at their respective 2.48832Gb/s, 1.24416Gb/s, 622.08Mbps, 155.52Mbps, or 1.25Gbps data rates. The VSC8122 complies with SONET jitter tolerance, jitter transfer and jitter generation specifications. Alarm functions support typical telecom system applications. The Loss of Lock (LOL) output indicates when the device goes out of lock, which would most often occur in the event of a loss of valid data. The NOREF output flags when the reference input to the VSC8122 either is removed, or goes severely out of tolerance. VSC8122 Block Diagram FILTO+/- FILTI+/FSEL[1:0] DI+ DI- Ph/Freq. Detector Loop Filter VCO Divider CO+ CO- Data Retiming REFCK1 +/REFCK0 +/Lock Detect DO+ DOLOL NOREF Divider REF_INPUTSEL REF_SEL[1:0] G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Data Sheet VSC8122 Functional Description Data Input The data input receiver is internally terminated by a center-tapped resistor network. For differential input AC coupling, the network is terminated to the appropriate termination voltage, VTERM through a blocking capacitor, CAC to ground. The input requires a differential signal with a peak-to-peak voltage on both the true and complement of a minimum of 250mV. These inputs are required to be AC-coupled to allow use with a variety of limiting amplifiers. Figure 1: Input Termination (AC-Coupled) Limiting Amp Zo = 50Ω 0.1 µF VSC8122 DI+ 50Ω VTERM 50Ω Zo = 50Ω 0.1 µF CAC DI- High-Speed Clock and Data Outputs The VSC8122 high-speed clock and data outputs can be DC-terminated, 50 Ω t o V CC as indicated in Figure 2. Figure 2: High-Speed Clock and Data Output DC Termination VSC8122 VCC VCC 100Ω CO+ / DO+ Zo = 50Ω 50Ω CO- / DO- 100Ω VCC Zo = 50Ω 50Ω VCC Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52228-0, Rev 4.1 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8122 Multi-Rate SONET/SDH Clock and Data Recovery IC Outputs can also be AC terminated as shown in Figure 3. The output differential voltage and common-mode voltage range are specified in Table 4, High-Speed Inputs and Outputs. Figure 3: High-Speed Clock and Data Output AC Termination VSC8122 VCC VTERM 100Ω CO+ / DO+ 0.1µF Zo = 50Ω 50Ω CO- / DO- 100Ω VCC 0.1µF Zo = 50Ω 50Ω VTERM Clock Recovery The VSC8122 has a selectable input data rate. Two pins (FSEL0 and FSEL1) select the data rate to be provided to the VSC8122. Table 1: Input Data Rate Select Input Data Rate 2.48832Gb/s or 2.5Gb/s 1.24416Gb/s or 1.25Gb/s 622.08Mb/s or 625Mb/s 155.52Mb/s or 156.25Mb/s FSEL0 0 1 0 1 FSEL1 0 0 1 1 The incoming data is presented both to the clock recovery circuit and the data retiming circuit. When there is a phase error between the incoming data and the on-chip Voltage-Controlled Oscillator (VCO), the loop filter raises or lowers the control voltage of the VCO to null the phase difference. The lock detector monitors the frequency difference between the REFCK (optionally divided by a prescaler) and the recovered clock divided by 128. In the event of the loss of an input signal, or if the input is switching randomly, the VCO will move in one direction. At the time the VCO differs by more than 1MHz from the REFCK based 2.48832GHz rate, the lock detector will assert the LOL output. LOL is designed to be asserted from between 2.3µs and 100µs after the interruption of data. The VCO will continue to be frequency-locked at approximately 1MHz off of the REFCK based 2.48832GHz rate. When NRZ data is again presented at the data input, the phase detector will permit the VCO to lock to the incoming data. Hysteresis is provided which delays the deassertion of LOL until approximately 160µs following the restoration of valid data. The NOREF output will go high to indicate that there is no signal on the REFCK input, or that the REFCK is more than approximately 25% above or below the expected value. G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Data Sheet VSC8122 Two sets of reference frequencies for the VSC8122 are shown in Table 2. SONET reference clock frequencies are as indicated, with Gigabit Ethernet frequencies listed in parenthesis. The two different sets of reference clocks are needed since the reference clock for SONET and Gigabit Ethernet applications will be slightly different. Internally, the VSC8122 requires a 19.44MHz reference (or 19.53MHz reference for Gigabit Ethernet). The customer can select to provide either the 19.44MHz reference (or 19.53MHz reference for Gigabit Ethernet), or the 2x, 4x or 8x of that reference at 38.88MHz (39.06MHz), 77.76MHz (78.13MHz) or 155MHz (156.25MHz). The REF_SEL[1:0] inputs will program the internal divider as required to use the selected REFCK frequency. Two reference clock inputs are provided, REFCK1 and REFCK0, to allow “on-the-fly switching” between SONET and Gigabit Ethernet applications if desired. Since SONET and Gigabit Ethernet require different reference clock frequencies, the VSC8122 allows the user to toggle between the two reference clock frequencies (REFCK1 and REFCK0) to supply the appropriate input clock. REF_INPUTSEL is used to toggle between the two reference clock input frequencies; REF_INPUTSEL= “0” selects REFCK0 and REF_INPUTSEL= “1” selects REFCK1. Either reference clock input (REFCK1, REFCK0) can be used for SONET or Gigabit Ethernet reference frequencies. LVPECL levels are recommended for REFCK inputs (see Figure 4). If a reference clock is unused, it is recommended that one of its inputs be tied to VCC through a 5.1kΩ resistor, the other one to GND through a 5.1kΩ resistor. Figure 4: REFCK Input Levels LVPECL Level REFCK Inputs (recommended) NON- LVPECL Level REFCK Inputs REFCK0 / REFCK1 0.1µf VSC8122 50Ω VCC-2(1) REFCK0 / REFCK1 50Ω VTERM(1, 2) VSC8122 NOTES: (1) For differential REFCK input signals, 100Ω termination between true and complement REFCK signals can be substituted for the 50Ω to VTERM termination on each line. (2) With the input ac-coupled, VTERM can be to any power supply required for the upstream device. Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52228-0, Rev 4.1 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8122 Table 2: Reference Frequency Reference Frequency 19.44MHz (19.53MHz) 38.88MHz (39.06MHz) 77.76MHz (78.13MHz) 155.52MHz (156.25MHz) Multi-Rate SONET/SDH Clock and Data Recovery IC REF_SEL0 0 1 0 1 REF_SEL1 0 0 1 1 Loop Filter The Phase-Lock Loop (PLL) on the VSC8122 employs two external capacitors. The PLL design is fully differential, therefore the loop filter must also be fully differential. One capacitor should be connected between FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended capacitors are low-inductance 1.0µF (0603 or 0805) ceramic SMT X7R devices, 6.3 WVDC or greater, with tolerance of 10% or better. AC Characteristics (Over recommended operating conditions) Table 3: AC Characteristics Parameters tpd tr,tf tr,tf Jittergen Jittertol LBW Jitterpeak Description Center of output data eye from rising edge of CO+ DO± rise and fall times CO± rise and fall times Jitter Generation (12kHz20MHz) Jitter Tolerance Loop Bandwidth Jitter Peaking Min -75 — — — — — — Typ — — — — — — — Max +75 150 135 3.6 — 2.0 0.1 Units ps ps ps Conditions 20% to 80% into 50Ω load. 20% to 80% into 50Ω load. Measured at the HS data output for ps - rms jitter in the 12kHz - 20MHz band. Assume 1.2ps rms input data jitter. — MHz dB Exceeds SONET/SDH mask -3dB point of jitter transfer curve G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Figure 5: High-Speed Clock and Data Outputs Data Sheet VSC8122 80% Data Output 20% tR, tF tPD 80% Clock Output 20% tR tF Table 4: High-Speed Inputs and Outputs Parameters ∆VOD ∆VOC VCMO VDIFF RIN Description Data output voltage swing Clock output voltage swing Common-mode range (DO/CO) Serial input absolute voltage, single ended peak-to-peak swing (VIHVIL) for DI +/Input resistance between DI+ and VTERM or DI- and VTERM Min 600 500 2.6 250 43 Typ 900 700 — — — Max 1000 1000 3.2 1200 58 Units mV mV V mV Ω Conditions AC-coupled Table 5: PLL Parameters Parameters Description REF_CLK Duty Cycle REF_CLK Frequency Range VIH VIL REF_CLK Input High Voltage REF_CLK Input Low Voltage Min 45 -100 VCC1.165 VCC2.0 Typ — — — — Max 55 +100 VCC0.7 VCC1.475 Units % ppm V V Conditions Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52228-0, Rev 4.1 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8122 DC Characteristics (Over recommended operating conditions) Table 6: TTL Inputs and Outputs Parameters VOH VOL VIH VIL IIH IIL Multi-Rate SONET/SDH Clock and Data Recovery IC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Min 2.4 — 2.0 0 — — Typ — — — — 50 — Max — 0.5 3.47 0.8 500 500 Units V V V V µA µA Conditions IOH = -1.0mA IOL= 1.0mA VIN = 2.4V VIN = 0.5V Table 7: Power Supply Parameters VCC PD ICC Description Supply voltage Power dissipation Supply current Min 3.14 — — Typ 3.3 1.0 300 Max 3.47 1.2 347 Units V W mA Conditions 3.3V± 5% Outputs terminated Outputs terminated Absolute Maximum Ratings (1) Power Supply Voltage (VCC) .......................................................................................................... -0.5V to +3.8V DC Input Voltage (differential inputs) ....................................................................................-0.5V to VCC +0.5V DC Input Voltage (TTL inputs)....................................................................................................... -0.5V to +5.5V DC Output Voltage (TTL outputs) ......................................................................................... -0.5V to VCC + 0.5V Output Current (TTL outputs).................................................................................................................. +/-50mA Output Current (differential outputs) ........................................................................................................+/-50mA Case Temperature Under Bias...................................................................................................... -55oC to +125oC NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage, (VCC) ............................................................................................................. +3.3V+5% Operating Temperature Range ........................................................ 0oC Ambient to +85oC Case Temperature ESD Ratings Proper ESD procedures should be used when handling this product. The VSC8122 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Data Sheet VSC8122 Figure 6: Pin Diagram Package Pin Descriptions Top View REFSEL1 REFSEL0 VTERM VCC VCC VCC VCC VCC 63 FSEL0 FSEL1 REF_INPUTSEL N/C VEE_ANA VCC_ANA N/C N/C LOL NOREF VCC FILTAO FILTAI FILTAIN FILTAON VEE 15 17 19 13 11 9 7 5 3 1 61 59 57 55 53 51 49 VEE 47 REFCLK0+ REFCLK045 REFCLK+ REFCLK143 VEE VCC 41 VEE VCC 39 DO+ DO37 VCC VEE VITESSE VCC 35 VEE VEE VEE N/C N/C DI+ DI- VSC8122 21 23 25 27 29 31 VCC N/C 33 N/C VCC N/C N/C VCC VCC VCC VCC CO- CO+ VEE VEE N/C N/C N/C N/C Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com N/C G52228-0, Rev 4.1 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8122 Table 8: Pin Identifications Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Multi-Rate SONET/SDH Clock and Data Recovery IC Name FSEL0 FSEL1 REF_INPUTSEL NC VEE_ANA VCC_ANA NC NC LOL NOREF VCC FILTAO FILTAI FILTAIN FILTAON VEE VCC NC NC NC NC NC NC VCC VEE VCC COCO+ VCC VEE VCC NC NC NC I/O I I I — I I — — O O I I I I I I I — — — — — — I I I O O I I I — — — Level TTL TTL TTL — GND typ. +3.3V typ. — — TTL TTL +3.3V typ. — — — — GND typ. +3.3V typ. — — — — — — +3.3V typ. GND typ. +3.3V typ. HS HS +3.3V typ. GND typ. +3.3V typ. — — — Description Selectable input rate pin 0 Selectable input rate pin 1 Toggle between REFCK1 and REFCK0 No connect, leave unconnected(1) Negative power supply pins for analog parts of CMU Positive power supply pins for analog parts of CMU No connect, leave unconnected No connect, leave unconnected Loss of lock indication No reference output. Active HIGH for REFCK far off the expected frequency. Positive power supply Loop filter pin - connect via capacitor to FILTAI Loop filter pin - connect via capacitor to FILTAO Loop filter pin - connect via capacitor to FILTAON Loop filter pin - connect via capacitor to FILTAIN Negative power supply Positive power supply No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) Positive power supply Negative power supply Positive power supply High-speed clock output, complement High-speed clock output, true Positive power supply Negative power supply Positive power supply No connect, leave unconnected(1) No connect, leave unconnected(1) No connect, leave unconnected(1) G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Data Sheet VSC8122 Level +3.3V typ. GND typ. +3.3V typ. HS HS +3.3V typ. GND typ. +3.3V typ. GND typ. LVPECL LVPECL LCPECL LVPECL GND typ. +3.3V typ. — — +3.3V typ. GND typ. GND typ. +3.3V typ. HS HS +3.3V typ. 0V->3.3V GND typ. +3.3V typ. — +3.3V typ. — Name VCC VEE VCC DODO+ VCC VEE VCC VEE REFCK1REFCK1+ REFCK0REFCK0+ VEE VCC REF_SEL[0] REF_SEL[1] VCC VEE VEE VCC DIDI+ VCC VTERM VEE VCC NC VCC NC I/O I I I O O I I I I I I I I I I I I I I I I I I I I I I — I — Description Positive power supply Negative power supply Positive power supply High-speed data output, complement. High-speed data output, true Positive power supply Negative power supply Positive power supply Negative power supply Reference clock 1 input, complement Reference clock 1 input, true Reference clock 0 input, complement Reference clock 0 input, true GND power supply Positive power supply Reference clock rate select pin 0 Reference clock rate select pin 1 Positive power supply Negative power supply Negative power supply Positive power supply High-speed data input, complement High-speed data input, true Positive power supply High-speed data input termination voltage (may be connected to ground through a series AC-coupling capacitor) Negative power supply Positive power supply No connect, leave unconnected Positive power supply No connect, leave unconnected(1) NOTE: (1) No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either the positive or negative power supply rails may cause improper operation or failure of the device, or in extreme cases, cause permanent damage to the device. Page 10 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52228-0, Rev 4.1 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8122 Package Information 64-pin PQFP Package Drawing Multi-Rate SONET/SDH Clock and Data Recovery IC F G Item 64 49 48 1 10 mm 2.45 2.00 0.22 13.20 10.00 13.20 10.00 0.88 0.50 Tol. MAX +0.10 ±.05 ±.25 ±.10 ±.25 ±.10 ±.15 BASIC A D E F I H L G H I 16 33 J K 17 10o TYP 32 A D 100 TYP K 0.30 RAD. TYP. A 0.20 RAD. TYP . STANDOFF 0.25 MAX. 0.17 MAX. 0.25 J 0 o - 8o 0.102 MAX. LEAD COPLANARITY E NOTES: Drawing not to scale. Heat spreader up on 10mm package only. All units in mm unless otherwise noted. Heat spreader is not electrically connected. Package #: 101-XXX-X Issue #: 1 Package #: 101-XXX-X Issue #: 1 G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Data Sheet VSC8122 Package Thermal Considerations This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table: Table 9: Thermal Resistance Symbol θ-jc θ-ca Description Thermal resistance from junction to case. Thermal resistance from case to ambient with no airflow, including conduction through the leads. o C/W 1.5 31.5 Thermal Resistance With Airflow Shown in the table below is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance. Table 10: Thermal Resistance With Airflow Airflow 100 lfpm 200 lfpm 400 lfpm 600 lfpm θ-ca (oC/W) 25.8 23.0 19.3 17.0 Maximum Ambient Temperature Without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation: TA(MAX) = TC(MAX) - P(MAX)θCA where: θCA = Theta case to ambient at appropriate airflow TA(MAX) = Ambient Air temperature TC(MAX) = Case temperature (85oC for VSC8122) P(MAX) = Power (1.2W for VSC8122) Page 12 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52228-0, Rev 4.1 01/05/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8122 Table 11: Maximum Ambient Air Temperature Without Heatsink Airflow Still air 100 lfpm 200 lfpm 400 lfpm 600 lfpm Multi-Rate SONET/SDH Clock and Data Recovery IC TA(MAX) oC 47.2 54.0 57.4 61.8 64.6 Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow. Ordering Information The order number for this product is formed by a combination of the device number, and package type. VSC8122 QP Device Type VSC8122: OC-3/12/48 (STM-1/4/16) Clock and Data Recovery Package Style QP: 64-pin, 10 x 10 mm PQFP Notice Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52228-0, Rev 4.1 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION Multi-Rate SONET/SDH Clock and Data Recovery IC Data Sheet VSC8122 Page 14 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52228-0, Rev 4.1 01/05/01