VG4616322BQ-7

VIS Overview Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by 256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The VG4616321(2) provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, it features the write per bit and the masked block write functions. By having a programmable Mode register and special mode register, the system can choose the best suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, and when combined with special graphics functions result in a device particularly well suited to high performance graphics applications. Features • • • • • • • • • • • • • • • Fast access time from clock: 4.5/5/5.5ns Fast clock rate: 200/166/143 MHz Fully synchronous operation Internal pipelined architecture Dual internal banks(256K x 32-bit x 2-bank) Programmable Mode and Special Mode registers - CAS Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst Read Single Write - Load Color or Mask register Burst stop function Individual byte controlled by DQM0-3 Block write and write-per-bit capability Auto Refresh and Self Refresh 2048 refresh cycles/32ms Single + 3.3V ± 0.3V power supply Input Reference Voltage : Vref = 1.5V ± 0.2V Interface: LVTTL and SSTL_3 JEDEC 100-pin Plastic QFP package Document:1G5-0145 Rev.1 Page 1 VIS DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS BS A8 1 2 3 4 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Key Specifications VG4616321/VG4616322 tCK tRAS tAC tRC Clock Cycle time(min.) Row Active time(min.) Access time from CLK(max.) Row Cycle time(min.) DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC VDD DQ0 DQ1 VSSQ DQ2 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 81 82 83 84 50 49 48 47 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQ28 VDDQ DQ27 DQ26 VSSQ DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC/Vref DQM3 DQM1 CLK CKE DSF NC A9 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 A7 A6 A5 A4 VSS NC NC NC NC NC NC NC NC NC NC VDD A3 A2 A1 A0 -5/6/7 5/6/7 ns 30/36/40 ns 4.5/5/5.5 ns 45/54/62 ns Document:1G5-0145 Rev.1 Page 2 VIS Block Diagram Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM CLOCK CLK BUFFER Row Decoder Column Decoder 1024 X 256 X 32 CELL ARRAY (BANK #0) Sense Amplifier CKE CS RAS CAS WE DSF COMMAND DECODER CONTROL SIGNAL GENERATOR DQM0~3 COLUMN COUNTER A9 DQs BUFFER COLOR REGISTER MODE REGISTER MASK REGISTER DQ0 | DQ31 A0 ~ ADDRESS BUFFER A8 BS SPECIAL MODE REGISTER Sense Amplifier REFRESH COUNTER R ow D ec oder Rev.1 1024 X 256 X 32 CELL ARRAY (BANK #1) Column Decoder Document:1G5-0145 Page 3 VIS Pin Num- Symbol ber 55 CLK Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Table 1 shows the details for pin number, symbol, type, and description. Table 1. Pin Description of VG4616321 Type Description Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and control the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When both banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes providing low standby power. Input Bank Select: BS defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. BS is also used to program the 10th bit of the Mode and Special Mode registers. Input Address Inputs: A0-A9 are sampled during the BankActivate command (row address A0-A9) and Read/Write command (column address A0-A7 with A9 defining Auto Precharge) to select one location out of the 256K available in the respective bank. During a Precharge command, A9 is sampled to determine if both banks are to be precharged (A9 = HIGH). The address inputs also provide the op-code during a Mode Register Set or Special Mode Register Set command. Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. Input Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and WE signals, and is latched at the positive edges of CLK. When RAS and CS are asserted “LOW” and CAS is asserted “HIGH”, either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted “HIGH” the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE is asserted "LOW", the Precharge command is selected and the bank designated by BS is switched to the idle state after precharge operation. Input Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS and WE signals, and it is latched at the positive edges of CLK. When RAS is held “HIGH” and CS is asserted “LOW”, the column access is started by asserting CAS “LOW”. Then, the Read or Write command is selected by asserting WE “LOW” or “HIGH”. Input Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals, and it is latched at the positive edges of CLK. The WE input is used to select the BankActivate or Precharge command and Read or Write command. Input Define Special Function: The DSF signal defines the operation commands in conjunction with the RAS and CAS and WE signals, and it is latched at the positive edges of CLK. The DSF input is used to select the masked write disable/enable command and block write command, and the Special Mode Register Set cycle. 54 CKE 29 BS 30-34, 47-51 A0-A9 28 CS 27 RAS 26 CAS 25 WE 53 DSF Document:1G5-0145 Rev.1 Page 4 VIS 23,56,24, 57 DQM0DQM3 97,98,100, 1,3,4,6,7, 60,61,63, 64,68,69, 71,72,9, 10,12,13, 17,18,20, 21,74,75, 77, 78,80, 81, 83, 84 30,36-45, 52,86-95 58 DQ0DQ31 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled HIGH during a write cycle. Output data is masked (two-clock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0. Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive Output edges of CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also serve as column/byte mask inputs during Block Writes. NC - No Connect: These pins should be left unconnected. NC/Vref -/Input No connect/Input Voltage Reference : It must be unconnected when the LVTTL interface is used in the SGRAM. It must be applied to Vref (1.5V) when the SSTL-3 interface is used in the SGRAM. VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. 2,8,14,22, 59,67,73, 79 5,11,19, 62,70,76, 82,99 15,35,65, 96 16,46,66, 85 VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VDD VSS Supply Power Supply: +3.3V Supply Ground ± 0.3V Document:1G5-0145 Rev.1 Page 5 VIS Operation Mode Command BankActivate & Masked Write Disable BankActivate & Masked Write Enable BankPrecharge PrechargeAll Write Block Write Command Write and AutoPrecharge Block Write and AutoPrecharge Read Read and AutoPrecharge Mode Register Set Special Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle(3) Idle(3) Any Any Active Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note(1), (2)) CKEn-1 CKEn DQM (7) BS H H H H (3) A9 V V L H L L H H L H L X X X X X X X A0-8 V V X X V V V V V V V V X X X X X X CS L L L L L L L L L L L L L L H L L H L RAS CAS L L L L H H H H H H L L H H X L L X H X X H X X H X X H H H H L L L L L L L L H H X L L X H X X H X X H X X WE H H L L L L L L H H L L H L X H H X H X X H X X H X X DSF L H L L L H L H L L L H X L X L L X X X X L X X L X X X X X X X X X X X X X X X X X H L H X X X X X X X X X X X X X X X X X X V V V X V V V V V V V X X X X X X X H H H H H H H H H H H H H L Active (3) Active (3) Active (3) Active (3) Active (3) Idle Idle (5) Any Active (4) Any Idle Idle Idle (SelfRefresh) Clock Suspend Mode Entry Power Down Mode Entry Active Any(6) Active Any (PowerDown) Active Active H H L L X X X X X X X X X H L Clock Suspend Mode Exit Power Down Mode Exit L L H H X X X X X X X X X H L Data Write/Output Enable Data Write/Output Disable H H X X L H X X X X X X X X Note: 1. V = Valid X = Don’t Care L = Low level H = High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. The Special Mode Register Set is also available in Row Active State. 6. Power Down Mode can not entry in the burst operation. When this command assert in the burst cycle, device state is clock suspend mode. 7. DQM0-3 Document:1G5-0145 Rev.1 Page 6 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Commands 1 BankActivate & Masked Write Disable command (RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”L”, BS = Bank, A0-A9 = Row Address) The BankActivate command activates the idle bank designated by the BS (Bank Select) signal. By latching the row address on A0 to A9 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD (min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the back-to-back activation of both banks. t RRD(min.) specifies the minimum time required between activating different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation. T0 T1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6 CLK Bank A Row Addr. RAS-CAS delay (tRCD) ADDRESS Bank A Col Addr. Bank A Row Addr. Bank A Row Addr. RAS-RAS delay time (tRRD) COMMAND Bank A Activate NOP NOP R/W A with AutoPrecharge Bank B Activate NOP NOP Bank A Activate RAS Cycle time (tRC) AutoPrecharge Begin : “H” or “L” BankActivate Command Cycle (Burst Length = n, CAS Latency = 3) 2 BankActivate & Masked Write Enable command (refer to the above figure) (RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”H”, BS = Bank, A0-A9 = Row Address) The BankActivate command activates the idle bank designated by BS signal. After this command is performed, the Write command and the Block Write command perform the masked write operation. In the masked write and the masked block write functions, the I/O mask data that was stored in the write mask register is used. BankPrecharge command (RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Bank, A9 = ”L”, A0-A8 = Don’t care) The BankPrecharge command precharges the bank designated by BS signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by t RAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still the idle state and ready to be activated again. PrechargeAll command (RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Don’t care, A9 = ”H”, A0-A8 = Don’t care) The PrechargeAll command precharges both banks simultaneously. Even if both banks are not in the active state, the PrechargeAll command can be issued. Both banks are then switched to the idle state. Read command (RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A9 = ”L”, A0-A7 = Column Address, A8 = Don’t care) 3 4 5 Document:1G5-0145 Rev.1 Page 7 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM The Read command is used to read burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS latency after the issue of Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs goes into high-impedance at the end of the burst, unless other command was initiated. The burst length, burst sequence, and CAS latency are determined by the mode register which is already prgrammed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP CAS Iatency = 1 tCK1,DQ’s CAS Iatency = 2 tCK2,DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 CAS Iatency = 3 tCK3,DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 Burst Read Operation (Burst Length = 4, CAS Latency = 1, 2, 3) The read data appears on the DQs subjects to the values on the DQM inputs two clocks early (i.e. DQM latency is two clocks for output buffers). A read burst without auto precharge function may be interrupted by a subsequent Read or Write/Block Write command to the same bank or the other active bank before the end of burst length. It may be interrupted by a BankPrecharge/PrechargeAll command to the same bank too. The interrupt comes from Read command can occur on any clock cycle following a previous Read command (refer to the following figure). T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP CAS Iatency = 1 tCK1,DQ’s CAS Iatency = 2 tCK2,DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS Iatency = 3 t CK3,DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Read Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3) The DQM inputs are used to avoid I/O contention on DQ pins when the interrupt comes from Write/Block Write command. The DQMs must be asserted (High) at least two clocks prior to the Write/Block Write command to suppress data-out on DQ pins. To guarantee DQ pins against the I/O contention, a single cycle with high-impedance on DQ pins must occur between the last read data and the Write/Block Write command (refer to the following three figures). If the data output of burst read occurs at the second clock of burst write, the DQMs must be asserted (High) at least one clock prior to the Write/Block Write command to avoid internal bus contention. Document:1G5-0145 Rev.1 Page 8 VIS T0 T1 T2 CLK DQM Preliminary T3 T4 T5 VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM T6 T7 T8 COMMAND NOP READ A NOP NOP NOP NOP WRITE B NOP NOP DQ’s DOUT A0 Must be Hi-Z before the Write Command DINB0 DINB1 DINB2 : “H” or “L” Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK 1 Clk Interval DQM COMMAND NOP NOP BANK A ACTIVATE NOP READ A WRITE A NOP NOP NOP CAS Iatency = 1 tCK1,DQ’s Must be Hi-Z before the Write Command DIN A0 DIN A1 DIN A2 DIN A3 CAS Iatency = 2 tCK2,DQ’s DIN A0 DIN A1 DIN A2 DIN A3 : “H” or “L” Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 1, 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP NOP READ A NOP NOP WRITE B NOP NOP NOP CAS Iatency = 1 tCK1,DQ’s DOUT A0 Must be Hi-Z before the Write Command DIN B0 DIN B1 DINB2 DIN B3 CAS Iatency = 2 tCK2,DQ’s DIN B0 DIN B1 DIN B2 DIN B3 : “H” or “L” Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 1, 2) A read burst without auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/PrechargeAll command is issued in different CAS latency. Document:1G5-0145 Rev.1 Page 9 VIS T0 T1 T2 CLK Bank Col A ADDRESS Preliminary T3 T4 T5 VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM T6 T7 T8 Bank(s) t RP Bank Row COMMAND READ A NOP NOP NOP Precharge NOP NOP Activate NOP CAS Iatency = 1 tCK1 ,DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 CAS Iatency = 2 tCK2 ,DQ’s CAS Iatency = 3 tCK3 ,DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Read to Precharge (CAS Latency = 1, 2, 3) 6 Read and AutoPrecharge command (RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A9 = ”H”, A0-A7 = Column Address, A8 = Don’t care) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command can not occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only read operation is performed in this command and the auto precharge function is ignored. Write command (RAS = ”H”, CAS = ”L”, WE = ”L”, DSF = “L”, BS = Bank, A9 = ”L”, A0-A7 = Column Address, A8 = Don’t care) The Write command is used to write burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remains high-impedance at the end of the burst, unless other command was initiated. The burst length and burst sequence are determined by the mode register which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 T1 T2 T3 T4 T5 T6 T7 T8 7 CLK COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP DQ0 - DQ3 DIN A0 DIN A1 DIN A2 DIN A3 don’t care The first data element and the write are registered on the same clock edge. Extra data is masked. Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3) Any Write performed to a row that was opened via an BankAcitvate & Masked Write Enable command is a masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte basis, and the Mask register, which masks on a per-bit basis. This is shown in the following block diagram. Document:1G5-0145 Rev.1 Page 10 VIS DSF BankActivate command D CK Q Preliminary DQM0 VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM DRAM CELL DQ7 MR7 DQ6 MR6 DQ5 MR5 DQ4 MR4 DQ3 MR3 DQ2 MR2 DQ1 MR1 DQ0 MR0 0 = Masked 1 = Not Masked Note: Only lower byte is shown. The operation is identical for other bytes. Write Per Bit (I/O Mask) Block Diagram A write burst without auto precharge function may be interrupted by a subsequent Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of burst length. The interrupt comes from Write/Block Write command can occur on any clock cycle following the previous Write command ( refer to the following figure). T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 COMMAND NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP 1 Clk Interval DQ’s DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge at which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored, and writes will not be executed. Document:1G5-0145 Rev.1 Page 11 VIS T0 T1 T2 Preliminary T3 T4 T5 T6 VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM T7 T8 CLK COMMAND NOP NOP WRITE A READ B NOP NOP NOP NOP NOP CAS latency = 1 tCK1,DQ’s DIN A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS latency = 2 tCK2,DQ’s CAS latency = 3 tCK3,DQ’s DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 DIN A0 don’t care don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from DQ’ s at least one clock cycle before the Read data appears on the outputs to avoid data contention Input data for the write is masked Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without auto precharge function should be issued m cycles after the clock edge at which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 CLK DQM tRP NOP COMMAND WRITE Precharge NOP NOP Activate NOP ADDRESS BANK COLn tWR DIN n DIN n+1 BANK (S) ROW DQ :don’t care Write to Precharge When Burst-Read and Single-Write mode is selected , the write burst length is 1 regardless of the read burst length (refer to Figures 21 and 22 in Timing Waveforms). 8 Block Write command (RAS = “H” , CAS = “L” , WE = “L”, DSF = “H” , BS =Bank , A9 = “L” , A3-A7 = Column Address, DQ0-DQ31 = Column Mask) The block writes are non-burst accesses that write to eight column locations simultaneously. A single data value, which was previously loaded in the Color register, is written to the block of eight consecutive column locations addressed by inputs A3-A7. The information on the DQs which is registered coincident with the Block Write command is used to mask specific column/byte combinations within the block . The mapping of the DQ inputs to the column/byte combinations is shown in following table. Document:1G5-0145 Rev.1 Page 12 VIS DQ inputs DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Column Address A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0~7 0~7 0~7 0~7 0~7 0~7 0~7 0~7 8~15 8~15 8~15 8~15 8~15 8~15 8~15 8~15 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM DQ Planes Controlled DQ Inputs DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Column Address A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DQ Planes Controlled 16~23 16~23 16~23 16~23 16~23 16~23 16~23 16~23 24~31 24~31 24~31 24~31 24~31 24~31 24~31 24~31 The overall Block Write mask consists of a combination of the DQM inputs, the Mask register, and the column/byte mask information, as shown in the following diagram. The DQM and Mask register masking operates as for normal Write command, with the exception that the mask information is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is written only if a ”0” was registered for the corresponding DQM input, a ”1” was registered for the corresponding DQ signal, and the corresponding bit in the Mask register is ”1”. A block write access requires a time period of tBWC to execute, so in general, there should be m NOP cycles, m equals (tBWC-tCK) /tCK rounded up to the next whole number, after the Block Write command. However, BankActivate or BankPrecharge commands to the other bank are allowed. When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank, t BPL must be met. Document:1G5-0145 Rev.1 Page 13 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Block of Columns (selected by A3-A7 registered coincident with Block Write command) Row in Bank (selected by A0-A9, and BS registered coincident with BankActivate Command) Column Mask on the DQ inputs (registered coincident with Block Write Command DSF D Q BankActivate CK command DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMO Mask Register (previously loaded from corresponding DQ inputs MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR7 Note: Only lower byte is shown. The operation is identical for other bytes. Block-Write Masking Block Diagram Document:1G5-0145 Rev.1 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 Page 14 VIS 9 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Write and AutoPrecharge command (refer to the following figure) (RAS = “H” , CAS = “L” , WE = “L” , DSF=”L” , BS = Bank, A9 = ”H”, A0-A7 = Column Address, A8 = Don’t care) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {burst length + tWR + tRP(min.)}. At full-page burst, only write operation is performed in this command and the auto precharge function is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND Bank A Activate Write A NOP NOP Auto Precharge NOP NOP tDAL NOP NOP NOP * CAS latency = 1 tck1,DQ’s DIN A0 DIN A1 tDAL CAS latency = 2 tck2,DQ’s * DIN A0 DIN A1 tDAL CAS latency = 3 tck3,DQ’s DIN A0 DIN A1 * tDAL = tWR + tRP * Begin AutoPrecharge Bank can be reactivated at completion of tDAL Burst Write with Auto-Precharge (Burst Length = 2, CAS Latency = 1, 2, 3) 10 Block Write and AutoPrecharge command (RAS = “H” , CAS = “L” , WE = “H”, DSF = “H” , BS = Bank , A9 = “H” , A3-A7 = Column Address, A8 = Don’t care DQ0-DQ31 = Column Mask) The Block Write and AutoPrecharge command performs the precharge operation automatically after the block write operation. Once this command is given, any subsequent command can not occur within a time delay of {tBPL + tRP (min.)}. 11 Mode Register Set command (RAS = “L” , CAS = ”L”, WE = “L” , DSF = “L” , BS , A0-A9 = Register Data) The mode register stores the data for controlling the various operating modes of SGRAM. The Mode Register Set command programs the values of CAS latency. Addressing Mode and Burst Length in the Mode register to make SGRAM useful for variety of different applications. The default values of the Mode Register after power-up are undefined, therefore this command must be issued at the power-up sequence. The state of pins A0-A9 and BS in the same cycle is the data written in the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure ). The mode register contents can be changed using the same command and the clock cycle requirements during operation as long as both banks are in the idle state. Document:1G5-0145 Rev.1 Page 15 VIS T0 T1 T2 CLK tCK2 CKE Preliminary T3 T4 T5 T6 VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM T7 T8 T9 T10 Clock min CS RAS CAS WE DSF BS A9 Address key A0-A8 DQM DQ Hi-Z tRP PrechargeAll Mode Register Set Command Any Command Mode Register Set Cycle (CAS Latency = 1, 2, 3) The mode register is divided into various fields depending on functionality. • Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 1, 2, 4, 8, or full page. A2 0 0 0 0 1 1 1 1 Document:1G5-0145 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length 1 2 4 8 Reserved Reserved Reserved Full Page Rev.1 Page 16 VIS • A3 0 1 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential Mode supports burst length of 1, 2, 4, 8, or full page. But, lnterleave Mode only supports burst length of 4 and 8. Addressing Mode Sequential Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. When the value of column address, (n+m), in the table is larger than 255, only the least significant 8 bits are effective. Data n Column Address 0 n 1 n+1 2 n+2 3 n+3 4 n+4 5 n+5 6 n+6 7 n+7 255 n+255 256 n 257 n+1 - 2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in following table. Data n Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 • A7 A7 A7 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A6 A6 A6 Column Address A5 A5 A5 A5 A5 A5 A5 A5 A4 A4 A4 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 A0 A0 4 Words 8 Words Burst Length CAS Latency Field (A6 ~ A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum value of CAS Latency depends on the frequency of CLK. And this value satisfying the following formula must be programmed into this field. tCAC (min) ≤ CAS Latency x tCK A6 0 0 0 0 1 A5 0 0 1 1 X A4 0 1 0 1 X CAS Latency Reserved 1 clock 2 clocks 3 clocks Reserved Rev.1 Page 17 Document:1G5-0145 VIS • Mode field (A8~A7) A8 0 0 1 A7 0 1 x Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM A7 and A8 must be programmed to “00” in normal operation. Test Mode normal mode Vendor Use Only Vendor Use Only • Single Write Mode (A9) This bit is used to select the write mode. When the A9 bit is “0”, Burst Read and Burst Write mode is selected. When the A9 bit is ”1”, Burst Read and Single Write mode is Selected. A9 0 1 Single Write Mode Burst Read and Burst Write Burst Read and Single Write 12 Special Mode Register Set command (RAS = ”L”, CAS = ”L”, WE = ”L”, DSF = ”H”, BS, A0-A9 = Register Data) The special mode register is used to load the Color and Mask registers, which are used in Block Write and masked Write cycles. The control information being written to the Special Mode register is applied to the address inputs and the data to be written to either the Color register or the Mask register is applied to the DQs. When A6 is “high” during a Special Mode Register Set cycle, the Color register will be loaded with the data on the DQs. Similarly, when A5 is “high” during a Special Mode Register Set cycle, the Mask register will be loaded with the data on the DQs. A6 = A5 = 1 in the Special Mode Register Set cycle is illegal. Functions Leave Unchanged Load Mask Register Load Color Register Illegal BS X X X X A9~A7 X X X X A6 0 0 1 1 A5 0 1 0 1 A4~A0 X X X X One clock cycle is required to complete the write in the Special Mode register. This command can be issued at the active state. As in write operation, this command accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. 13 No-Operation command (RAS = ”H”, CAS = ”H”, WE = ”H”) The No-Operation command is used to perform a NOP to SGRAM which is selected (CS is Low). This prevents unwanted commands from being registered during idle or wait states. Burst Stop command (RAS = ”H”, CAS = ”H”, WE = ”L’, DSF = ”L”) Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without auto precharge function. The terminated read burst ends after a delay equal to the CAS latency (refer to the following figure). The termination of a write burst is shown in the following figure. 14 Document:1G5-0145 Rev.1 Page 18 VIS T0 T1 T2 CLK COMMAND READ A NOP NOP CAS Iatency = 1 tCK1,DQ’s CAS Iatency = 2 tCK2,DQ’s DOUT A0 DOUT A1 Preliminary T3 T4 T5 T6 VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM T7 T8 NOP Burst Stop NOP NOP NOP NOP DOUT A2 DOUT A3 The burst ends after a delay equal to the CAS latency. DOUT A0 DOUT A1 DOUT A2 DOUT A3 CAS Iatency = 3 tCK3,DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 Termination of a Burst Write Operation (Burst Length > 4, CAS Latency = 1, 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK NOP NOP NOP Burst Stop NOP NOP NOP COMMAND WRITE A NOP CAS latency = 1, 2, 3 DQ’s DIN A0 DIN A1 DIN A2 don’t care Input data for the Write is masked. Termination of a Burst Write Operation (Burst Length = X, CAS Latency = 1, 2, 3) 15 Device Deselect command (CS = ”H”) The Device Deselect command disables the command decoder so that the RAS, CAS , WE and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms) (RAS = ”L”, CAS = ”L”, WE = ”H”, DSF = ”L”, CKE = ”H”, BS, A0-A9 = Don’t care) The AutoRefresh command is used during normal operation of the SGRAM and is analagous to CAS-before-RAS(CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “don’t care” during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 2048 times within 32ms. The time required to complete the auto refresh operation is specified by tRP(min.). To provide the AutoRefresh command, both banks need to be in the idle state and the device is not in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operations is completed. The precharge time requirement, tRP(min.). must be met befor successive auto refresh operations are performed. SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms) (RAS = ”L”, CAS = ”L”, WE = ”H”, DSF = ”L”, CKE = ”L”, BS, A0-A9 = Don’t care) The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SGRAM becomes “don’t care” with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power comsumption. The SGRAM may remain in SelfRefresh mode for an indefinite period. Once the SGRAM enters the SelfRefresh mode , tRAS (min.) is required before exit from SelfRefresh mode. The SelfRefresh mode is exited by restarting the external clock and then asserting high on CKE(SelfRefresh Exit command). 16 17 Document:1G5-0145 Rev.1 Page 19 VIS 18 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms) (CKE = ”H”, CS = ”H” or CKE = ”H”, RAS = ”H”, CAS = ”H”, WE = ”H”) The command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min), because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 1024 auto refresh cycles should be completed just prior to entering, and just after exiting the SelfRefresh mode. Clock Suspend Mode Entry/PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing Waveforms) (CKE = ”L”) When SGRAM operating the burst cycle, the internal CLK is suspended (masked) from the subsequent cycle by issuing this command (asserting CKE ”low”). The device operation is held intact while CLK is suspended. On the other hand, when both banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (16ms) since the command does not perform any refresh operations. Clock Suspend Mode Exit/PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing Waveforms) (CKE = ”H”) When the internal CLK has been suspended, the operation of the internal CLK is resumed from the subsequent cycle by providing this command (asserting CKE “high”). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required when the device exit from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. Data Write/Output Enable, Data Mask/Output Disable command (DQM = ”L”, ”H”) During a write cycle, the DQM signal functions as Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the control of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31, DQM masks the DQ’s by a byte regardless that the corresponding DQ’s are in a state of write-per-bit masking or pixel masking. the byte control. The each DQM0-3 corresponds to DQ0-7, DQ8-15, DQ16-23, DQ24-31. 19 20 21 Document:1G5-0145 Rev.1 Page 20 VIS VDD, VDDQ T OPR TSTG TSOLDER PD IOUT Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Absolute Maximum Rating Symbol Item VIN, VOUT Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature(10s) Power Dissipation Short Circuit Output Current Rating -0.3~VDD + 0.3 -0.3~4.6 0~70 -55~150 260 1 50 Unit V V °C °C °C W mA Note 1 1 1 1 1 1 1 Recommended D.C. Operating Conditions (Ta = 0~70°C) Symbol Parameter Min. VDD Power Supply Voltage 3.0 VDDQ VIH VIL Vref VIH VIL VTT Power Supply Voltage (for I/O Buffer) LVTTL Input High Voltage LVTTL Input LOW Voltage Input Reference Voltage SSTL Input High voltage SSTL Input Low Voltage SSTK Teruination Voltage 3.0 2.0 -0.3 1.25 VREF+0.2 -0.3 VREF-0.1 Typ. 3.3 3.3 1.5 V Max. 3.6 3.6 VDD+ 0.3 0.8 1.75 VDDQ+0.3 VREF+0.2 VREF+0.1 Unit V V V V V V V V Note 2 2 2 2 2 2 2 2 Note : the peak to peak AC noise on Vref may not exceed 2%. VREF (DC). Vtt of transmitting device must track VREF of receiving device. Typically the value of VREF must be about 0.45 * VDDQ of the transmitting device and VREF track Variations in VDDQ . Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C) Symbol CI CI/O Parameter Input Capacitance Input/Output Capacitance Min. Max. 5 7 Unit pF pF Note: These parameters are periodically sampled and are not 100% tested. Document:1G5-0145 Rev.1 Page 21 VIS Description/test condition Operating Current t ≥t , Outputs Open RC RC ( min ) Address changed once during tCK(min). Burst Length = 1 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0 ~ 70¢J) -5 -6 -7 Symbol Min. Max. Min. Max. Min. Max. IDD1 190 170 150 Unit Note 3,4 1 bank operation Precharge Standby Current in non-power down mode tCK = tCK(min), CS ≥ VI H (min), CKE ≥ V I H (min) Input signals are changed once during 30ns. Precharge Standby Current in non-power down mode tCK = ∞ , C KE ≥ V I H (min), C LK Input signals are stable Precharge Standby Current in power down mode tCK = tCK(min), CKE ≤ V I L (max) Precharge Standby Current in power down mode tCK = ∞ , CKE ≤ V I L (max), C LK IDD2N 35 35 35 3 ≤ VIL (max) IDD2NS 15 15 15 mA IDD2P 2.0 2.0 2.0 3 ≤ VIL (max) IDD2PS 2.0 2.0 2.0 Active Standby Current in non power down mode CKE ≥ V I H (min), tCK = tCK(min) Active Standby Current in power down mode CKE ≤ V I L (max), tCK = tCK(min), CS ≥ VIH(min) Operating Current (Page Burst, and All Bank activated) tCCD = tCCD(min), Outputs Open, Multi-bank interleave, gapless data Refresh Current t RC ≥ tRC (min) Self Refresh Current CKE IDD3P IDD3N IDD4 4 30 220 4 30 200 4 30 170 3 4,5 IDD5 IDD6 IDD7 190 170 140 3 ≤ 0.2V 1 250 1 230 1 190 Operating Current (Block Write) tCK = tCK(min), Outputs Open, tBWC = tBWC(min) Parameter IIL IOL ( 0V ≤ V ≤V Description Min. -5 Max. 5 Unit µA µA Note IN DD Input Leakage Current All other pins not under test = OV) Output Leakage Current Output disable, ( 0V ≤ V ) ≤V OUT DDQ LVTTL Output ”H” Level Voltage (lOUT = -2mA) LVTTL Output ”L” Level Voltage (lOUT = 2mA) SSTL Output ”H” Level Voltage (lOUT = -16mA) SSTL Output ”L” Level Voltage (lOUT = 16mA) -5 5 VOH VOL VOH VOL 2.4 VTT+0.8 - 0.4 VTT+0.8 V V V V Document:1G5-0145 Rev.1 Page 22 VIS symbol tRC tRCD tRP tRRD tRAS tWR tCK1 tCK2 tCK3 tCH tCL tAC1 tAC2 tAC3 tT tCCD tOH tLZ tHZ1 tHZ2 tHZ3 tIS tIH tSRX tPDE tRSC tBWC tDAL2 Data-in to ACT Command tDAL3 tBPL tREF Data output high impedance Access time from CLK (positive edge) Clock high time Clock low time Clock cycle time A.C. Parameter Row cycle time RAS to CAS delay Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0~70°C) (Note: 6, 7, 8, 9, 10) *** CL is CAS Latency. -5 Min. 45 15 15 10 Max. Min. 54 18 18 12 -6 Max. Min. 62 20 20 14 ns -7 Max. unit Precharge to refresh/row activate command Row activate to row activate delay Row activate to precharge time Write recovery time CL* = 1 30 100,000 36 100,000 40 100,000 1 14 7 5 1.5 1.5 1 16 8 6 2 2 11 5 4.5 0.5 1 2 2 10 0.5 1 2.5 2 5 5 5 3 3 3 1 1 1 4 2 1 1clk+ tRP 1clk+ tRP 1 32 32 5 5 5 13 5 5 10 0.5 1 2.5 2 3 3 3 1.5 1 1 5 2 1 1clk +tRP 1clk +tRP 1 32 CLK ms CLK ns CLK CLK 6 6 5 ns 1 18 9 7 2.5 2.5 15 6 5.5 10 CLK ns CLK CL* = 1 CL* = 2 CL* = 3 Transition time of CLK (Rise and Fall) CAS to CAS Delay time Data output hold time Data output low impedance CL = 1 CL = 2 CL = 3 Data/Address/Control Input setup time Data/Address/Control Input hold time Minimum CKE ”High”for Self-Refresh exit Power Down Exit set-up time (Special) Mode Register Set Cycle time Block Write Cycle time (CL = 2) (CL = 3) Block Write to Precharge command Refresh time 3 3 3 1 1 1 3 2 1 1clk +tRP 1clk +tRP 1 Document:1G5-0145 Rev.1 Page 23 VIS Note: device. 2. All voltages are referenced to VSS. Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. Assume that there are only one read/write cycle during tRC (min). 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Assume minimum column address update cycle tCCD (min). 6. Power-up sequence is described in Note 11. 7. A.C. Test Conditions Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals 3.3V 1.2K Ω Output Output 1.4V / 1.4V Reference to the Under Output Load (B) 3.0V / 0.0V 1ns 1.4V 1.4V 50 Ω ZO=50Ω 30pF 30pF 870 Ω LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B) Document:1G5-0145 Rev.1 Page 24 VIS SSTL_3 Interface Reference Level of Output Signals (VREF) Output Load Input Signal Levels Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM 0.45*VDDQ Reference to the Under Output Load VREF + 0.4/VREF-0.4 1ns 0.45*VDDQ Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals(VREF) AC Test Load Circuits (for SSTL - 3 interface) : VDDQ VREF VDDQ 0.45 * VDDQ VTT = 0.45 * VDDQ RT2 = 50 Ohms VOUT RS = 25 Ohms Z = 50 Ohms RT1 = 50 Ohms CLOAD = 30 pF VIN Device Under Test VREF = 0.45 * VDD VTT = 0.45 * VDDQ VSS SSTL-3 A.C. Test Load 8. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns). 9. tOHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels. 10. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number) Document:1G5-0145 Rev.1 Page 25 VIS Clock period (tCK) 30ns 20ns 15ns 10ns 5ns tRC 45 2 3 3 5 9 tRP 15 1 1 1 2 3 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Latency relationship to frequency (Unit : clock cycles) -5 Version (Calculation with tCK = 5ns ~ 30ns) tRRD 10 1 1 1 1 2 tRAS 30 1 2 2 3 6 tRSC 10 1 1 1 1 2 tRCD 15 1 1 1 2 3 -6 Version (Calculation with tCK = 6ns ~ 30ns) Clock period (tCK) 30ns 20ns 15ns 10ns 6ns tRC 54 2 3 4 6 9 tRP 18 1 1 2 2 3 tRRD 12 1 1 1 2 2 tRAS 36 2 2 3 4 6 tRSC 12 1 1 1 2 2 tRCD 18 1 1 2 2 3 -7 Version (Calculation with tCK = 7ns ~ 30ns) Clock period (tCK) 30ns 20ns 15ns 10ns 7ns tRC 62 3 4 5 7 9 tRP 20 1 1 2 2 3 tRRD 12 1 1 1 2 2 tRAS 36 2 2 3 4 6 tRSC 14 1 1 1 2 2 tRCD 20 1 1 2 2 3 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ (simultaneously) when all input signals are held “NOP” state and CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time. 2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held “high” (VDD levels) to ensure DQ output to be in the high impedance. 3) Both banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Sequence of 4 and 5 may be changed. Document:1G5-0145 Rev.1 Page 26 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Timing Waveforms Figure 1. AC Parameters for Write Timing (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CH t CL t t IS IS IH t CK2 Begin Auto Precharge Begin Auto Precharge Bank A Bank B t IS t CS RAS CAS WE DSF BS t IH A9 tIS RAx RBx RAy RAz RBy A0 ~ A8 RBx CAx RBx CBx RAy CAy RAz RBy DQM tRCD tRC tDAL tIS tIH tWR Ay2 Ay3 tRP tRRD DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Activate Command Bank A Write with Write Activate Write with Activate Auto Precharge Command Auto Precharge Command Command Bank B Command Bank A Bank A Command Bank B Bank A Precharge Command Bank A Activate Command Bank A Activate Command Bank B Document:1G5-0145 Rev.1 Page 27 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 2. AC Parameters for Read Timing (Burst Length = 2, CAS Latency = 2) T0 CLK tCH tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 t CK2 t IS Begin Auto Precharge t IH Bank B CKE tIS t IH CS RAS CAS WE DSF BS tIH A9 tIS RAx RBx RAy A0 ~ A8 RAx CAx tRRD RBx CBx RAy tRAS tRC DQM tAC2 tLZ t AC2 tOH Ax0 t RCD tHZ tRP DQ Hi-Z Ax1 Bx0 Bx1 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A Document:1G5-0145 Rev.1 Page 28 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 3. Auto Refresh (CBR) (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 t RP t RC t RC RAx CAx DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Precharge All Auto Refresh Command Command Auto Refresh Command Read Activate Command Command Bank A Bank A Document:1G5-0145 Rev.1 Page 29 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 4. Power on Sequence and Auto Refresh (CBR) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High level is required Minimum of 8 Refresh cycles are required 2 Clock min. CS RAS CAS WE DSF BS A9 Address Key A0 ~ A8 DQM t RP t RC DQ Hi-Z Precharge All Command 1st Auto Refresh Inputs must be Command stable for 200 us 2nd Auto Refresh Command Mode Register Set Command Any Command Document:1G5-0145 Rev.1 Page 30 VIS T0 T1 T2 T3 T4 T5 CLK * Note 1 * Note 2 Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 5. Self Refresh Entry & Exit Cycle T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 t * Note 4 * Note 3 RC(min) * Note 7 CKE t IS SRX * Note 5 * Note 6 t t PDE CS RAS * Note 8 * Note 8 CAS BS A0 ~ A9 WE DSF DQM Hi-Z Self Refresh Enter Hi-Z DQ Self Refresh Exit Auto Refresh Note: To Enter SelfRefresh Mode 1. CS, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays “low”. Once the device enters SelfRefresh mode, Minimum tRAS is required before exit from SelfRefresh. Note: To Exit SelfRefresh Mode 4. System clock restart and be stable before returning CKE high. 5. Enable CKE and CKE should be set high for minimum time of tSRX. 6 .CS starts from high. 7. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 8. 1024 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh. Document:1G5-0145 Rev.1 Page 31 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 6.1 Clock Suspension During Burst Read (Using CKE) (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK1 CKE CS RAS CAS WE BS BS A9 RAx A0 ~ A8 RAx CAx DQM t HZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend Clock Suspend 1 Cycle 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Document:1G5-0145 Rev.1 Page 32 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 6.2 Clock Suspension During Burst Read (Using CKE) (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx DQM DQ Hi-Z t HZ Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enables = 1 clock Document:1G5-0145 Rev.1 Page 33 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 6.3 Clock Suspension During Burst Read (Using CKE) (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK3 CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx DQM DQ Hi-Z t HZ Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Document:1G5-0145 Rev.1 Page 34 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 7.1 Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK1 CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Clock Suspend Activate 1 Cycle Command Clock Suspend Bank A 2 Cycles Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Document:1G5-0145 Rev.1 Page 35 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 7.2 Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK2 CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Clock Suspend Activate 1 Cycle Command Clock Suspend Bank A 2 Cycles Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Document:1G5-0145 Rev.1 Page 36 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 7.3 Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK3 CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Document:1G5-0145 Rev.1 Page 37 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 8. Power Down Mode and Clock Mask (Burst Length = 4, CAS Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 t IS t PDE CKE Valid CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx DQM tHZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Power Down Mode Entry ACTIVE STANDBY Read Command Bank A Clock Mask Start Clock Mask End PRECHARGE Precharge STANDBY Command Bank A Power Down Mode Entry Power Down Mode Exit Any Command Power Down Mode Exit Document:1G5-0145 Rev.1 Page 38 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 9.1 Random Column Read (Page within same Bank) (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK1 CKE CS RAS CAS WE DSF BS A9 RAw RAz A0 ~ A8 RAw CAw CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 Activate Command Bank A Read Command Bank A Read Read Command Command Bank A Bank A Read Precharge Command Command Bank A Bank A Activate Command Bank A Document:1G5-0145 Rev.1 Page 39 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 9.2 Random Column Read (Page within same Bank) (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE DSF BS A9 RAw RAz A0 ~ A8 RAw CAW CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 Activate Command Bank A Read Command Bank A Read Read Command Command Bank A Bank A Precharge Bank A Command Command Command Bank A Bank A Activate Read Document:1G5-0145 Rev.1 Page 40 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 9.3 Random Column Read (Page within same Bank) (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE DSF BS A9 RAw RAz A0 ~ A8 RAw CAw CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Activate Command Bank A Read Command Bank A Read Command Command Read Precharge Bank A Bank A Command Bank A Activate Command Bank A Read Command Bank A Note: CKE to CLK disable/enable = 1 clock Document:1G5-0145 Rev.1 Page 41 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 10.1 Random Column Write (Page within same Bank) (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK1 CKE CS RAS CAS WE DSF BS A9 RBw RBz A0 ~ A8 RBw CBw CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 Activate Command Bank B Write Command Command Bank B Bank B Write Write Precharge Write Command Bank B Activate Command Bank B Command Bank B Command Bank B Document:1G5-0145 Rev.1 Page 42 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 10.2 Random Column Write (Page within same Bank) (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK2 CS RAS CAS WE DSF BS A9 RBw RBz A0 ~ A8 RBw CBy CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 Activate Command Bank B Write Write Bank B Write Bank B Command Bank B Command Command Command Command Command Bank B Bank B Bank B Precharge Activate Write Document:1G5-0145 Rev.1 Page 43 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 10.3 Random Column Write (Page within same Bank) (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK3 CS RAS CAS WE DSF BS A9 RBw RBz A0 ~ A8 RBw CBw CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 Activate Command Bank B Write Write Bank B Write Bank B Command Bank B Command Command Command Bank B Precharge Activate Command Bank B Write Command Bank B Document:1G5-0145 Rev.1 Page 44 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 11.1 Random Row Read (Interleaving Banks) (Burst Length = 8, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK1 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RBx RBx RBy A0 ~ A8 RBx CBx RAx CAx RBy CBy tRCD DQM tAC1 tRP DQ Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 By2 Activate Command Bank B Read Command Bank B Activate Precharge Command Command Bank B Bank A Read Activate Command Command Bank B Bank A Read Precharge Command Command Bank A Bank B Document:1G5-0145 Rev.1 Page 45 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 11.2 Random Row Read (lnterleaving Banks) (Burst Length = 8, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High t CK2 CS RAS CAS WE DSF BS A9 RBx RBx RBy A0 ~ A8 RBx CBx RAx CAx RBy CBy tRCD tAC2 tRP DQM DQ Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 Activate Read Command Command Bank B Bank B Activate Command Bank A Precharge Bank B Command Read Command Bank A Activate Command Bank B Read Command Bank B Document:1G5-0145 Rev.1 Page 46 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 11.3 Random Row Read (Interleaving Banks) (Burst Length = 8, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High t CK3 CS RAS CAS WE DSF BS A9 RBx RAx RBy A0 ~ A8 RBx CBx RAx CAx RBy CBy tRCD tAC3 tRP DQM DQ Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Activate Command Bank B Read Command Bank B Activate Command Bank A Read Precharge Command Command Bank B Bank A Activate Command Bank B Read Precharge Command Command Bank A Bank B Document:1G5-0145 Rev.1 Page 47 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 12.1 Random Row Read (Interleaving Banks) (Burst Length = 8, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High t CK1 CS RAS CAS WE DSF BS A9 RAx RBx RAy A0 ~ A8 RAx CAx RBx CBx RAy CAy tRCD tRP tWR DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Precharge Command Bank B Write Command Bank A Document:1G5-0145 Rev.1 Page 48 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 12.2 Random Row Write (Interleaving Banks) (Brust Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High t CK2 CS RAS CAS WE DSF BS A9 RAx RBx RAy A0 ~ A8 RAx CAx RBx CBx RAy CAy tRCD tWR* tRP tWR* DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) Document:1G5-0145 Rev.1 Page 49 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 12.3 Random Row Write (Interleaving Banks) (Burst Length = 8, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 CLK CKE High T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t CK3 CS RAS CAS WE BS BS A9 RBx RBx RAy A0 ~ A8 RBx CAx RBx CBx RAy CAy tRCD tWR* tRP tW R* DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B *tWR > tWR (min) Document:1G5-0145 Rev.1 Page 50 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 13.1 Read and Write Cycle (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK1 CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Read Write The Write Data Command is Masked with a Command Bank A Bank A Zero Clock Latency The Read Data is Masked with a Two Clock Latency Document:1G5-0145 Rev.1 Page 51 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 13.2 Read and Write Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK2 CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Write The Write Data Command is Masked with a Bank A Zero Clock Latency Read Command Bank A The Read Data is Masked with a Two Clock Latency Document:1G5-0145 Rev.1 Page 52 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 13.3 Read and Write Cycle (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS RAS CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Write The Write Data Command is Masked with a Bank A Zero Clock Latency Read Command Bank A The Read Data is Masked with a Two Clock Latency Document:1G5-0145 Rev.1 Page 53 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 14.1 Interleaving Column Read Cycle (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK1 CS RAS CAS WE DSF BS A9 RAx RBw A0 ~ A8 RAx CAx RBw CBw CBx CBy CAy CBz tRCD t AC1 DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank A Precharge Command Bank B Document:1G5-0145 Rev.1 Page 54 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 14.2 Interleaving Column Read Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t CK2 CS RAS CAS WE DSF BS A9 RAx RBw A0 ~ A8 RAx CAx RBw CBw CBx CBy CAy CBz t RCD tAC2 DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank A Precharge Command Bank B Document:1G5-0145 Rev.1 Page 55 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 14.3. Interleaved Column Read Cycle (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE DSF BS A9 RAx RBx A0 ~ A8 RAx CAx RBx CBx CBy CBz CAy DQM tRCD t AC3 DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Command Bank A Precharge Command Bank B Precharge Command Bank A Document:1G5-0145 Rev.1 Page 56 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 15.1. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK1 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE DSF BS A9 RAx RBw A0 ~ A8 RAx CAx RBw CBw CBx CBy CAy CBz tRP DQM tRCD tRRD tWR tRP DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Document:1G5-0145 Rev.1 Page 57 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 15.2. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE DSF BS A9 RAx RBw A0 ~ A8 RAx CAx RBw CBw CBx CBy CAy CBz DQM tRCD tRRD tRP tWR tRP DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Document:1G5-0145 Rev.1 Page 58 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 15.3. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE DSF BS A9 RAx RBw A0 ~ A8 RAx CAx RBw CBw CBx CBy CAy CBz tWR tRP tWR (min) DQM tRCD tRRD > tRRD(min) DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Document:1G5-0145 Rev.1 Page 59 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 16.1. Auto Precharge after Read Burst (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK1 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx RBx RBy RBz A0~A8 RAx CAx CAx CBx CAy RBy CBy RBz CBz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Activate Command Bank B Read with Auto Precharge Command Bank A Read with Auto Precharge Command Bank B Activate Command Bank B Read with Auto Precharge Command Bank B Document:1G5-0145 Rev.1 Page 60 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 16.2 Auto Precharge after Read Burst (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS DSF WE BS A9 RAx RBx RBy RAz A0 ~ A8 RAx CAx RBx CBx RAy RBy CBy RAz CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Az1 Az2 Activate Command Bank A Read with Command Bank A Read with Activate Auto Precharge Command Command Bank B Bank B Activate Read with Read with Read with Activate Auto Precharge Auto Precharge Command Auto Precharge Command Command Command Command Bank A Bank B Bank A Bank A Bank B Document:1G5-0145 Rev.1 Page 61 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 16.3 Auto Precharge after Read Burst (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx RBx RBy A0 ~ A8 RAx CAx RBx CBx CAy RBy CBy DQM Hi-Z A x0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 BY0 BY1 B Y2 BY3 Activate Command Bank A Activate Command Bank B Read Command Bank A Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Document:1G5-0145 Rev.1 Page 62 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 17.1 Auto Precharge after Write Burst (Burst Length = 4, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK1 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx RBx RBy RAz A0 ~ A8 RAx CAx RBx CBx C Ay RBy CBy RAz CAz DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3 Activate Command Bank A Write Command Bank A Write with Activate Auto Precharge Command Command Bank B Bank B Write with Auto Precharge Command Bank A Activate Command Bank B Activate Command Bank A Write with Auto Precharge Command Bank A Write with Auto Precharge Command Bank B Document:1G5-0145 Rev.1 Page 63 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 17.2. Auto Precharge after Write Burst (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx R Bx RBy R Az A0 ~ A8 RAx CAx RBx CBx C Ay RBy CBy RAz CAz DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3 Activate Command Bank A Write Command Bank A Write with Activate Auto Precharge Command Command Bank B Bank B Write with Auto Precharge Command Bank A Activate Activate Command Write with Command Write with Bank B Auto Precharge Bank A Auto Precharge Command Command Bank B Bank A Document:1G5-0145 Rev.1 Page 64 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 17.3. Auto Precharge after Write Burst (Burst Length = 4, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx RBx RBy A0 ~ A8 RAx CAx RBx CBx CAy RBy CBy DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Activate Command Bank B Write with Auto Precharge Command Bank B Document:1G5-0145 Rev.1 Page 65 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 18.1. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 CLK t T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CK1 High CS RAS CAS WE DSF BS A9 RAx RBx RBy A0 ~ A8 RAx CAx RBx CBx RBy DQM tRRD t RP DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7 Activate Command Bank A Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Precharge Command Bank B Activate Command Bank B Read Command Bank A Burst Stop Command Document:1G5-0145 Rev.1 Page 66 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 18.2. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx RBx RBy A0 ~ A8 R Ax CAx RBx CBx RBy DQM tRP DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Activate Command Bank A Read Command Bank A Activate Command Bank A Read Command Bank B Burst Stop Command Precharge Command Bank B Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Document:1G5-0145 Rev.1 Page 67 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 18.3. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS RAx RBx RBy A9 A0 ~ A8 RAx CAx RBx CBx RBy DQM tRP Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 DQ Activate Command Bank B Read Command Bank B Precharge Command Bank B Burst Stop Command Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Activate Command Bank B Activate Command Bank A Read Command Bank A The burst counter wraps from the highest order page address back to zero during this time interval Document:1G5-0145 Rev.1 Page 68 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 19.1 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK1 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx RBx RBy A0 ~ A8 RAx CAx RBx CBx RBy DQM DQ Hi-Z DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 DBx+7 Activate Command Bank A Activate Command Bank B Write Command Bank B Data is ignored Precharge Command Bank B Burst Stop Command Activate Command Bank B Write Command Bank A The burst counter wraps from the highest order page address back to zero during this time interval Full Page burst operation does not terminate when the burst length is satisfied;the burst counter increments and continues bursting beginning with the starting address Document:1G5-0145 Rev.1 Page 69 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 19.2 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE DSF BS A9 RAx RBx RBy A0 ~ A8 RAx CAx RBx CBx RBy DQM DQ DAx DAx+1 DAx+2 DAx+3 DAx-1 D Ax DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 Activate Write Activate Command Command Command Bank B Bank A Bank A The burst counter wraps from the highest order page address back to zero during this time interval Write Command Bank B Data is ignored Precharge Activate Command Command Bank B Bank B Full Page burst operation does not terminate when the burst length is satisfied;the burst counter increments and continues bursting beginning with the starting address. Burst Stop Command Document:1G5-0145 Rev.1 Page 70 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure19.3 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 CLK CKE High T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t CK3 CS RAS CAS WE DSF BS A9 RAx RBx RBy A0 ~ A8 RAx CAx RBx CBx RBy DQM Data is ignored DQ Hi-Z DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B The burst counter wraps from the highest order page addresss back to zero during this time interval Full Page burst operation does Burst stop not terminate when the burst Command length is satisfied;the burst counter inrements and continues bursting beginning with the starting address. Document:1G5-0145 Rev.1 Page 71 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 20. Byte Write Operation (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS RAS High t CK2 CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx CAy CAz DQM0 DQM1~3 DQ0 - DQ7 Ax0 Ax1 Ax2 DAy1 DAy2 Az1 Az2 DQ8 - DQ31 Hi-Z Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az2 Az3 Activate Read Command Command Bank A Bank A Lower Byte is masked Upper 3 Bytes are masked Write Command Bank A Read Command Bank A Upper 3 Bytes are masked Lower Byte is masked Lower Byte is masked Document:1G5-0145 Rev.1 Page 72 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 21. Burst Read and Single Write Operation (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS RAS High t CK2 CAS WE DSF BS A9 RAx A0 ~ A8 RAx CAx CAw CAx CAy CAz DQM0 DQM1~3 DQ0 - DQ7 Hi-Z Ax0 Ax1 Ax2 Ax3 DQw0 Ay0 Ay1 Ay3 Az0 DQ8 - DQ31 Hi-Z Ax0 Ax1 Ax2 Ax3 DQw0 DQx0 Ay0 Ay2 Ay3 Az0 Activate Read Command Command Bank A Bank A Read Single Write Command Command Bank A Bank A Single Write Command Bank A Lower Byte is masked Upptr 3 Bytes is masked Single Write Command Bank A Lower Byte is masked Document:1G5-0145 Rev.1 Page 73 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 22. Full Page Burst Read and Single Write Operation (Burst Length = Full Page, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS RAS High t CK3 CAS WE DSF BS A9 RAv A0 ~ A8 RAv CAv CAw CAx CAy DQM0 DQM1~3 DQ0 - DQ7 Av0 Av1 Av2 Av3 DQw0 DQx0 Av0 Av1 Av2 Av3 DQ8 - DQ31 Av0 Av1 Av2 Av3 DQw0 DQx0 Av0 Av1 Av2 Av3 Activate Command Bank A Read Command Bank A Burst Stop Command Single Write Single Write Read Command Command Command Bank A Bank A Bank A Burst Stop Command Document:1G5-0145 Rev.1 Page 74 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 23. Random Row Read (lnterleaving Banks) (Burst Length = 2, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 CLK CKE CS t CK1 High Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A RAS CAS WE DSF BS A9 RBu RAu RBv RAv RBw RAW RBx RAx RBy RAy RBz RAz A0 ~ A8 RBu CBu RAu CAu RBv CBv RAv CAv RBw CBw RAw CAw RBx CBx RAx CAx RBy CBy RAy CAy RBz CBz RAz DQM t RP t RP t RP t RP t RP t RP t RP t RP t RP tRP DQ Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0 Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Read Bank B With Auto Precharge Read Bank A With Auto Precharge Read Bank B With Auto Precharge Read Bank A With Auto Precharge Read Bank B With Auto Precharge Read Bank A With Auto Precharge Read Bank B With Auto Precharge Read Bank A With Auto Precharge Read Bank B With Auto Precharge Read Bank A With Auto Precharge Read Bank B With Auto Precharge Document:1G5-0145 Rev.1 Page 75 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 24. Full Page Random Column Read (Burst Length = Full Page, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE DSF BS A9 RAx RBx RBw A0 ~ A8 RAx RBx CAx CBx CAy CBy CAz CBz t RP RBw DQM t RRD tRCD DQ Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2 Read Activate Activate Command Command Command Bank B Bank A Bank B Read Read Command Command Bank A Bank A Read Read Command Command Bank A Bank B Read Command Bank B Precharge Command Bank B (Precharge Termination) Activate Command Bank B Document:1G5-0145 Rev.1 Page 76 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 25. Full Page Random Column Write (Burst Length = Full Page, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE DSF BS A9 RAx RBx RBw A0 ~ A8 RAx R Bx CAx CBx CAy CBy CAz CBz RBw tWR tRP DQM tRRD tRCD DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2 DQ Activate Command Bank A Activate Command Bank B Write Command Bank B Write Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B (Precharge Termination) Write Data is masked Activate Command Bank B Write Command Bank A Command Bank A Document:1G5-0145 Rev.1 Page 77 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 26.1. Precharge Termination of a Burst (Burst Length = Full Page, CAS Latency = 1) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK1 CKE CS RAS CAS WE DSF BS RAx RAy A9 RAz RAx CAx RAy CAy RAz CAz A0 ~ A8 tWR tRP tRP DQM Precharge Termination of a Read Burst DQ DAx0 DAx1 DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz0 DAz1 DAz2 DAz3 DAz4 DAz5 DAz6 DAz7 Activate Command Bank A Precharge Termination Precharge Command of a Write Burst. Bank A Write data is masked. Read command Bank A Write Precharge Command Command Bank A Bank A Activate Command Bank A Write Command Bank A Activate Command Bank A Document:1G5-0145 Rev.1 Page 78 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 26.2. Precharge Termination of a Burst (Burst Length = 8 or Full Page, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS RAS CAS WE DSF BS RAx RAy RAz A9 RAx CAx RAy CAy R Az CAz A0 ~ A8 tWR tRP tRP tRP DQM DQ DAx0 DAx1 DAx2 DAx3 Ay0 Ay1 Ay2 DAz0 DAz1 DAz2 Activate Command Bank A Write Command Bank A Precharge Activate Command Command Bank A Bank A Read command Bank A Precharge Command Bank A Activate Command Bank A Precharge Termination of a Write Burst. Write data is masked. Read Precharge Command Command Bank A Bank A Precharge Termination of a Read Burst Document:1G5-0145 Rev.1 Page 79 VIS Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Figure 26.3 Precharge Termination of a Burst (Burst Length = 4, 8 or Full page, CAS Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High t CK3 CKE CS RAS CAS WE DSF BS A9 RAx RAy RAz A0 ~ A8 RAx CAx RAy CAy RAz t WR t RP t RP DQM DQ DAx0 DAx1 Ay0 Ay1 Ay2 Activate Command Bank A Write Command Bank A Write Data is masked Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Activate Command Command Bank A Bank A Precharge Termination of a Write Burst Precharge Termination of a Write Burst Document:1G5-0145 Rev.1 Page 80 VIS Ordering Information Part Number VG4616321BQ-7 VG4616321BQ-7R VG4616321BQ - 6 VG4616321BQ - 6R VG4616321BQ - 5 VG4616321BQ - 5R VG4616322BQ-7 VG4616322BQ-7R VG4616322BQ-6 VG4616322BQ-6R VG4616322BQ-5 VG4616322BQ-5R Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM Frequency 143MHz 143MHz 166MHz 166MHz 200MHz 200MHz 143MHz 143MHz 166MHz 166MHz 200MHz 200MHz Package QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP Packing Type Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel VG4616321BQ - 7 • VG • 46 •16321(2) •B •Q •7 •R • VIS Memory Product • Synchronous Graphic • Sync, 2k self - ref. 512k x 32 SGRAM.16321 LVTTL, 16322 : SSTL-3 • Revision • Package Type (Q : QFP) • Speed (7 : 7ns, 6 : 6ns , 5 : 5ns) • Packing Type (R : Tape & Reel, Blank : Tray) Document:1G5-0145 Rev.1 Page 81 VIS Outline Drawing Information DIM A A1 A2 b c D D1 E E1 e L L1 θ 0.73 0¢X Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM D D1 MIN. --0.25 MILLIMETERS NOM. MAX. --3.40 ----2.90 2.70 2.50 0.38 --0.22 0.23 0.15 0.11 23.20 20.00 17.20 14.00 0.65 BASIC 0.88 1.60 REF. --7¢X 1.03 23.40 20.15 17.40 14.15 MIN. --0.010 0.098 0.009 0.004 0.906 0.781 0.669 0.545 0.029 0¢X INCHES NOM. MAX. --0.134 ----0.106 0.114 --0.015 0.006 0.009 0.913 0.787 0.677 0.551 0.035 0.063 REF. --7¢X 0.921 0.793 0.685 0.557 0.041 80 81 51 50 c A2 A 23.00 19.85 17.00 13.85 E1 E A1 L 0.12mmM b TYP. L1 θ 0.026 BASIC 100 1 30 31 DETAIL A NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D1 & E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. DIMENSION D1 & E1 INCLUDE MOLD MISMATCH. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAXIMUM b DIMENSION BY SEATING PLANE MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DETAIL A e 0.08mm e Document:1G5-0145 Rev.1 Page 82