W3H64M72E-667ESM

White Electronic Designs W3H64M72E-XSBX ADVANCED* 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Package: • 208 Plastic Ball Grid Array (PBGA), 17 x 23mm • 1.0mm pitch DDR2 Data Rate = 667*, 533, 400 Core Supply Voltage = 1.8V ± 0.1V I/O Supply Voltage = 1.8V ± 0.1V - (SSTL_18 compatible) Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Adjustable data – output drive strength Programmable CAS latency: 3, 4 or 5 Posted CAS additive latency: 0, 1, 2, 3 or 4 Write latency = Read latency - 1* tCK Commercial, Industrial and Military Temperature Ranges Organized as 64M x 72 Weight: W3H64M72E-XSBX - 2.5 grams typical BENEFITS 63% SPACE SAVINGS vs. FPBGA Reduced part count 55% I/O reduction vs FPBGA Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Upgradable to 128M x 72 density (contact factory for information) * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. FIGURE 1 – DENSITY COMPARISONS Actual Size W3H64M72E-XSBX 11.0 CSP Approach (mm) 11.0 11.0 11.0 11.0 23 19.0 90 FBGA 90 FBGA 90 FBGA 90 FBGA 90 FBGA White Electronic Designs W3H64M72E-XSBX 17 S A V I N G S 63% 55% Area I/O Count 5 x 209mm2 = 1,045mm2 5 x 92 balls = 460 balls 391mm2 208 Balls White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H64M72E-XSBX ADVANCED* FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM CS# WE# RAS# CAS# CKE CS# WE# RAS# CAS# CKE ODT A0-12 BA0-2 DQ0 ¥ CK CK# LDM UDM LDQS LDQS# UDQS UDQS# ODT A0-12 BA0-2 CK0 CK0# LDM0 UDM0 LDQS0 LDQS0# UDQS0 UDQS0# DQ0 U0 ¥ ¥ ¥ ¥ ¥ DQ15 ¥ ¥ ¥ ¥ ¥ ¥ DQ15 CK1 CK1# LDM1 UDM1 LDQS1 LDQS1# UDQS1 UDQS1# CS# WE# RAS# CAS# CKE ODT A0-12 DQ0 BA0-2 ¥ CK CK# LDM UDM LDQS LDQS# UDQS UDQS# DQ16 U1 ¥ ¥ ¥ ¥ ¥ DQ15 ¥ ¥ ¥ ¥ ¥ ¥ DQ31 CS# WE# RAS# CAS# CKE ODT A0-12 BA0-2 CK2 CK2# LDM2 UDM2 LDQS2 LDQS2# UDQS2 UDQS2# CK CK# LDM UDM LDQS LDQS# UDQS UDQS# DQ0 DQ32 U2 ¥ ¥ ¥ ¥ ¥ ¥ DQ15 ¥ ¥ ¥ ¥ ¥ ¥ DQ47 CS# WE# RAS# CAS# CKE ODT A0-12 DQ0 BA0-2 CK3 CK3# LDM3 UDM3 LDQS3 LDQS3# UDQS3 UDQS3# CK CK# LDM UDM LDQS LDQS# UDQS UDQS# DQ48 U3 ¥ ¥ ¥ ¥ ¥ ¥ DQ15 ¥ ¥ ¥ ¥ ¥ ¥ DQ63 CS# WE# RAS# CAS# CKE ODT A0-12 DQ0 BA0-2 CK4 CK4# LDM4 VCC LDQS4 LDQS4# UDQS4 UDQS4# CK CK# LDM UDM LDQS LDQS# UDQS UDQS# DQ64 U4 ¥ ¥ ¥ ¥ ¥ ¥ DQ15 ¥ ¥ ¥ ¥ ¥ ¥ DQ71 White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 3 - PIN CONFIGURATION TOP VIEW W3H64M72E-XSBX ADVANCED* 1 A B C D E F G H J K L M N P R T U V W VCC 2 VCC 3 VSS 4 VCC 5 VCC 6 VSS 7 VCC 8 VCC 9 VSS 10 11 VCC VSS VSS NC NC NC NC NC NC NC VSS VCC VSS NC NC NC NC NC NC DQ34 CK3 CK3# VSS DQ35 DQ51 NC NC NC NC DQ50 DQ53 DQ37 CK2# CK2 DQ52 DQ36 DQ33 NC BA2 DNU DQ39 LDQS2 LDQS3 DQ48 DQ32 LDM3 LDM2 DQ49 DQ43 DQ59 DNU DQ55 DQ58 DQ42 LDQS2# LDQS3# DQ38 DQ54 DQ60 DQ57 UMD2 VSS DQ63 DQ56 DQ40 DQ61 DQ45 UMD3 DQ44 DQ41 DQ46 DQ62 VCC UDQS2# DQ47 UDQS2 UDQS3 UDQS3# VCC A6 A10 A9 VCC VSS VCC A3 A12 DNU* VCC VSS A0 A11 VCC VSS VREF VSS VCC A1 BA1 VSS VCC A2 A4 A8 VCC VSS VCC BA0 A5 A7 VCC UDQS1# UDQS1 UDQS0 DQ15 UDQS0# VCC DQ30 DQ14 DQ9 DQ12 UMD1 DQ13 DQ29 DQ8 DQ24 DQ31 VSS UDM0 DQ25 DQ28 DQ22 DQ6 LDQS1# LDQS0# DQ10 DQ26 DQ23 ODT DQ27 DQ11 DQ17 LDM0 LDM1 DQ0 DQ16 LDQS1 LDQS0 DQ7 LDQS4# UDQS4 UDQS4# DQ1 DQ4 DQ20 CK0 CK0# DQ5 DQ21 DQ18 LDQS4 DQ71 CKE WE# DQ19 DQ3 VSS CK1# CK1 DQ2 RAS# CAS# DQ64 DQ70 DQ65 DQ68 VSS VCC VSS CK4# CK4 CS# DQ66 DQ69 LDM4 DQ67 VSS VCC VSS VCC VSS VCC VCC VSS Vcc VCC VSS VCC VSS * Pin J10 is reserved for signal A13 on 128Mx72 and higher densities. Note: UDQS4 and UDQS4# require a 10KΩ pull up resistor. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs TABLE 1 – BALL DESCRIPTIONS Symbol ODT Type Input Description W3H64M72E-XSBX ADVANCED* On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once VCC is applied during first power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH operation, VREF must be maintained. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4 Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. Continued on next page CK, CK# Input CKE Input CS# RAS#, CAS#, WE# Input Input LDM, UDM Input BA0–BA2 Input White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H64M72E-XSBX ADVANCED* TABLE – 1 BALL DESCRIPTIONS (continued) Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD MODE command. Data input/output: Bidirectional data bus Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edgealigned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edgealigned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Power Supply: 1.8V ±0.1V DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity SSTL_18 reference voltage. Ground No connect: These balls should be left unconnected. Future use; address bits A14 and A15 are reserved for future densities. A0-A12 Input DQ0-71 UDQS, UDQS# I/O I/O LDQS, LDQS# VCC VCCQ VREF VSS NC DNU I/O Supply Supply Supply Supply - White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DESCRIPTION The 4Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 4,294,967,296 bits. Each of the five chips in the MCP are internally configured as 8-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3. The 4Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the 4Gb DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. There are strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The 4Gb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with another write. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 6 W3H64M72E-XSBX ADVANCED* An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18compatible. GENERAL NOTES • The functionality and the timing specifications discussed in this data sheet are for the DLLenabled mode of operation. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, each chip is divided into 2 bytes, the lower byte and upper byte. For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS. Note that the there is no upper byte for U4 and therefore no UDM4. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. • • • INITIALIZATION DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for power up and initialization and is shown in Figure 4 on page 8. White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Notes appear on page 9 W3H64M72E-XSBX ADVANCED* FIGURE 4 – POWER-UP AND INITIALIZATION VCC VCCQ VTT1 VREF T0 tCK Ta0 Tb0 Tc0 Td0 Te0 Tf 0 Tg 0 Th 0 Ti 0 Tj 0 Tk 0 Tl 0 Tm 0 t VTD1 CK# CK tCL tCL See not e 3 SSTL_18 LVCM OS CKE LOW LEVEL8 LOW LEVEL8 OD T COM M A ND NOP2 PRE LM LM LM LM PRE REF REF LM LM LM VA LID3 DM 7 A DDRESS9 A 10 = 1 CODE CODE CODE CODE A 10 = 1 CODE CODE CODE VA LID DQS7 DQ 7 RTT Hi g h -Z Hi g h -Z Hi g h -Z T = 200µ s (M IN) Po w er -u p : VCC an d st ab l e cl o ck (CK, CK#) T = 400n s (M IN) t RPA EM R(2) t M RD t M RD EM R(3) t M RD t M RD t RPA t RFC t RFC See not e 4 t M RD t M RD t M RD EM R w i t h DLL ENA BLE5 M R w /o EM R w i t h DLL RESET OCD Def au l t 10 200 cycl es o f CK3 EM R w i t h OCD Exi t 11 No r m al Op er at i o n DON’ T CA RE In dicat es a b r eak i n t i m e scal e M R w it h DLL RESET White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs NOTES: 1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF, and VTT are between their minimum and maximum values as stated in DC Operating Conditions table): A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V. Once supply voltage ramping is complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table specifications apply. • VCC, VCCQ are driven from a single power converter output • VTT is limited to 0.95V MAX • VREF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp time. • VCCQ ≥ VREF at all times B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage ramping, for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses VCC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table specifications apply. • Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be ≤ 200ms from when VCC ramps from 300mV to VCC (MIN) • Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤ 500ms; while VCC is ramping, current can be supplied from VCC through the device to VCCQ • VREF must track VCCQ/2, VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp time; VCCQ ≥ VREF must be met at all times • Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT (MIN) is achieved must be no greater than 500ms 2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-up prior to VREF. being stable. After state T0, Cke is required to have SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for the duration on the initialization sequence. 3. PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode Register, EMR = extended mode register, EMR2 = extended mode register 2, EMR3 = extended mode register 3, REF = REFRESH command, ACT = ACTIVE command, A10 = PRECHARGE ALL, CODE = desired value for mode registers (blank addresses are required to be decoded), VALID - any valid command/ address, RA = row address, bank address. 4. DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS#, DQ represents DQ0-71. 5. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT commands, then take CKE HIGH. 6. Wait a minimum of 400ns, then issue a PRECHARGE ALL command. 7. Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command, provide LOW to BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or "1;" all others must be "0". 8. Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command, provide HIGH to BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0". 9. Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL W3H64M72E-XSBX ADVANCED* 10. 11. 12. 13. 14. 15. 16. ENABLE command provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits E7, E8 and E9 can be set to "0" or "1;" Micron recommends setting them to "0". Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA2 = BA1 = BA0 = 0.) CKE must be HIGH the entire time. . Issue PRECHARGE ALL command. Issue two or more REFRESH commands. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program operating parameters without resetting the DLL). To access the mode registers, BA0 = 0, BA1 = 0, BA2 = 0. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and E9 to “1,” and then setting all other desired parameters. To access the extended mode register, BA2 = 0, BA1 = 0, BA0 = 1. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to “0,” and then setting all other desired parameters. To access the extended mode registers, BA2 = 0, BA1 = 0, BA0 = 1. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the DLL RESET at Tf0. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs MODE REGISTER (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CL, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 5. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0–M14) must be programmed when the command is issued. The mode register is programmed via the LM command (bits BA2–BA0 = 0, 0, 0) and other bits (M12–M0) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The controller must wait the specified time tMRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. W3H64M72E-XSBX ADVANCED* FIGURE 5 – MODE REGISTER (MR) DEFINITION BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 15 14 13 12 11 10 01 PD MR WR 9 876543210 DLL TM CAS# Latency BT Burst Length Mode Register (Mx) M7 Mo de 0 Normal M12 0 1 PD mode Fast Exit (Normal) Slow Exit (Low Power) M8 DLL Reset 0 1 No Yes 1 Test M2 M1 M0 Burst Length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved M11 M10 M9 WRITE RECOVERY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 3 4 5 6 Reserved Reserved M6 M5 M4 0 0 M15 M14 0 0 1 0 1 0 1 1 Mo de Register Definition Mode Register (MR) Extended Mode Register (EMR) Extended Mode Register (EMR2) Extended Mode Register (EMR3) 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 0 1 Burst Type Sequential Interleaved CAS Latency (CL) Reserved Reserved Reserved 3 4 5 6 Reserved BURST LENGTH Burst length is defined by bits M0–M3, as shown in Figure 5. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length dete rmines the maximum number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Note: 1. Not used on this part BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs TABLE 2 – BURST DEFINITION Burst Length Starting Column Address A1 0 4 0 1 1 A2 0 0 0 8 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-0-5-6-7-4 2-3-0-1-6-7-4-5 3-0-1-2-7-4-5-6 4-5-6-7-0-1-2-3 5-6-7-4-1-2-3-0 6-7-4-5-2-3-0-1 7-4-5-6-3-0-1-2 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 Order of Accesses Within a Burst Type = Sequential Type = Interleaved W3H64M72E-XSBX ADVANCED* DLL RESET DLL RESET is defined by bit M8, as shown in Figure 5. Programming bit M8 to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of “0” after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. WRITE RECOVERY Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 5. The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the internal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last data burst. WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9–M11. The user is required to program the value of WR, which is calculated by dividing t WR (in ns) by tCK (in ns) and rounding up a non integer value to the next integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result. NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. POWER-DOWN MODE Active power-down (PD) mode is defined by bit M12, as shown in Figure 5. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 does not apply to precharge PD mode. When bit M12 = 0, standard active PD mode or “fast-exit” active PD mode is enabled. The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower-power active PD mode or “slowexit” active PD mode is enabled. The tXARD parameter is used for slow-exit active PD exit timing. The DLL can be enabled, but “frozen” during active PD mode since the exitto-READ command timing is relaxed. The power difference expected between PD normal and PD low-power mode is defined in the ICC table. OPERATING MODE The normal operating mode is selected by issuing a command with bit M7 set to “0,” and all other bits set to the desired values, as shown in Figure 5. When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is ‘1.’ White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs CAS LATENCY (CL) The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 5. CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending on the speed grade option being used. DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. W3H64M72E-XSBX ADVANCED* DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This feature allows the READ command to be issued prior to tRCD (MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. Examples of CL = 3 and CL = 4 are shown in Figure 6; both assume AL = 0. If a READ command is registered at clock edge n, and the CL is m clocks, the data will be available nominally coincident with clock edge n+m (this assumes AL = 0). FIGURE 6 – CAS LATENCY (CL) CK# CK COMMAND DQS, DQS# DQ CL = 3 (AL = 0) DOUT n DOUT n+1 DOUT n+2 DOUT n+3 T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP CK# CK COMMAND DQS, DQS# DQ T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP NOP NOP NOP DOUT n DOUT n+1 DOUT n+2 DOUT n+3 CL = 4 (AL = 0) Burst length = 4 Posted CAS# additive latency (AL) = 0 Shown with nominal t AC, t DQSCK, and t DQSQ TRANSITIONING DATA DON’T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EXTENDED MODE REGISTER (EMR) The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on die termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These functions are controlled via the bits shown in Figure 7. The EMR is programmed via the LOAD MODE (LM) command and will retain the stored information W3H64M72E-XSBX ADVANCED* until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. FIGURE 7 – EXTENDED MODE REGISTER DEFINITION BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 16 15 14 MRS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode Register (Ex) 0 2 out RDQS DQS# OCD Program R TT Posted CAS# R TT ODS DLL E12 0 1 Outputs Enabled Disabled E0 E6 E2 Rtt (nominal) 0 0 0 1 0 1 R TT disabled 75 Ω 150 Ω 50 Ω 0 1 DLL Ena ble Enable (Normal) Disable (Test/Debug) E11 RDQ S Ena ble 0 1 No Yes 1 1 E1 0 1 Output Drive Strength Full strength (18 Ω target) Reduced strength (40 Ω target) E10 DQ S# Ena ble 0 1 Enable Disable E5 E4 E3 Poste d CA S# A dditive Laten cy (AL) 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 Reserved Reserved Reserved E9 E8 E7 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 OCD Operation OCD not supported Reserved Reserved Reserved OCD default state 1 1 0 1 1 1 1 E16 E15 E14 0 0 0 0 0 0 1 1 0 1 0 1 Mo de Regi ster Set Mode register set (MRS) Extended mode register (EMRS) Extended mode register (EMRS2) Extended mode register (EMRS3) Note: 1. During initialization, all three bits must be set to "1" for OCD default state, then must be set to "0" before initialization is finished, as detailed in the initialization procedure. 2.. E13 (A13) is not used on this device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DLL ENABLE/DISABLE The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 7. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using an LM command. The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset upon exit of SELF REFRESH operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued, to allow time for the internal clock to synchronize with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. W3H64M72E-XSBX ADVANCED* OUTPUT ENABLE/DISABLE The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled, thus removing output buffer current. The output disable feature is intended to be used during ICC characterization of read current. ON-DIE TERMINATION (ODT) ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in Figure 7. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 50Ω ,75Ω, and 150Ω are selectable and apply to each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2) determine what ODT resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is elected by enabling switch “sw1,” which enables all R1 values that are 150Ω each, enabling an effective resistance of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values of 100Ω enabling effective resistance of 50Ω Reserved states should not be used, as unknown operation or incompatibility with future versions may result. The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input ball are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge powerdown modes of operation. ODT must be turned off prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until issuing the EMR command to enable the ODT feature, at which point the ODT ball will determine the RTT(EFF) value. Any time the EMR enables the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has been enabled. See “ODT Timing” section for ODT timing diagrams. OUTPUT DRIVE STRENGTH The output drive strength is defined by bit E1, as shown in Figure 7. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0 selects normal (full strength) drive strength for all outputs. Selecting a reduced drive strength option (E1 = 1) will reduce all outputs to approximately 60 percent of the SSTL_18 drive strength. This option is intended for the support of lighter load and/or point-to-point environments. DQS# ENABLE/DISABLE The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single ended mode and the DQS# ball is disabled. When disabled, DQS# should be left floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs POSTED CAS ADDITIVE LATENCY (AL) Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result. W3H64M72E-XSBX ADVANCED* In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tRCD (MIN) with the requirement that AL ≤ tRCD (MIN). A typical application using this feature would set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is controlled by the sum of AL and CL; RL = AL+CL. Write latency (WL) is equal to RL minus one clock; WL = AL + CL - 1 x tCK. FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0 Address Bus 16 15 14 13 12 11 EMR2 01 01 01 10 9 8765432 01 01 01 01 01 01 01 01 01 1 0 1 0 01 Exten ded Mo de Register (Ex) M1 6 M15 M14 0 0 0 0 0 0 1 1 0 1 0 1 Mode Register Definition Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) E7 0 1 High Temperature Self Refresh rate enable Commercial temperature default Industrial temperature option; use if T C exceeds 85° C Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to "0." A13 is not used in this device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H64M72E-XSBX ADVANCED* FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0 Address Bus 16 15 14 13 12 EMR3 01 01 11 10 9 87 01 01 01 01 01 6 01 54 01 01 3 01 2 01 1 01 0 01 Exten ded Mo de Register (Ex) M1 6 M15 M14 0 0 0 0 0 0 1 1 0 1 0 1 Mode Register Definition Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to "0." A13 is not used in this device. EXTENDED MODE REGISTER 2 The extended mode register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved, as shown in Figure 8. The EMR2 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. Bit E7 (A7) must be programmed as"1" to provide a faster refresh rate on devices if the TCASE exceeds 85°C EMR2 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. not alter the contents of the memory array, provided it is performed correctly. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. COMMAND TRUTH TABLES The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes, and bank-to-bank commands. EXTENDED MODE REGISTER 3 The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently, all bits in EMR3 are reserved, as shown in Figure 9. The EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3H64M72E-XSBX ADVANCED* TABLE 3 – TRUTH TABLE - DDR2 COMMANDS Notes 1, 5, and 6 apply to all CKE Function LOAD MODE REFRESH SELF-REFRESH Entry SELF-REFRESH Exit Single bank precharge All banks PRECHARGE Bank activate WRITE WRITE with auto precharge READ READ with auto precharge NO OPERATION Device DESELECT POWER-DOWN entry POWER-DOWN exit Previous Cycle H H H L H H H H H H H H H H L Current Cycle H H L H H H H H H H H X X L H CS# L L L H L L L L L L L L L H H L H L RAS# L L L X H L L L L H H H H X X H X H CAS# L L L X H H H H H L L L H X X H X H WE# L H H X H L L L L L H H H X X H X H BA2 BA1 BA0 BA X X X X X BA BA BA BA BA X X X X Column Address Column Address Column Address Column Address X X X X X X X X X A12 A11 A10 OP Code X X X L H Row Address L H L H X X X X A9-A0 Notes 2 X X X X X 7 2 Column Address Column Address Column Address Column Address X X X X 2, 3 2, 3 2, 3 2, 3 4 4 Note: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. 2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed. 3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. 4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details. 6. “X” means “H or L” (but a defined logic level). 7. Self refresh exit is asynchronous. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. W3H64M72E-XSBX ADVANCED* entered. The same procedure is used to convert other specification limits from time units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE (LM) The mode registers are loaded via inputs BA2–BA0, and A12–A0. BA2–BA0 determine which mode register will be programmed. See “Mode Register (MR)”. The LM command can only be issued when all banks are idle, and a subsequent execute able command cannot be issued until tMRD is met. FIGURE 10 – ACTIVE COMMAND CK# BANK/ROW ACTIVATION ACTIVE COMMAND The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A12–A0 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. CK CKE CS# RAS# CAS# WE# Row ACTIVE OPERATION Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 17 ADDRESS BANK ADDRESS Bank DON’T CARE White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs READ COMMAND The READ command is used to initiate a burst read access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–i (where i = A9) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. W3H64M72E-XSBX ADVANCED* FIGURE 11 – READ COMMAND CK# CK CKE CS# READ OPERATION READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. During READ bursts, the valid data-out element from the starting column address will be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL; RL = AL + CL. The value for AL and CL are programmable via the MR and EMR commands, respectively. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and HIGH state on DQS# is known as the read preamble (tRPRE). The LOW state on DQS and HIGH state on DQS# coincident with the last data-out element is known as the read postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals BL / 2 cycles. RAS# CAS# WE# ADDRESS AUTO PRE CHARGE Col ENABLE A10 DISABLE BANK ADDRESS Bank DON’T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 18 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WRITE COMMAND The WRITE command is used to initiate a burst write access to an active row. The value on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–9 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. W3H64M72E-XSBX ADVANCED* DQS edge is WL ± tDQSS. Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as ± tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The first data element from the new burst is applied after the last element of a completed burst. The new WRITE command should be issued x cycles after the first WRITE command, where x equals BL/2. DDR2 SDRAM supports concurrent auto precharge options, as shown in Table 4. DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However, a WRITE (with auto precharge disabled) using BL = 8 operation might be interrupted and truncated ONLY by another WRITE burst as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may not to be interrupted or truncated with any command except another WRITE command. Data for any WRITE burst may be followed by a subsequent READ command. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. tWT starts at the end of the data burst, regardless of the data mask condition. WRITE OPERATION WRITE bursts are initiated with a WRITE command, as shown in Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first rising White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 19 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 12 – WRITE COMMAND CK# CK CKE CS# RAS# CAS# HIGH W3H64M72E-XSBX ADVANCED* WE# ADDRESS CA EN AP A10 DIS AP BANK ADDRESS BA DON’T CARE Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge. TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE From Command (Bank n) To Command (Bank m) READ OR READ w/AP WRITE with Auto Precharge WRITE or WRITE w/AP PRECHARGE or ACTIVE Minimum Delay (With Concurrent Auto Precharge) (CL-1) + (BL/2) + WTR (BL/2) 1 t Units t t t CK CK CK White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 20 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PRECHARGE COMMAND The PRECHARGE command, illustrated in Figure 13, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. W3H64M72E-XSBX ADVANCED* FIGURE 13 – PRECHARGE COMMAND CK# CK CKE HIGH CS# RAS# CAS# WE# ADDRESS ALL BANKS PRECHARGE OPERATION Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA2–BA0 select the bank. Otherwise BA2–BA0 are treated as “Don’t Care.” When all banks are to be precharged, inputs BA2–BA0 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices. A10 ONE BANK BA0 - BA2 BA DON’T CARE Note: BA = bank address (if A10 is LOW; otherwise "Don't Care"). SELF REFRESH COMMAND The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including VREF) must be maintained at valid levels upon entry/exit and during SELF REFRESH operation. The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a READ command can be issued). The differential clock should remain stable and meet tCKE specifications at least 1 x tCK after entering self refresh mode. All command and address input signals except CKE are “Don’t Care” during self refresh. The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable and meet tCK specifications at least 1 x tCK prior to CKE going back HIGH. Once CKE is HIGH (tCLE(MIN) has been satisfied with four clock registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOP or DESELECT commands for 200 clock cycles before applying any other command. Note: Self refresh not available at military temperature.. White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2006 Rev. 1 21 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage I/O Reference voltage I/O Termination voltage Symbol VCC VCCQ VREF VTT Min 1 .7 1 .7 0.49 x VCCQ VREF-0.04 Typical 1 .8 1 .8 0.50 x VCCQ VREF W3H64M72E-XSBX ADVANCED* Max 1 .9 1 .9 0.51 x VCCQ VREF + 0.04 Unit V V V V Notes 1 4 2 3 Notes: 1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC track with VCC. ABSOLUTE MAXIMUM RATINGS Symbol VCC VCCQ VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on any pin relative to VSS Storage temperature Command/Address, RAS#, CAS#, WE#, CS#, CKE CK, CK# DM DQ, DQS, DQS# MIN -1.0 -0.5 -0.5 -55 -25 -10 -5 -5 -10 MAX 2.3 2.3 2.3 125 25 10 5 5 10 U nit V V V °C µA µA µA µA µA IL Input leakage current; Any input 0V