WED7PXXXATA70XXI25

White Electronic Designs 128MB to 1GB Industrial ATA Flash FEATURES ATA Compatibility • 3.3V or 5.0V single power supply. • 68 pin two piece connector with Type-2 form factor (5mm thickness) • Support for CIS implementation with 256 bytes of attribute memory Interface modes • PC card memory mode • PC card I/O mode • True IDE mode High performance • Interface Transfer speed in PIO mode 4 or Multi Word DMA mode 2 cycle timing, 16.6 Mbytes/ second (theoretical) • Sustained write: max 6.0 Mbytes/s in ATA PIO mode 4 cycle timing • Sustained read: max 6.5 Mbytes/s in ATA PIO mode 4 cycle timing W/E Endurance: 100,000cycles1 /300,000cycles2 Notes: 1. TA = -40 to 85°C 2. TA = 0 to 70°C WED7PxxxATA70xxI25 512MB and 1.02GB unformatted capacity. Being able to emulate IDE hard disk drives, WEDC’s ATA card is a perfect choice for solid-state mass-storage in industrial applications and applications that require performance and extended environmental tolerances. Dimensions: Type 2 card: 85.6mm(L) x 54.0mm (W) x 5.03mm (H) Lead free and RoHS compliant Storage Capacities: 128MB, 256MB, 512MB and 1.02GB (unformatted) Operating Voltage: 3.3V ± 5% 5.0V ± 0.5V Power consumption: • 5V operation Active mode: Write operation: 28 mA (Typ.) Read operation: 23 mA (Typ.) Power down mode: 1.2mA (Typ.) 2.0mA (max.) • 3.3V operation Active mode: Write operation: 25 mA (Typ.) Read operation: 21 mA (Typ.) Power down mode: 1.0mA (Typ.) 1.5mA (max.) Environment conditions: • Operating temperature: -40°C to 85°C • Storage temperature: -45°C to 90°C • Storage humidity: 95% (max) (No condensation) * This product is subject to change without notice. DESCRIPTION The WED7PxxxATA70xxI25 series ATA card is an ATA interface flash memory card based on flash technology. The ATA card is constructed with a flash disk controller chip and NAND-type flash memory device. Operates from a single 5-Volt or 3.3-Volt power source. The card is available in ATA type-2 form factor with 128MB, 256MB, PRODUCT TYPES Card Density 128MB 256MB 512MB 1.02GB Model No. 7P128ATA70xxI25 7P256ATA70xxI25 7P512ATA70xxI25 7P1G0ATA70xxI25 Cylinder 978 978 993 1985 Head 8 16 16 16 Sector 32 32 63 63 Memory capacity1 128,188,416 Byte 256,376,832 Byte 512,483,328 Byte 1024,450,560 Byte 1: It is the logical address capacity including the area used for File System. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED7PxxxATA70xxI25 PIN ASSIGNMENTS AND PIN TYPE Memory card mode Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name GND D3 D4 D5 D6 D7 CE1# A10 OE# N.C. A9 A8 N.C. N.C. WE# RDY/BSY Vcc N.C. N.C. N.C. N.C. A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND – – – – I I I I I I I I I/O I/O I/O O – I/O I/O I/O I/O I/O I I I – I I – – I O I/O I/O Card Mode Signal Name GND D3 D4 D5 D6 D7 CE1# A10 OE# N.C. A9 A8 N.C. N.C. WE# IREQ# Vcc N.C. N.C. N.C. N.C. A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND – – – – I I I I I I I I I/O I/O I/O O – I/O I/O I/O I/O I/O I I I – I I – – I O I/O True IDE Mode Signal Name GND D3 D4 D5 D6 D7 CE1# A10 ATASEL# N.C. A9 A8 N.C. N.C. WE# INTRQ Vcc N.C. N.C. N.C. N.C. A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND – – – – I I I I I I I I I/O I/O I/O O – I/O I/O I/O I/O I/O I I I – I I – – I O I/O Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Memory card mode Signal Name GND CD1# D11 D12 D13 D14 D15 CE2# VS1 IORD# IOWR# NC NC NC NC NC Vcc NC NC NC NC CSEL# VS2 RESET Wait# INPACK# REG# BVD2 BVD1 D8 D9 D10 CD2# GND I/O – O I/O I/O I/O I/O I I O I I – – – – – – – – – – I O I O O I I/O I/O I/O I/O O O – I/O Card Mode Signal Name GND CD1# D11 D12 D13 D14 D15 CE2# VS1 IORD# IOWR# NC NC NC NC NC Vcc NC NC NC NC CSEL# VS2 RESET Wait# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND I/O – O I/O I/O I/O I/O I I O I I – – – – – – – – – – I O I O O I I/O I/O I/O I/O O O – True IDE Mode Signal Name GND CD1# D11 D12 D13 D14 D15 CE2# VS1 IORD# IOWR# NC NC NC NC NC Vcc NC NC NC NC CSEL# VS2 RESET# IORDY INPACK# REG# DASP PDIAG# D8 D9 D10 CD2# GND I/O – O I/O I/O I/O I/O I I O I I – – – – – – – – – – I O I O O I I/O I/O I/O I/O O O – White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ACCESS SPECIFICATIONS 1. Attribute access specifications WED7PxxxATA70xxI25 When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the condition of REG# = ”L” as follows. That region can be accessed by Byte/Word/Odd-byte modes, which are defined by PC card standard specifications. Attribute Read Access Mode Mode Standby mode Byte access (8bit) Word access (16bit) Odd byte access (8bit) Note: X → L or H REG# X L L L L CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X L L L L WE# X H H H H D8 to D15 High-Z High-Z High-Z invalid invalid D0 to D7 High-Z even byte Invalid even byte High-Z Attribute Write Access Mode Mode Standby mode Byte access (8bit) Word access (16bit) Odd byte access (8bit) Note: X → L or H Write CIS-ROM region is invalid. REG# X L L L L CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X H H H H WE# X L L L L D8 to D15 Don’t care Don’t care Don’t care Don’t care Don’t care D0 to D7 Don’t care even byte Don’t care even byte Don’t care White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs 2. Task File register access specifications WED7PxxxATA70xxI25 There are two types of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address area. Each type of Task File register read and write operation is executed under the condition as follows. That area can be accessed by Byte/Word/Odd Byte modes, which are defined by PC card standard specifications. (1) I/O address map – Task File Register Read Access Mode (1) Mode Standby mode Byte access (8bit) Word access (16bit) Odd byte access (8bit) Note: X → L or H REG# X L L L L CE2# H H H L L CE1# H L L L H A0 X L H X X IORD# X L L L L IOWR# X H H H H OE# X H H H H WE# X H H H H D8 to D15 High-Z High-Z High-Z odd byte odd byte D0 to D7 High-Z even byte odd byte even byte High-Z Task File Register Write Access Mode (1) Mode Standby mode Byte access (8bit) Word access (16bit) Odd byte access (8bit) Note: X → L or H REG# X L L L L CE2# H H H L L CE1# H L L L H A0 X L H X X IORD# X H H H H IOWR# X L L L L OE# X H H H H WE# X H H H H D8 to D15 Don’t care Don’t care Don’t care odd byte odd byte D0 to D7 Don’t care even byte odd byte even byte Don’t care (2) Memory address map – Task File Register Read Access Mode (2) Mode Standby mode Byte access (8bit) Word access (16bit) Odd byte access (8bit) Note: X → L or H REG# X H H H H CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X L L L L WE# X H H H H IORD# X H H H H IOWR# X H H H H D8 to D15 High-Z High-Z High-Z odd byte odd byte D0 to D7 High-Z even byte odd byte even byte High-Z Task File Register Write Access Mode (2) Mode Standby mode Byte access (8bit) Word access (16bit) Odd byte access (8bit) Note: X → L or H REG# X H H H H CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X H H H H WE# X L L L L IORD# X H H H H IOWR# X H H H H D8 to D15 Don’t care Don’t care Don’t care odd byte odd byte D0 to D7 Don’t care even byte odd byte even byte Don’t care White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs 3. TRUE IDE MODE WED7PxxxATA70xxI25 The card can be configured in a True IDE. This card is configured in this mode only when the OE# input signal is asserted to GND by the host during power on . In this True IDE mode Attribute Registers are not accessible from the host. Only I/O operation to the task file and data register is allowed. If this card is configured during power on sequence, data register is accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature Command to put the device in 8-bit mode. True IDE Mode Read I/O Function Mode Invalid mode Standby mode PIO Data register access Multiword DMA Data register access Alternate status access Other task file access Note: X → L or H CE2# L H H H L H CE1# L H L H H L A0~A2 X X 0 X 6H 1~7H DMACK# X H H L H H DIOR# X X L L L L DIOW# X X H H H H D8~D15 High-Z High-Z Odd byte Odd byte High-Z High-Z D0~D7 High-Z High-Z even byte even byte Status out Data True IDE Mode Write I/O Function Mode Invalid mode Standby mode PIO Data register access Multiword DMA Data register access Control register access Other task file access Note: X → L or H CE2# L H H H L H CE1# L H L H H L A0~A2 X X 0 X 6H 1~7H DMACK# X H H L H H DIOR# X X H H H H DIOW# X X L L L L D8~D15 Don’t care Don’t care Odd byte Odd byte Don’t care Don’t care D0~D7 Don’t care Don’t care even byte even byte Control in Data CARD SYSTEM PERFORMANCE ITEM Set up time (Reset to Ready) Set up time (Power down to Ready) Data transfer rate to / from host Sustained read transfer rate Sustained write transfer rate Command to DRQ (Sector Re ad at Ready state) Command to DRQ (Sector Write at Ready state) Data transfer cycle end to ready (Sector write) Auto Power down time Notes: 1. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com PERFORMANCE 250 ms (max.) 5.5 ms (max.) 16.6 M byte / s burst (max.), theoretically 6.5 M byte / s (max.), actually *1 6.0 M byte / s (max.), actually *1 4 ms (max.) 700 ms (max.) 2 ms (typ.), 200 ms (max.) 1.5s (min.), 1.8s (typ.) White Electronic Designs ELECTRICAL SPECIFICATION SYMBOL VIN, VOUT VCC PARAMETER All input / output voltage Power Supply Voltage (Absolute Maximum Ratings) Power Supply Voltage (Recommended Operation Condition) Operating Temperature Storage Temperature MIN -0.3 -0.6 4.5 3.135 -40 -45 WED7PxxxATA70xxI25 MAX VCC+0.3 6.0 5.5 3.465 85 90 TYP — — 5.0 3.3 — — UNIT V V V V °C °C VCC TOPR TSTG Input Leakage Current Type IxZ IxU IxD SYMBOL IL RPU1 RPD1 PARAMETER Input leakage current Pull Up Resistor Pull Down Resister CONDITION VIH = Vcc / VIL = GND Vcc = 5.0V Vcc = 5.0V MIN -1 50 50 MAX 1 500 500 TYP — — — UNIT µA kΩ kΩ NOTES *1 *1 *1 Notes: 1. x refers to the characteristics described in section “DC Characteristics ( Input Characteristics)”. For example, I1U indicates a pull up resister with a type 1 input characteristics. Output Drive Type Type OTx OZx OPx ONx OUTPUT TYPE Totempole Tri-State N-P Channel P-Channel only N-Channel only VALID CONDITIONS IOH & IOL IOH & IOL IOH Only IOL Only NOTES *1 *1 *1 *1 Notes: 1. x refers to the characteristics described in section “DC Characteristics ( Output Drive Characteristics)”. Fo r example, OT1 refers to Totempole output with a type 1 Output drive characteristics. White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DC CHARACTERISTICS VCC = 3.3 V ± 5%, 5 V ± 0.5V, -40°C ≤ TA ≤ 85°C SYMBOL ILI ILO IPU IPD ICCS PARAMETER Input leakage current Output leakage current Pull-up current (Resistivity) Pull-down current (Resistivity) Power down mode current Operating current @ 3.3V Write operation Read operation Operating current @ 5V Write operation Read operation MIN — — — — — — — — — — MAX 1 1 — — 1.5 2.0 — — — — WED7PxxxATA70xxI25 TYP. — — 43 (75) -43 (75) 1.0 1.2 25 21 28 23 UNIT µA µA µA (kΩ) µA (kΩ) mA TEST CONDITIONS — VOUT = high impedance VFORCE = 3.3V VFORCE = 0V VCC = 3.3V VCC = 5V VCC = 3.3V operation mA ICCO mA VCC = 5V operation Input Characteristics Type 1 VIL VIH 2 VIL VT+ 3 VTVt VT+ 4 VTVt Input Low Voltage CMOS Input Low to High threshold Schmitt trigger Input High to Low threshold Schmitt trigger Hysteresis voltage Input Low to High threshold Schmitt trigger Input High to Low threshold Schmit trigger Hysteresis voltage Input Low Voltage CMOS Input High Voltage SYMBOL VIH PARAMETER Input High Voltage CMOS MIN 2.0 2.0 — 2.0 2.0 — — 0.9 0.9 0.5 0.8 — 1.0 0.8 0.5 0.8 MAX — 1.0 1.0 — 1.0 0.8 2.5 2.5 — TYP — — — — 2.1 2.1 1.2 1.2 UNIT CONDITION VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V V 2.3 2.0 2.1 1.8 1.2 1.1 Output Drive Characteristics Type 1 SYMBOL VOH VOL PARAMETER Output High Voltage Output Low Voltage MIN VCC - 0.8 — MAX — Gnd + 0.4 TYP — — UNIT V CONDITION IOH = -4mA IOL = 4mA White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS VCC = 3.3 V ± 5%, 5 V ± 0.5V, -40°C ≤ TA ≤ 85°C WED7PxxxATA70xxI25 Attribute Memory Read AC Characteristics SYMBOL tC tA tA tA tDIS tDIS tEN tEN tV tSU PARAMETER Read cycle time Address access time CE# access time OE# access time Output disable time (CE#) Output disable time (OE#) Output enable time (CE#) Output enable time (OE#) Data valid time (A) Address setup time MIN 250 — — — — — 5 5 0 30 MAX — 250 250 125 100 100 — — — — UNIT ns Attribute Memory Write AC Characteristics SYMBOL tC tW tSU tSU tH tREC PARAMETER Write cycle time Write pulse time Address setup time Data setup time (-WE) Data hold time Write recover time MIN 250 150 30 80 30 30 MAX — — — — — — UNIT ns I/O Access Read AC Characteristics SYMBOL tD tH tW tSUA tHA tSUCE tHCE tSUREG tHREG tDFINPACK tDRINPACK tDFIOIS16 tDRIOIS16 PARAMETER Data delay after IORD# Data hold following IORD# IORD# pulse width Address setup before IORD# Address hold following IORD# CE# setup before IORD# CE# hold following IORD# REG# setup before IORD# REG# hold following -IORD INPACK# delay failing from IORD# INPACK# delay rising from IORD# IOIS#16 delay failing from address IOIS#16 delay rising from address MIN — 0 165 70 20 5 20 5 0 0 — — — MAX 100 — — — — — — — — 45 45 35 35 UNIT ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs SYMBOL tSU tH tW tSUA tHA tSUCE tHCE tSUREG tHREG tDFIOIS16 tDRIOIS16 PARAMETER Data setup before IOWR# Data hold following IOWR# IOWR# pulse width Address setup before IOWR# Address hold following IOWR# CE# setup before IOWR# CE# hold following IOWR# REG# setup before IOWR# REG# hold following IOWR# IOIS16# delay failing from address IOIS16# delay rising from address MIN 60 30 165 70 20 5 20 5 0 — — WED7PxxxATA70xxI25 I/O Access Write AC Characteristics MAX — — — — — — — — — 35 35 UNIT ns Common Memory Access Read AC Characteristics SYMBOL tA tDIS tSU tH tSU tH PARAMETER OE# access time Output disable time (OE#) Address setup time Address hold time CE# setup before OE# OE# hold following OE# MIN — — 30 20 0 20 MAX 125 100 — — — — UNIT ns Common Memory Access Write AC Characteristics SYMBOL tSU tH tW tH tSU tSU tREC tH PARAMETER Data setup before WE# Data hold following WE# Write pulse width Address hold time Address setup time CE# setup time Write recover time CE# hold following WE# MIN 80 30 150 20 30 0 30 20 MAX — — — — — — — — UNIT ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs SYMBOL t0 t1 t2 t2 t2i t3 t4 t5 t6 t6z t7 t8 t9 PARAMETER Cycle time Address valid to -DIOW/-DIOR setup DIOW#/-DIOR DIOW#/-DIOR Register (8bit) DIOW#/-DIOR recoverry time DIOW# data setup DIOW# data hold DIOR# data setup DIOR# data hold DIOR# data tristate Address valid to -IOIS16 assertion Address valid to -IOIS16 released DIOW#/-DIOR to address valid hold MIN 120 25 70 70 25 20 10 20 5 — — — 10 WED7PxxxATA70xxI25 True IDE Mode IO Read/Write AC Characteristics MAX — — — — — — — — — 30 35 35 — UNIT ns True IDE Mode Multiword DMA Read/Write AC Characteristics SYMBOL t0 tD tE tF tG tH tI tJ tKR tKW tLR tLW tM tN tZ PARAMETER Cycle time DIOR#/DIOW# assert width DIOR# data access DIOR# data hold DIOW#/DIOR# data setup DIOW# data hold DMACK# to DIOR#/DIOW# setup DIOR#/DIOW# to DMACK hold DIOR# negated width DIOW# negated width DIOR# to DMARQ delay DIOW# to DMARQ delay CS0#/CS1# valid to -DIOR#/-DIOW# CS0#/CS1# hold DMACK# to read data released MIN 120 70 — 5 20 10 0 5 25 25 — — 25 10 — MAX — — 50 — — — — — — — 35 35 — — 25 UNIT ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED7PxxxATA70xxI25 Reset Characteristics (only Memory Card Mode or I/O Card Mode) SYMBOL tSU tREC tPR tPF tW tH tS Reset pulse width PARAMETER Reset setup time CE# recover time VCC rising up time VCC falling down time MIN 100 1 0.1 3 10 1 0 MAX — — 100 300 — — — UNIT ms µs ms ms µs ms ms Power on Reset Characteristics Power on reset sequence must need by PORST# at the rising edge of VCC. SYMBOL tSU tPR PARAMETER CE# setup time VCC rising up time MIN 100 0.1 MAX — 100 UNIT ms ms White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE DIMENSIONS WED7PxxxATA70xxI25 Type II 1.6mm ± 0.05 (0.063”) 85.6mm ± 0.20 (3.370”) 3.0mm MIN (0.118”) 1.0mm ± 0.05 (0.039”) Substrate area 54.0mm ± 0.10 (2.126”) 1.0mm ± 0.05 (0.039”) 10.0mm MIN (0.400”) 5.0mm ± T1 (0.197”) Interconnect area 3.3mm ± 0.10 (0.129”) White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ATTENTION FOR CARD USE • • • • • • WED7PxxxATA70xxI25 In the reset or power off mode, the information in all registers are cleared. Note that the card insertion/removal should not be executed while host is active if the card is used in True IDE mode. After the hard reset, soft reset or power-on reset or ATA reset command is applied the card cannot be accessed while READY pin is “low.” Flash card can’t be operated in this mode. Before insertion VCC cannot be supplied to the card. After confirmation that CD1#, CD2# pins are set, VCC may be supplied to the card. OE# must be kept at the VCC level during power on reset in memory card mode and I/O card mode. OE must be kept constantly at the GND level in True IDE mode. Do not turn off the power or remove WED7PxxxATA70xxI25 Series from the slot before read/write operation is complete. Avoid using WED7PxxxATA70xxI25 Series when the battery is low. Power shortage, power failure and/or removal of WED7PxxxATA70xxI25 Series from the slot before read/write operation is complete may cause malfunction of WED7PxxxATA70xxI25 Series, data loss and/or damage to data. Routine performance of backing-up data (or taking back-up of data) is strongly recommended. • White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED7PxxxATA70xxI25 PART NUMBERING GUIDE WED 7P xxx ATA 70 xx I 25 WEDC Flash Memory Size ATA Flash Industrial Flash Housing: 03 = WEDC Logo 04 = Blank Housing Enhanced Industrial Temp Speed White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Document Title 128MB to 1GB Industrial ATA Flash WED7PxxxATA70xxI25 Revision History Rev # Rev 0 History Initial Release Release Date March 2005 Status Final Rev 1 1.1 Added "ED" to part marking July 2005 Final White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com