WV3HG64M72EER665D6SG

White Electronic Designs WV3HG64M72EER-D6 ADVANCED* 512MB – 64Mx72 DDR2 SDRAM REGISTERED DIMM, w/PLL FEATURES Registered 240-pin, dual in-line memory module Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 MT/s DDR2 SDRAM components VCC = VCCQ = 1.8V ± 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Write Latency = Read Latency 1tck Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-die termination (ODT) 7.8µs average periodic refresh interval Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM Auto & Self Refresh (8k/64ms refresh) Gold edge contacts RoHS compliant Package option • 240 Pin DIMM • PCB – 30.00mm (1.181") TYP DESCRIPTION The WV3HG64M72EER is a 64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of nine 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 240-pin DIMM FR4 substrate. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES PC2-3200 Clock Speed CL-tRCD-tRP * Consult factory for availability PC2-4200 266MHz 4-4-4 PC2-5300* 333MHz 5-5-5 PC2-6400* 400MHz 6-6-6 200MHz 3-3-3 August 2006 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VCC CKE0 VCC NC NC VCC A11 A7 VCC A5 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol A4 VCC A2 VCC VSS VSS VCC NC VCC A10/AP BA0 VCC WE# CAS# VCC NC NC VCC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DM0/DQS9 NC/DQS9# VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 NC/DQS10# VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 NC/DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 NC/DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8/DQS17 NC/DQS17# VSS CB6 CB7 VSS VCC NC VCC NC NC VCC A12 A9 VCC A8 A6 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCC A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCC RAS# CS0# VCC ODT0 A13 VCC VSS DQ36 DQ37 VSS DM4/DQS13 NC/DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 NC/DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6/DQS15 NC/DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC/DQS16# VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 2 WV3HG64M72EER-D6 ADVANCED PIN NAMES Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS17 DQS0#-DQS17# DM0 - DM8 ODT0 CK0,CK0# CKE0 CS0# RAS# CAS# WE# RESET# VCC VSS SA0-SA2 SDA SCL VREF VCCSPD NC Function Address Inputs SDRAM Bank Addresses Data Input/Output Check Bits Data strobes Data strobes complement Data Masks On-die termination control Clock Inputs Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Register Reset Input/PLL OE Core and I/O Power (1.8V) Ground SPD address SPD Data Input/Output Serial Presence Detect(SPD) Clock Input Input/Output Reference Voltage SPD Power Spare pins, No connect August 2006 Rev. 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM RCS0# DQS0 DQS0# DM0/DQS9 NC/DQS9# DM/ RDQS NU/ CS# DQS DQS# RDQS# WV3HG64M72EER-D6 ADVANCED DQS4 DQS4# DM4/DQS13 NC/DQS13# DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DM1/DQS10 NC/DQS10# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5# DM5/DQS14 NC/DQS14# DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DM2/DQS11 NC/DSS11# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6# DM6/DQS15 NC/DQS15# DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3# DM3/DQS12 NC/DSS12# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7# DM7/DQS16 NC/DQS16# DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS NU/ CS# DQS DQS# RDQS# Serial PD SCL WP A0 A1 A2 SDA DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8# DM8/DQS17 NC/DSS17# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SA0 SA1 SA2 DM/ RDQS NU/ CS# DQS DQS# RDQS# VCCSPD VCC/VCCQ VREF VSS Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS0# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 ODT0 RESET#** PCK7** PCK7#** 1:2 R E G I S T E R RST# CK0 RCS0# : DDR2 SDRAMs RBA0 - RBA1 : DDR2 SDRAMs RA0 - RA13 : DDR2 SDRAMs RRAS# : DDR2 SDRAMs RCAS# : DDR2 SDRAMs RWE# : DDR2 SDRAMs RCKE0 : DDR2 SDRAMs RODT0 : DDR2 SDRAMs CK0# RESET# P L L OE PCK0-PCK6, PCK8, PCK9 CK : DDR2 SDRAMs CK# : DDR2 SDRAMs PCK0#-PCK6#, PCK8#, PCK9# PCK7 CK : Register PCK7# CK# : Register NOTE: All resistor values are 22 ohms unless otherwise specified. **RESET#, PCK7 and RCK7# connects both registers. Other signals connect to one of two registers. August 2006 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage SPD Supply Voltage Symbol VCC VREF VTT VCCSPD Min 1.7 0.49 x VCC VREF-0.04 1.7 Typical 1.8 0.50 x VCC VREF - WV3HG64M72EER-D6 ADVANCED Max 1.9 0.51 x VCC VREF+0.04 3.6 Unit V V V V Notes 3 1 2 Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC. ABSOLUTE MAXIMUM RATINGS Symbol VCC VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Input leakage current: Any input 0V