W25Q512NWEIM

W25Q512NW-DTR 1.8V 512M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI, QPI & DTR -1- Publication Release Date: July 19, 2021 - Revision B W25Q512NW-DTR Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 6 2. FEATURES ....................................................................................................................................... 6 3. PACKAGE TYPES AND PIN CONFIGURATIONS........................................................................... 7 3.1 Pad Configuration 6x5-mm/ 8x6-mm.................................................................................... 7 3.2 Pad Description WSON 6x5-mm / 8x6-mm ......................................................................... 7 Pin Configuration SOIC 300-mil ........................................................................................................ 8 4. 3.3 Pin Description SOIC 300-mil ............................................................................................... 8 3.4 Ball Configuration TFBGA 8x6-mm (5x5 Ball Array) ............................................................ 9 3.5 Ball Description TFBGA 8x6-mm ......................................................................................... 9 3.6 Ball Configuration WLCSP ................................................................................................. 10 3.7 Ball Description WLCSP88 ................................................................................................. 10 PIN DESCRIPTIONS ...................................................................................................................... 11 4.1 Chip Select (/CS) ................................................................................................................ 11 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ................................... 11 4.3 Write Protect (/WP) ............................................................................................................ 11 4.4 HOLD (/HOLD) ................................................................................................................... 11 4.5 Serial Clock (CLK) .............................................................................................................. 11 4.6 Reset (/RESET) .................................................................................................................. 11 5. BLOCK DIAGRAM .......................................................................................................................... 12 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 13 6.1 6.2 7. SPI / QPI Operations .......................................................................................................... 13 6.1.1 Standard SPI Instructions ..................................................................................................... 13 6.1.2 Dual SPI Instructions ............................................................................................................ 13 6.1.3 Quad SPI Instructions ........................................................................................................... 14 6.1.4 QPI Instructions .................................................................................................................... 14 6.1.5 SPI / QPI DTR Read Instructions ......................................................................................... 14 6.1.6 3-Byte / 4-Byte Address Modes ............................................................................................ 14 6.1.7 Hold Function ....................................................................................................................... 15 6.1.8 Software Reset & Hardware /RESET pin .............................................................................. 15 Write Protection .................................................................................................................. 16 STATUS AND CONFIGURATION REGISTERS ............................................................................ 17 7.1 Status Registers ................................................................................................................. 17 7.1.1 Program/Erase/Write In Progress (BUSY) – Status Only ..................................................... 17 7.1.2 Write Enable Latch (WEL) – Status Only ............................................................................. 17 7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) – Volatile/Non-Volatile Writable .......................... 18 7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable .......................................... 18 7.1.5 Complement Protect (CMP) – Volatile/Non-Volatile Writable ............................................... 18 7.1.6 Status Register Protect (SRP, SRL) – Volatile/Non-Volatile Writable .................................. 18 7.1.7 Erase/Program Suspend Status (SUS) – Status Only .......................................................... 19 -2- Publication Release Date: July 19, 2021 - Revision B W25Q512NW-DTR 7.2 8. 7.1.8 Security Register Lock Bits (LB3, LB2, LB1, SFDP Lock bit) – Non-Volatile OTP Writable . 19 7.1.9 Quad Enable (QE) – Volatile/Non-Volatile Writable ............................................................. 19 7.1.10 Current Address Mode (ADS) – Status Only ...................................................................... 20 7.1.11 Power-Up Address Mode (ADP) – Non-Volatile Writable ................................................... 20 7.1.12 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable ........................................ 20 7.1.13 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ............................. 21 7.1.14 /HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable .................. 21 7.1.15 Reserved Bits – Non Functional ......................................................................................... 21 7.1.16 W25Q512NW Status Register Memory Protection (WPS = 0, CMP = 0) ........................... 22 7.1.17 W25Q512NW Status Register Memory Protection (WPS = 0, CMP = 1) ........................... 23 7.1.18 W25Q512NW Individual Block Memory Protection (WPS=1) ............................................ 24 Extended Address Register – Volatile Writable Only ......................................................... 25 INSTRUCTIONS ............................................................................................................................. 26 8.1 Device ID and Instruction Set Tables ................................................................................. 26 8.1.1 Manufacturer and Device Identification ................................................................................ 26 8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte Address Mode ADS=0)(1) ........... 27 8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode ADS=0) ........... 28 8.1.4 Instruction Set Table 3 (Standard SPI, 4-Byte Address Mode ADS=1)(1) ............................. 29 8.1.5 Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode ADS=1) .......... 30 8.1.6 Instruction Set Table 5 (QPI Instructions, 3-Byte Address Mode) ........................................ 31 8.1.7 Instruction Set Table 6 (QPI Instructions, 4-Byte Address Mode) ........................................ 32 8.1.8 Instruction Set Table 7 (DTR with SPI Instructions, 3-Byte Address Mode) ......................... 33 8.1.9 Instruction Set Table 8 (DTR with SPI Instructions, 4-Byte Address Mode) ......................... 33 8.1.10 Instruction Set Table 9 (DTR with QPI Instructions, 3-Byte Address Mode)....................... 33 8.1.11 Instruction Set Table 10 (DTR with QPI Instructions, 4-Byte Address Mode)..................... 33 Notes:................................................................................................................................................ 34 8.2 Instruction Descriptions ...................................................................................................... 35 8.2.1 Write Enable (06h) ............................................................................................................... 35 8.2.2 Write Enable for Volatile Status Register (50h) .................................................................... 35 8.2.3 Write Disable (04h) ............................................................................................................... 36 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 36 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 37 8.2.6 Read Extended Address Register (C8h) .............................................................................. 40 8.2.7 Write Extended Address Register (C5h) .............................................................................. 41 8.2.8 Enter 4-Byte Address Mode (B7h) ........................................................................................ 42 8.2.9 Exit 4-Byte Address Mode (E9h) .......................................................................................... 42 8.2.10 Read Data (03h) ................................................................................................................. 43 8.2.11 Read Data with 4-Byte Address (13h) ................................................................................ 44 8.2.12 Fast Read (0Bh) ................................................................................................................. 45 8.2.13 DTR Fast Read (0Dh) ......................................................................................................... 47 8.2.14 Fast Read with 4-Byte Address (0Ch) ................................................................................ 49 8.2.15 Fast Read Dual Output (3Bh) ............................................................................................. 50 8.2.16 Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 51 8.2.17 Fast Read Quad Output (6Bh) ............................................................................................ 52 -3- Publication Release Date: July 19, 2021 - Revision B W25Q512NW-DTR 9. 8.2.18 Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 53 8.2.19 Fast Read Dual I/O (BBh) ................................................................................................... 54 8.2.20 DTR Fast Read Dual I/O (BDh) .......................................................................................... 56 8.2.21 Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 58 8.2.22 Fast Read Quad I/O (EBh) ................................................................................................. 60 8.2.23 DTR Fast Read Quad I/O (EDh) ......................................................................................... 64 8.2.24 Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 67 8.2.25 Set Burst with Wrap (77h) .................................................................................................. 69 8.2.26 Set Read Parameters (C0h) ............................................................................................... 70 8.2.27 Burst Read with Wrap (0Ch)............................................................................................... 73 8.2.28 DTR Burst Read with Wrap (0Eh) ...................................................................................... 74 8.2.29 Page Program (02h) ........................................................................................................... 75 8.2.30 Page Program with 4-Byte Address (12h) .......................................................................... 77 8.2.31 Quad Input Page Program (32h) ........................................................................................ 78 8.2.32 Quad Input Page Program with 4-Byte Address (34h) ....................................................... 79 8.2.33 Sector Erase (20h) ............................................................................................................. 80 8.2.34 Sector Erase with 4-Byte Address (21h)............................................................................. 81 8.2.35 32KB Block Erase (52h) ..................................................................................................... 82 8.2.36 64KB Block Erase (D8h) ..................................................................................................... 83 8.2.37 64KB Block Erase with 4-Byte Address (DCh) ................................................................... 84 8.2.38 Chip Erase (C7h / 60h) ....................................................................................................... 85 8.2.39 Erase / Program Suspend (75h) ......................................................................................... 86 8.2.40 Erase / Program Resume (7Ah) ......................................................................................... 88 8.2.41 Power-down (B9h) .............................................................................................................. 89 8.2.42 Release Power-down / Device ID (ABh) ............................................................................. 90 8.2.1 Read Manufacturer / Device ID (90h) ................................................................................... 92 8.2.2 Read Manufacturer / Device ID Dual I/O (92h) ..................................................................... 93 8.2.3 Read Manufacturer / Device ID Quad I/O (94h) ................................................................... 94 8.2.4 Read Unique ID Number (4Bh)............................................................................................. 95 8.2.5 Read JEDEC ID (9Fh) .......................................................................................................... 96 8.2.6 Read SFDP Register (5Ah) .................................................................................................. 97 8.2.7 Erase Security Registers (44h) ............................................................................................. 98 8.2.8 Program Security Registers (42h) ........................................................................................ 99 8.2.9 Read Security Registers (48h) ........................................................................................... 100 8.2.10 Enter QPI Mode (38h)....................................................................................................... 101 8.2.11 Exit QPI Mode (FFh) ......................................................................................................... 102 8.2.12 Individual Block/Sector Lock (36h) ................................................................................... 103 8.2.13 Individual Block/Sector Unlock (39h) ................................................................................ 104 8.2.14 Read Block/Sector Lock (3Dh) ......................................................................................... 105 8.2.15 Global Block/Sector Lock (7Eh) ........................................................................................ 106 8.2.16 Global Block/Sector Unlock (98h) ..................................................................................... 106 8.2.17 Enable Reset (66h) and Reset Device (99h) .................................................................... 107 ELECTRICAL CHARACTERISTICS ............................................................................................. 108 9.1 Absolute Maximum Ratings (1) ........................................................................................ 108 -4- Publication Release Date: July 19, 2021 - Revision B W25Q512NW-DTR 9.2 Operating Ranges............................................................................................................. 108 9.3 Power-up Power-down Timing and Requirements ........................................................... 109 9.3.1 Power Cycle Requirement .................................................................................................. 110 9.4 DC Electrical Characteristics ............................................................................................ 111 9.5 AC Measurement Conditions ............................................................................................ 112 9.6 AC Electrical Characteristics ............................................................................................ 113 Continued – next page .................................................................................................................. 113 AC Electrical Characteristics (cont’d)............................................................................................ 114 10. 11. 9.7 Serial Output Timing ......................................................................................................... 115 9.8 Serial Input Timing ............................................................................................................ 115 9.9 /HOLD Timing ................................................................................................................... 115 9.10 /WP Timing ....................................................................................................................... 115 PACKAGE SPECIFICATIONS ...................................................................................................... 116 10.1 8-Pad WSON 8x6-mm (Package Code E) ....................................................................... 116 10.2 16-Pin SOIC 300-mil (Package Code F) .......................................................................... 117 10.3 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) ......................................... 118 10.4 102-Ball WLCSP (Package Code Y) ................................................................................ 119 10.5 Ordering Information......................................................................................................... 120 10.6 Valid Part Numbers and Top Side Marking ...................................................................... 121 REVISION HISTORY .................................................................................................................... 122 -5- Publication Release Date: July 19, 2021 - Revision B W25Q512NW-DTR 1. GENERAL DESCRIPTIONS The W25Q512NW (512M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 1.65V to 1.95V power supply with current consumption as low as 0.3µA for power-down. All devices are offered in space-saving packages. The W25Q512NW array is organized into 262,144 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q512JV has 16,384 erasable 4KB sectors and 1,028 erasable 64KB blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. The W25Q512NW support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI, Quad Peripheral Interface (QPI) as well as Double Transfer Rate (DTR): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers. 2. FEATURES  New Family of SpiFlash Memories – W25Q512NW: 512M-bit / 32M-byte – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – SPI/QPI DTR (Double Transfer Rate) Read – 3 or 4-Byte Addressing Mode – Software & Hardware Reset(1)  Highest Performance Serial Flash – 133MHz Standard/Dual/Quad SPI clocks – 266/532MHz equivalent Dual/Quad SPI – 66MB/S continuous data transfer rate – Min. 100K Program-Erase cycles – More than 20-year data retention  Low Power, Wide Temperature Range – Single 1.65V to 1.95V supply –