W682388

W682388 Layout Guideline Rev 1.3 - AN-CS006a W682388 Pro-X™ CODEC Layout Guideline 1. W682388 Layout Considerations The Winbond W682388 Pro-X™ CODEC family is an excellent solution for short loop telephony applications. Place the components carefully to insure best performance. This document outlines critical component layout issues. Use it together with the W682388 data sheet and other supporting Pro-X application notes. The W682388 will exhibit high-quality low-noise performance with the appropriate layout design. Pins 52–61 are sensitive current input pins that are susceptible to induced noise. Keep traces between these pins and their respective components (C7, C8, C10, C11, R13–16, and R18–27) to a minimum length. Do not route any digital traces near these sensitive traces. Place the line compensation capacitors, C5, C8, C9, and C12, near their respective TIP and RING output pins. Place a 0.1 µF ceramic decoupling capacitor as close as possible to each VDD and VBAT power supply input pin. These are Pin 49 (VDD1), Pin 64 (VDD2), Pin 41 (VDD3), Pin 8 (VDD4), Pin 27 (VDD5) and Pin 26 (VDDL). Replace the 0.1 µF capacitors at VDD1 and VDD2 with 10 µF ceramic capacitors for additional noise performance. Refer to the Figure 3 for an example of this layout. There are two external Tip and Ring capacitors for each channel. They are connected to CT1 (Pin 39), CR1 (Pin 38), CT2 (Pin 10), and CR2 (Pin 11). The capacitor is a 10 µF ceramic (low leakage) capacitor. It is connected to 3.3V. Route the capacitors directly to the appropriate VDD pin. For example, the CT1 and CR1 capacitors connect directly to their respective pins. Their shared 3.3V connection is routed directly to VDD1 before connecting to the main 3.3V supply. The situation is the same for CT2 and CR2, which must terminate at VDD2. The AFE transistors QR3/QT3 (SOT-223) and QR1/QT1 (SOT-89) should have exposed copper pads to help reduce the thermal resistance of these components. The amount of copper used for the heat sink in combination with the surface area of the PCB will improve the heat dissipation of the transistor package. One way to increase the copper area when board space is limited is to connect the pad used for the heat sink by using multiple layers. A top and bottom side can be used with multiple vias connecting them together. The optimal copper area to heat sink a SOT-223 is 1 sq inch. This approach is similar to heat sinking used for the QFN package. (Refer to Section 4 on QFN grounding) Place the resistors for IREF (Pin 13) and the transconductance amplifiers (Pins 3,5,44 and 46) as close as possible to the part to minimize the trace length. These resistors are R29, R30 and R31. If more than two layers are used for the overall board circuit, separate analog and digital trace layers may enhance performance. Digital signals are best applied to a dedicated layer. The ideal approach is to separate digital layers from analog layers by a power/ground plane. AN-CS006a_W682388 PCB Layout.doc Page 1 of 8 W682388 Layout Guideline Rev 1.3 Idle Channel Noise (ICN) performance can be further improved by splitting the 3.3V power plane. This way the front end power (VDD1 – VDD4) and ground (GND1 – GND4 & VSSP) will be isolated from the main 3.3V and Ground planes by using ferrite beads. 2. DC-TO-DC Converter Layout The W682388 DC-to-DC converter circuit uses pulse width modulation to generate the desired voltages. Lay out this circuit carefully to minimize the contributed noise from the high switching currents. The DC-to-DC converter has specific areas to optimize to minimize this noise effect. The critical areas are described below: Loop 1 in Figure 1 is the secondary fly-back current path that generates the negative VBAT potential. Place the components in this area in a tight loop. Cover the open areas in between with as much copper as possible. Loop 2 in Figure 1 is the primary input current loop for the DC-to-DC converter from the unregulated power supply. Place the capacitors in this area near the sense resistor to maximize results. DCH1 R41 (Rdh) 56.2K Voltage Sense Resistors (Rdh and Rdl) DC_IN_CH1 DC_UNREG R45 200 R42 (Rdl) 56.2K R38(Ris) 0.56 Current Sense Resistor (Ris) C36 0.1UF 100V C31 10UF 25V DCL1 3 DCP1 1 Q16 ZX5T955G INDP1 Loop 2 BAT1 C29 10UF 100V BAT1 3 2 4 D4 ES1D L 150UH DCN1 2 Q18 2N2222 1 R39 (Re1) 200 C34 0.1UF 100V Loop 1 Single point connection to Ground Figure 1. DC-to-DC Converter Circuit AN-CS006a_W682388 PCB Layout.doc Page 2 of 8 W682388 Layout Guideline Rev 1.3 DC-to-DC converter layout recommendations: 1) The perimeters of loops (1) & (2) must be as short as possible. 2) The high current paths must use large trace widths: typically WVDC>WVBAT>5 mm [200 mils.] 3) The Ground connection should be extended with multiple vias (3) in the case of inner layer or bottom layer ground plane (WVIAS