W83194BR-323

W83194BR-323/W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET Date: 03/22/2006 Revision: 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET W83194BR-323 Data Sheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 2 3 4 5 6 7 8 9 10 n.a. n.a. P13 All 13/May 02/August 02/20/2003 03/22/2006 1.0 1.1 2.0 2.1 n.a. n.a 1.1 2.0 All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 Delete Test mode register. Update new form Add lead free part number --- W83194BG-323 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -I- Publication Release Date: March 2006 Revision 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET Table of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 BLOCK DIAGRAM ...................................................................................................................... 2 PIN CONFIGURATION ............................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 5.2 5.3 5.4 5.5 6. 7. Crystal I/O.................................................................................................................................3 CPU, 3V66, and PCI Clock Outputs........................................................................................3 I2C Control Interface .................................................................................................................4 Fixed Frequency Outputs.........................................................................................................4 Power Pins................................................................................................................................5 FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 6 I2C CONTROL AND STATUS REGISTERS .............................................................................. 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 Register 0: Frequency Select Register (default = 0)...............................................................7 Register 1: CPU Clock Register (1 = enable, 0 = Stopped) ...................................................7 Register 2: PCI Clock Register (1 = enable, 0 = Stopped) .....................................................7 Register 3: PCI, 48MHz Clock Register (1 = enable, 0 = Stopped) .......................................8 Register 4: 3V66 Control Register (1 = enable, 0 = Stopped)................................................8 Register 5: Watchdog Control Register...................................................................................8 Register 6: Watchdog Timer Register .....................................................................................9 Register 7: M/N Program Register ..........................................................................................9 Register 8: M/N Program Register ..........................................................................................9 Register 9: Spread Spectrum Programming Register ..........................................................10 Register 10: Divisor and Step-less Enable and Skew Control Register...............................10 Register 11: Winbond Chip ID Register (Read Only).........................................................11 Register 12: Winbond Chip ID Register (Read Only).........................................................11 Register 13: Reserved ...........................................................................................................11 Register 14: CPU to PCI Skew Control .................................................................................12 Register 15: SEL24_48 and SEL48_66 Control ...................................................................12 Block Write protocol ...............................................................................................................13 Block Read protocol ...............................................................................................................13 Byte Write protocol .................................................................................................................13 Byte Read protocol.................................................................................................................13 8. ACCESS INTERFACE .............................................................................................................. 13 8.1 8.2 8.3 8.4 9. 10. 11. ORDERING INFORMATION..................................................................................................... 14 HOW TO READ THE TOP MARKING...................................................................................... 14 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 15 - II - W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 1. GENERAL DESCRIPTION The W83194BR-323 is a Clock Synthesizer for Intel Brook dale 845 chipset. W83194BR-323 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and 3V66 clocks setting. All clocks are externally selectable with smooth transitions. The W83194BR-323 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-323 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-323 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. The fixed frequency outputs as REF and 48 MHz provide better than 0.5V /ns slew rate. 2. PRODUCT FEATURES 3 Differential pairs of CPU clock outputs • 4 3V66 clock outputs • 10 PCI synchronous clocks • 24_48Mhz clock output for super I/O. • 48 MHz clock output for USB. • Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns • Smooth frequency switch with selections from 66.8 to 200MHz • Step-less frequency programming • I2C 2-Wire serial interface and support byte read/write and block read/write. • -0.5% and +/- 0.25% center type spread spectrum • Programmable S.S.T. scale to reduce EMI • Programmable registers to enable/stop each output and select modes • Watch Dog Timer and RESET# output pins • 48-pin SSOP package -1- Publication Release Date: March 2006 Revision 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 3. BLOCK DIAGRAM Driver 48MHz PLL2 1/2 Mux 24_48MHz XIN XOUT XTAL OSC VCOCLK 2 REF0:1 PLL1 Spread Spectrum Divider /2,/4,/8,/16 3 Stop 3 CPUCLK_T 0:2 CPUCLK_C 0:2 M/N/Ratio S.S.P ROM VTTPWRGD# FS Latch & POR /3,/6,/12 /5,/10,/20 /7,/14 /9,/18 Stop 4 3V66_0:3 1 0 PCICLK_F0:2 PCICLK_0:6 PD# PCI_STOP# CPU_STOP# MULTISEL 0:1 2 Control Logic & Config Register I2C interface RESET# Rref *SDATA *SDCLK 4. PIN CONFIGURATION *MULTSEL1/REF1 VDDREF Xin Xout GND PCICLK_F0/*FS2 PCICLK_F1/*FS3 PCICLK_F2/&SEL24_4 8 VDDPCI PCICLK0/*FS4 PCICLK1 PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDPCI VTTPWRGD# RESET# GND 48MHz/*FS0 24_48MHz/*FS1 VDD48 1 2 3 4 5 6 7 8 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 *MULTSEL0/REF0 GND VDDCPU CPUCLK_T2 CPUCLK_C2 GND *PD# CPUCLK_T0 CPUCLK_C0 VDDCPU CPUCLK_T1 CPUCLK_C1 GND IREF VDDCORE GND VDD3V66 3V66_0 3V66_1 GND 3V66_2 3V66_3 / 48MHz /*SEL48_66 *SDCLK *SDATA * :internal 120K pull-up &:internal 120K pull-down #: active low -2- W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 5. PIN DESCRIPTION BUFFER TYPE SYMBOL DESCRIPTION IN INtd120k OUT OD I/O I/OD # * & Input Input pin and internal 120K pull down Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain Active Low Internal 120kΩ pull-up Internal 120kΩ pull-down 5.1 Crystal I/O PIN PIN NAME TYPE DESCRIPTION 3 4 XIN XOUT IN OUT Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). 5.2 CPU, 3V66, and PCI Clock Outputs PIN PIN NAME TYPE DESCRIPTION 41,38, 40,37 45,44 31,30,28 27 CPUCLK_T [0:2] CPUCLK_C [0:2] 3V66_0:2 3V66_3 / 48MHz *SEL48_66 OUT Low skew (< 250ps) differential clock outputs for host frequencies of CPU and chipset. 　 3.3V 66MHz clock outputs. OUT 35 IREF 20 RESET# OUT 　 3V66_3 or 48MHz clock output. INtp120k Latched input for 48MHz or 66MHz select pin. This is internal 120K pull up default 66MHz. In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 16 bit 6. IN 　 Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are several modes to select different current via power on trapping the Pin 1 & 48 (MULTISEL0, 1). The table is show as follows. OD System reset signal when the watchdog is time out. This pin will generate 250ms low phase when the watchdog timer is timeout. IN Power good input signal comes from ACPI with low active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL0, MULTISEL1, input are valid and is ready to sampled. This pin is low active. Publication Release Date: March 2006 Revision 2.1 19 VTTPWRGD# -3- W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET CPU, 3V66, and PCI Clock Outputs, continued PIN PIN NAME TYPE DESCRIPTION 42 6 7 PD# PCICLK_F0 *FS2 PCICLK_F1 *FS3 PCICLK_F2 &SEL24_48 PCICLK0 *FS4 IN OUT INtp120k OUT INtp120k Power Down Function. This is power down pin, low active (PD#). Internal 120K pull up 3.3V free running PCI clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. 3.3V free running PCI clock output. Latched input for FS3 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. 8 10 OUT 3.3V free running PCI clock outputs. INtd120k Latched input for 24MHz or 48MHz select pin. This is internal 120K pull down default 24MHz. OUT Low skew (< 250ps) PCI clock outputs. INtP120k Latched input for FS4 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. OUT Low skew (< 250ps) PCI clock outputs. 11, 12, 14, PCICLK [1:6] 15, 16, 17 5.3 I2C Control Interface PIN 25 26 Pin Name Type SDATA* SCLK* I/OD IN Description Serial data of I C 2-wire control interface with internal pullup resistor. Serial clock of I2C 2-wire control interface with internal pullup resistor. 2 5.4 Fixed Frequency Outputs PIN PIN NAME TYPE DESCRIPTION 48 REF0 MULTSEL0* REF1 MULTSEL1* 48MHz *FS0 24_48MHz *FS1 1 22 23 OUT 14.318NHz output. INtp120k Latched input for MULTSEL0 at initial power up, internal 120K pull up OUT 14.318NHz output. INtp120k Latched input for MULTSEL1 at initial power up, internal 120K pull up OUT 48MHz clock output for USB. INtp120k Latched input for FS0 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. OUT 24(default) or 48MHz clock output, In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 16 bit 7. INtp120k Latched input for FS1 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. -4- W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 5.5 Power Pins PIN PIN NAME TYPE DESCRIPTION 2 9,18 32 39,46 34 24 5, 13, 21, 29, 33, 36, 43, 47 VDDREF VDDPCI VDD3V66 VDDCPU VDDCORE VDD48 GND PWR PWR PWR PWR PWR PWR PWR 3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for 3V66. 3.3V power supply for CPU. 3.3V power supply for analog core. Analog power 3.3V for 48MHz. Ground pin for 3.3 V Hardware MULTSEL [1:0] selects Function MULTSEL1 MULTSEL0 BOARD TARGET TRACE/TERM Z REFERENCE R,IREF = VDD/(3*RR) OUTPUT CURRENT VOH @ Z 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω 50 Ω 60 Ω Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Ioh=4*IREF Ioh=4*IREF Ioh=5*IREF Ioh=5*IREF Ioh=6*IREF Ioh=6*IREF Ioh=7*IREF Ioh=7*IREF Ioh=4*IREF Ioh=4*IREF Ioh=5*IREF Ioh=5*IREF Ioh=6*IREF Ioh=6*IREF Ioh=7*IREF Ioh=6*IREF 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 50 0.47V @ 50 0.56V @ 50 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60 -5- Publication Release Date: March 2006 Revision 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 6 ~ 2). FS4 FS3 FS2 FS1 FS0 CPU (MHZ) 3V66(MHZ) PCI (MHZ) SPREAD % 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 102.0 105.0 108.0 111.0 114.0 117.0 120.0 123.0 126.0 130.0 136.0 140.0 144.0 148.0 152.0 156.0 160.0 164.0 166.6 170.0 175.0 180.0 185.0 190.0 66.8 100.2 133.6 200.4 66.6 100.0 200.0 133.3 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 63.0 65.0 68.0 70.0 72.0 74.0 76.0 78.0 80.0 82.0 66.6 68.0 70.0 72.0 74.0 76.0 66.8 66.8 66.8 66.8 66.6 66.6 66.6 66.6 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 31.5 32.5 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 33.3 34.0 35.0 36.0 37.0 38.0 33.4 33.4 33.4 33.4 33.3 33.3 33.3 33.3 +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% -0.5% -0.5% -0.5% -0.5% -6- W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7. I2C CONTROL AND STATUS REGISTERS 7.1 BIT Register 0: Frequency Select Register (default = 0) NAME PWD DESCRIPTION 7 6 5 4 3 2 1 EN_SPSP SSEL [4] SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL 0 0 0 0 0 0 0 Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum enabled Frequency selection by software via I2C. 0 EN_SAFE_FREQ 0 Enable software program FS [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 6 ~ 2. Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0. 7.2 BIT Register 1: CPU Clock Register (1 = enable, 0 = Stopped) PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 44,45 37,38 40,41 - 1 1 1 X X X X X CPUCLK_T2 / C2 CPUCLK_T1 / C1 CPUCLK_T0 / C0 FS [4] Read back. FS [3] Read back FS [2] Read back FS [1] Read back FS [0] Read back 7.3 BIT Register 2: PCI Clock Register (1 = enable, 0 = Stopped) PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 48 17 16 15 14 12 11 10 X 1 1 1 1 1 1 1 MULTISEL0 trapping pin data read back PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 -7- Publication Release Date: March 2006 Revision 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.4 BIT Register 3: PCI, 48MHz Clock Register (1 = enable, 0 = Stopped) PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 22 23 48 1 Reserved 8 7 6 1 1 1 1 1 1 1 1 48MHZ 24_48MHz REF0 REF1 Reserved PCICLK_F2 PCICLK_F1 PCICLK_F0 7.5 BIT Register 4: 3V66 Control Register (1 = enable, 0 = Stopped) PIN NO PWD DESCRIPTION 7 6 5 4 3 2 1 0 27 28 30 31 1 1 1 1 1 1 1 1 Reserved Reserved Reserved Reserved 3V66_3 / 48MHz 3V66_2 3V66_1 3V66_0 7.6 BIT Register 5: Watchdog Control Register NAME PWD DESCRIPTION 7 6 MULTISEL1 EN_WD X 0 MULTISEL1 trapping pin data read back Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only. 5 WD_TIMEOUT 0 4 3 2 1 0 SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0] 0 0 0 0 0 Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits. -8- W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.7 BIT Register 6: Watchdog Timer Register NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 WD_TIME [7] WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0] 0 0 0 0 1 0 0 0 Watchdog timeout time. The bit resolution is 250mS. The default time is 8*250mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value. 7.8 BIT Register 7: M/N Program Register NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 N_DIV [8] TEST1 TEST0 M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0] 1 1 0 0 1 1 0 1 Programmable N divisor value. Bit 7 ~0 are defined in the Register 8. Test bit 1. Winbond test bit, do not change them. Test bit 0. Winbond test bit, do not change them. Programmable M divisor value. 7.9 BIT Register 8: M/N Program Register NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0] 0 1 1 0 0 1 1 1 Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 7. -9- Publication Release Date: March 2006 Revision 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.10 Register 9: Spread Spectrum Programming Register BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0] 0 0 0 1 1 1 1 1 Spread Spectrum Up Counter bit 3. Spread Spectrum Up Counter bit 2. Spread Spectrum Up Counter bit 1. Spread Spectrum Up Counter bit 0 Spread Spectrum Down Counter bit 3 Spread Spectrum Down Counter bit 2 Spread Spectrum Down Counter bit 1 Spread Spectrum Down Counter bit 0 7.11 Register 10: Divisor and Step-less Enable and Skew Control Register BIT NAME PWD DESCRIPTION 7 EN_MN_PROG 0 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 0 bit 0). CPU, 3V66, and PCI ratio selection. The ratio is shown as following table. CPU to 3V66 skew. 6 5 4 3 2 1 0 RATIO_SEL [3] RATIO_SEL [2] RATIO_SEL [1] RATIO_SEL [0] CPU_3V66_SKEW [2] CPU_3V66_SKEW [1] CPU_3V66_SKEW [0] 0 0 1 0 1 0 0 Table of CPU, 3V66, and PCI clock selection. I2C Reg10 Definition REG10 BIT6 SSEL3 0 0 0 0 0 0 REG10 BIT5 SSEL2 0 0 0 0 1 1 REG10 BIT4 SSEL1 0 0 1 1 0 0 REG10 BIT3 0 1 0 1 0 1 CPU 2 2 3 4 4 6 3V66 5 6 6 6 8 6 PCI 10 12 12 12 16 12 SSEL0 RATIO RATIO RATIO - 10 - W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.12 Register 11: Winbond Chip ID Register (Read Only) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0] 0 1 0 1 0 1 1 1 Winbond Chip ID. W83194BR-323 is 0x57. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. 7.13 Register 12: Winbond Chip ID Register (Read Only) BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 SUB_ID [3] SUB_ID [2] SUB_ID [1] SUB_ID [0] VER_ID [3] VER_ID [2] VER_ID [1] VER_ID [0] 0 0 1 0 0 0 1 0 The sub-chip ID of W83194BR-323 is defined as 0010b. Winbond Sub-Chip ID. Winbond Sub-Chip ID. Winbond Sub-Chip ID. Winbond Version ID. The Version ID of W83194BR-323 is 0010b. Winbond Version ID. Winbond Version ID. Winbond Version ID. 7.14 Register 13: Reserved BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 1 0 0 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - 11 - Publication Release Date: March 2006 Revision 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.15 Register 14: CPU to PCI Skew Control BIT NAME PWD DESCRIPTION 7 6 5 4 3 2 1 0 Reserved Reserved Reserved CPU_PCI_SKEW [2] CPU_PCI_SKEW [1] CPU_PCI_SKEW [0] Reserved Reserved 1 0 0 1 0 0 0 0 CPU to PCI Skew 7.16 Register 15: SEL24_48 and SEL48_66 Control BIT NAME PWD DESCRIPTION 7 SEL24_48 X In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. 0-> 24 MHz, 1->48MHz. In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. 0-> 48 MHz, 1->66MHz. Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them 6 SEL_48_66 X 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 1 - 12 - W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 8. ACCESS INTERFACE The W83194BR-323 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-323 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8.4 Byte Read protocol - 13 - Publication Release Date: March 2006 Revision 2.1 W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 9. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83194BR-323 W83194BG-323 48 PIN SSOP 48 PIN SSOP (Lead free package) Commercial, 0°C to +70°C Commercial, 0°C to +70°C 10. HOW TO READ THE TOP MARKING W83194BR-323 28051234 514GAB 1st line: Winbond logo and the type number: Normal part:W83194BR-323, Lead free part:W83194BG-323 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 514 G BB 514: packages made in '2005, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision W83194BG-323 28051234 514GAB All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. - 14 - W83194BR-323W83194BG-323 STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 11. PACKAGE DRAWING AND DIMENSIONS Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 15 - Publication Release Date: March 2006 Revision 2.1