W83627HG

W 83627HF/F W83627HG/G Winbond LPC I/O Date： 2006/06/09 Revision： 2.27 W83627HF/ F/ HG/ G W83627HF/F, W83627HG/G Data Sheet Revision History VERSION DATE PAGE DESCRIPTION 0.50 09/25/98 n.a. 88-93,102,105, 139,151,153 90-93;113-115 90,91,113-115, 119-123,133,136, 137,140,141 All All 90 1. P74 ~ P76 2. P3,P90,P111 3. P6~P7 Not released For internal use only First published. Explanation of H/W Monitor function andregister correction. Pinout and register correction. Typo and data correction. H/W Monitor register explanation. New composition. New composition. Correct SUSLED mode register 1. Add Section 4.1 Plug and Pla Configuration. 2. Remove Phoenix MultiKey related. 3. Add Block Digram Add the top marking of W83627HG and W83627G. Typo and data correction. Data correction. Data correction. Data correction. Add part No.to Section 13 Ordering Instruction and data correction. Add pin configuration of W83627G & W83627HG 0.51 0.52 0.53 1.0 2.0 2.1 2.2 11/10/98 01/11/99 07/26/99 11/14/00 11/01/02 03/07/03 04/09/03 2.21 2.22 2.23 2.24 2.25 2.26 2.27 02/03/04 05/28/04 07/07/04 10/28/04 11/02/04 01/11/05 06/09/06 121 12,13,21,23,39,4 5,46,82,93,94,98 ~ 100 20,24,84,100 48,79 98 24, 76,77,120 8 ~ 11 -i- Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Table of Content1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 3 BLOCK DIAGRAM FOR W83627F............................................................................................. 6 BLOCK DIAGRAM FOR W83627HF .......................................................................................... 7 PIN CONFIGURATION ............................................................................................................... 8 PIN DESCRIPTION................................................................................................................... 12 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 LPC Interface ............................................................................................................... 13 FDC Interface............................................................................................................... 14 Multi-Mode Parallel Port............................................................................................... 15 Serial Port Interface ..................................................................................................... 21 KBC Interface............................................................................................................... 22 ACPI Interface.............................................................................................................. 22 Hardware Monitor Interface ......................................................................................... 23 Game Port & MIDI Port ................................................................................................ 24 General Purpose I/O Port ............................................................................................ 25 6.9.1 6.9.2 6.9.3 General Purpose I/O Port 1 （Power source is Vcc） .................................................... 25 General Purpose I/O Port 2 （Power source is Vcc） .................................................... 25 General Purpose I/O Port 3 （Power souce is VSB） .................................................... 26 6.10 7. 7.1 7.2 POWER PINS .............................................................................................................. 26 General Description ..................................................................................................... 27 Access Interface........................................................................................................... 27 7.2.1 7.2.2 LPC interface.................................................................................................................. 27 I2C interface.................................................................................................................... 29 Monitor over 4.096V voltage： ....................................................................................... 32 Monitor negative voltage： ............................................................................................. 33 Temperature Measurement Machine.............................................................................. 34 Fan speed count............................................................................................................. 35 Fan speed control........................................................................................................... 37 Voltage SMI# mode： .................................................................................................... 38 Fan SMI# mode： .......................................................................................................... 38 Temperature 1 SMI# modes........................................................................................... 39 Temperature 2, 3 SMI# modes： ................................................................................... 40 HARDWARE MONITOR ........................................................................................................... 27 7.3 Analog Inputs ............................................................................................................... 32 7.3.1 7.3.2 7.3.3 7.4 FAN Speed Count and FAN Speed Control ................................................................ 35 7.4.1 7.4.2 7.5 SMI# interrupt mode..................................................................................................... 38 7.5.1 7.5.2 7.5.3 7.5.4 7.6 OVT# interrupt mode ................................................................................................... 41 - ii - W83627HF/ F/ HG/ G 7.7 8. 8.1 8.2 8.3 9. 9.1 REGISTERS AND RAM............................................................................................... 42 Start Frame .................................................................................................................. 76 IRQ/Data Frame........................................................................................................... 76 Stop Frame .................................................................................................................. 77 Plug and Play Configuration ........................................................................................ 78 9.1.1 9.1.2 Compatible PnP.............................................................................................................. 78 Configuration Sequence ................................................................................................. 79 SERIAL IRQ .............................................................................................................................. 76 CONFIGURATION REGISTER ................................................................................................ 78 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 10. 10.1 10.2 11. 11.1 11.2 11.3 12. 13. 14. 15. Chip（Global）Control Register .................................................................................. 81 Logical Device 0 （FDC） ........................................................................................... 87 Logical Device 1 （Parallel Port） ............................................................................... 91 Logical Device 2 （UART A） ..................................................................................... 93 Logical Device 3 （UART B） ..................................................................................... 94 Logical Device 5 （KBC） ........................................................................................... 96 Logical Device 6 （CIR） ............................................................................................ 97 Logical Device 7 （Game Port, MIDI Port and GPIO Port 1） .................................... 97 Logical Device 8 （GPIO Port 2 and Watch Dog Timer） ......................................... 98 Logical Device 9 （GPIO Port 3, VSB powered）..................................................... 100 Logical Device A （ACPI） ........................................................................................ 101 Logical Device B （Hardware Monitor） ................................................................... 108 Absolute Maximum Ratings ....................................................................................... 110 DC CHARACTERISTICS........................................................................................... 110 Parallel Port Extension FDD ...................................................................................... 118 Parallel Port Extension 2FDD .................................................................................... 118 Four FDD Mode ......................................................................................................... 119 SPECIFICATIONS .................................................................................................................. 110 APPLICATION CIRCUITS ...................................................................................................... 118 ORDERING INSTRUCTION ................................................................................................... 120 HOW TO READ THE TOP MARKING.................................................................................... 120 PACKAGE DIMENSIONS ....................................................................................................... 121 APPENDIX A ： DEMO CIRCUIT .......................................................................................... 122 - iii - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 1. GENERAL DESCRIPTION The W83627HF and W83627F are evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC（Low Pin Count）interface, which will be supported in the next generation Intel chip-set. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83627F/HF's integration of Game Port and MIDI Port.It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. The disk drive adapter functions of W83627F/HF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83627F/HF greatly reduces the number of components required for interfacing with floppy disk drives. The W83627F/HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83627F/HF provides two high-speed serial communication ports（UARTs）, one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83627F/HF provides IR functions： IrDA 1.0 （SIR for 1.152K bps）and TV remote IR （Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols）. The W83627F/HF supports one PC-compatible printer port （ SPP ） , Bi-directional Printer port （BPP） and also Enhanced Parallel Port （EPP） and Extended Capabilities Port（ECP）. Through the printer port interface pins, also available are： Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature TM demand of Windows 95/98 , which makes system resource allocation more efficient than ever. The W83627F/HF provides functions that complies with ACPI （Advanced Configuration and Power Interface ） , which includes support of legacy and ACPI power management through PME# or PSOUT# function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up. The W83627F/HF also has auto power management to reduce the power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY Phoenix MultiKey/42 TM TM -2, , or customer code. The W83627F/HF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode（VCC is off）. The W83627F/HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide. Moreover W83627F/HF is made to meet the specification of PC98/PC99's requirement in the power management： ACPI and DPM （Device Power Management）. Publication Release Date: June 09, 2006 Revision 2.27 -1- W83627HF/ F/ HG/ G The W83627F/HF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, They are very important for a entertainment or consumer computer. Only the W83627HF support hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. -2- W83627HF/ F/ HG/ G 2. FEATURES General • Meet LPC Spec. 1.0 • Support LDRQ#（LPC DMA）, SERIRQ （serial IRQ） • Include all the features of Winbond I/O W83977TF and W83977EF • Integrate Hardware Monitor functions • Compliant with Microsoft PC98/PC99 Hardware Design Guide • Support DPM （Device Power Management）, ACPI • Programmable configuration settings • Single 24 or 48 MHz clock input FDC • Compatible with IBM PC AT disk drive systems • Variable write pre-compensation with track selectable capability • Support vertical recording format • DMA enable logic • 16-byte data FIFOs • Support floppy disk drives and tape drives • Detects all overrun and underrun conditions • Built-in address mark detection circuit to simplify the read electronics • FDD anti-virus functions with software write protect and FDD write enable signal （write data signal was forced to be inactive） • Support up to four 3.5-inch or 5.25-inch floppy disk drives • Completely compatible with industry standard 82077 • 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate • Support 3-mode FDD, and its Win95/98 driver UART • Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI compatible • Fully programmable serial-interface characteristics： ─ 5, 6, 7 or 8-bit characters ─ Even, odd or no parity bit generation/detection ─ 1, 1.5 or 2 stop bits generation -3- Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G • Internal diagnostic capabilities： ─ Loop-back controls for communications link fault isolation ─ Break, parity, overrun, framing error simulation • Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to （216-1） • Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz Infrared • Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Parallel Port • Compatible with IBM parallel port • Support PS/2 compatible bi-directional parallel port • Support Enhanced Parallel Port（EPP）− Compatible with IEEE 1284 specification • Support Extended Capabilities Port（ECP）− Compatible with IEEE 1284 specification • Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port • Enhanced printer port back-drive current protection Keyboard Controller • 8042 based with optional F/W from AMIKKEY mable ROM, and 256 bytes of RAM • Software compatibility with the 8042 • Support PS/2 mouse • Support port 92 • Support both interrupt and polling modes • Fast Gate A20 and Hardware Keyboard Reset • 8 Bit Timer/ Counter • Support binary and BCD arithmetic • 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency TM -2,or customer code with 2K bytes of program- • Asynchronous Access to Two Data Registers and One status Register Game Port • Support two separate Joysticks • Support every Joystick two axis （X,Y） and two button （A,B） controllers -4- W83627HF/ F/ HG/ G MIDI Port • The baud rate is 31.25 Kbaud • 16-byte input FIFO • 16-byte output FIFO General Purpose I/O Ports • 22 programmable general purpose I/O ports • General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watch dog timer output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED output, RSMRST# signal, PWROK signal, Beep output • Functional in power down mode （GP1 only） OnNow Functions • Keyboard Wake-Up by programmable keys • Mouse Wake-Up by programmable buttons • CIR Wake-Up by programmable keys • On Now Wake-Up from all of the ACPI sleeping states （S1-S5） Hardware Monitor Functions （ Only for W83627HF） • 5 VID input pins for CPU Vcore identification • 3 thermal inputs from optionally remote thermistors or 2N3904 transistors or PentiumTM II （Deschutes） thermal diode output • 7 positive voltage inputs （typical for +12V, -12V, +5V, -5V, +3.3V, VcoreA, VcoreB） • 2 intrinsic voltage monitoring （typical for Vbat, +5VSB） • 3 fan speed monitoring inputs • 2 fan speed control • Build in Case open detection circuit • WATCHDOG comparison of all monitored values • Programmable hysteresis and setting points for all monitored items • Over temperature indicate output • Automatic Power On voltage detection Beep • Issue SMI#, IRQ, OVT# to activate system protection • Intel LDCMTM / Acer ADMTM compatible Package • 128-pin PQFP -5- Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 3. BLOCK DIAGRAM FOR W83627F LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ LPC Interface Joystick interface signals MSI MSO General-purpose I/O pins Keyboard/Mouse data and clock Game Port MIDI FDC Floppy drive interface signals Serial port A, B interface signals IRRX IRTX URA, B GPIO IR KBC CIR CIRRX# Printer port interface signals ACPI PRT -6- W83627HF/ F/ HG/ G 4. BLOCK DIAGRAM FOR W83627HF LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ LPC Interface Joystick interface signals MSI MSO General-purpose I/O pins Keyboard/Mouse data and clock Hardware monitor channel and Vref Game Port MIDI FDC Floppy drive interface signals Serial port A, B interface signals IRRX IRTX URA, B GPIO IR KBC CIR CIRRX# Printer port interface signals HM PRT ACPI -7- Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 5. PIN CONFIGURATION Pin configuration of W83627F and W83627G SP R LW S P R P MC _ C WR I STRS R X L OT R ##K# X P ///// S G G G G GP O M M P P P P PS UD C 3 33 3 3I TAL 0 12 3 4N# TK A A GG V GP P N N N N N C NN NN 2 2 C C C C C C CC CD 1 2 P WI I L DRR S E T RT U D OX X S //// D S D R DC C G G G G R C OS T T S T LV P P P P V I D UI R S R S V K B 2 2 2 2 S BB T N B B B BC N I A 3 4 5 6 S # # BB # # # # C C N T 11 199 9 9 999 99 9 88 888888 8877 77 7777 7 76666 6 00 098 7 6 543 21 0 98 765432 1098 76 5432 1 09876 5 21 0 NC NC NC NC NC NC NC NC NC NC NC VCC NC NC VSS NC MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 SUSLED/GP35 KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 W83627F 1 1 1 1 1 1 1 1 1 1 22 2 2 2 2 2 2 2 2 3 33 3 3 33 33 1 2 3 4 5 67 8 9 0 1 2 3 4 5 6 7 8 9 01 2 3 4 5 6 7 8 9 0 12 3 4 56 78 D R V D E N 0 D I M D D M D S WW V R N OS S OI T DE C V D A BA BR E# # C DE### ## P EX # N# 1 / S M I # / G P 2 7 T WR H RP D E A# A A K TD 0 A# ## D CP V P L S L L L L S L MS C D E AA A A K K E S I R R DD D D C I # C QI 3 2 1 0 HN L #R KQ G # V L L S P B A P PP P C F R L E U C D DD D C RE C S K 7 6 5 4 3 AS T Y # V ME ET ## -8- W83627HF/ F/ HG/ G A A GG V GP P N N N N N C NN N N 2 2 C C C C C C CC C D 1 2 P WI I L DRR S E T RT U D OX X S //// D S D R DC C G G G G R C OS T T S T LV P P P P V I D UI R S RS V K B 2 2 2 2 S BB T N B B B B C N I A 3 4 5 6 S # # BB # # # # C C N T SP R LW S P R P MC _ C WR I STRSR X L OT R ##K# X P ///// S G G G G GP O M M P P P P PS UD C 3 33 3 3I TAL 0 12 3 4N#T K 11 199 9 9 999 99 9 88 8 88888 8877 7 7 7777 7 76666 6 00 098 7 6 543 21 0 98 7 65432 1098 7 6 5432 1 09876 5 21 0 NC NC NC NC NC NC NC NC NC NC NC VCC NC NC VSS NC MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 SUSLED/GP35 KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 W83627G 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 33 3 3 33 3 3 1 234 5 67 8 90 1 2 3 4 5 6 7890 1 23 4 5 6 7 8 9 0 12 3 4 56 78 D R V D E N 0 D I M D D MD S WW V R N O S S OI T DE C V D A BA BR E# # C DE### ## P EX # N# 1 / S M I # / G P 2 7 T WR H RP D E A# A A K TD 0 A# ## D CP V P L S L L L L S L M SC D E AA A A K K E S I R R DD D D C I # C QI 3 2 1 0 L #R HN KQ G # V L L S P B A P PP P C F R L E U C D DD D C RE C S K 7 6 5 4 3 AS T Y # V ME ET ## -9- Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G PIN CONFIGURATION of W83627HF and W83627HG V T I N 3 V R E F P WI I C A S S L DRR S C D E T RT + E L A D OX X VV3 + D S D RDC O / ///// CC. 1 1 O O 3 A 2 2 5 A G G G G G G R C OS T T S T P R R V V V V V G P P P P P P V I D UI R S R S V E E E I C I I I N 2 2 2 2 2 2 S BB TN B BBBC N A B NC N N N D 1 2 3 4 5 6 S # # BB # # # # C # S U S C LV KB IA NT SP R LW S P RP MC _ C WR I STRS R X L OT R ##K# X P ///// S G G G G GP O M M P P P P PS UD C 3 33 3 3I TAL 0 12 3 4N# T K 11 199 9 9 999 99 9 88 888888 8 877 77 7777 7 766666 00 098 7 6 543 21 0 98 765432 1 098 76 5432 1 098765 21 0 VTIN2 VTIN1 OVT# VID4 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 VCC FANPWM2 FANPWM1 VSS BEEP MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 SUSLED/GP35 KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 W83627HF 1 1 1 1 1 1 1 1 112 2 2 2 2 2 2 2 2 2 3 33 3 3 33 33 1 2 3 4 5 67 8 90 1 2 3 4 5 6 7 890 1 2 3 4 5 6 7 8 9 0 12 3 4 56 78 D D I M D D M D S WW V R R N OS S OI T DE C V V D A BA BR E# # C DDE### ## P # EEX NN# 01 / S M I # / G P 2 7 T WR H RP D E A# A A K TD 0 A# ## D CP V P L S L L L L S L MS C D E AA A A K K E S I R R DD D D C I # C QI 3 2 1 0 L #R HN KQ G # V L L S P B A P PP P C F R L E U C D DD D C RE C S K 7 6 5 4 3 AST Y# V ME ET ## - 10 - W83627HF/ F/ HG/ G V T I N 3 V R E F C P WI I A S S L DRR S C D E T RT + E L A D OX X VV3 + / ///// D S D RDC O CC. 1 1 O O 3 A 2 2 5 A G G G G G G R C OS T T S T P R R V V V V V G P P P P P P V I D UI R S R S V E E E I C I I I N 2 2 2 2 2 2 S BB TN B BBBC N A B NC N N N D 1 2 3 4 5 6 S # # BB # # # # C # S U S C LV KB IA NT SP R LW S P R P MC _ C WR I STRSR X L OT R ##K# X P ///// S G G G G GP O M M P P P P PS UD C 3 33 3 3I TAL 0 12 3 4N#T K 11 199 9 9 999 99 9 88 888888 8 877 77 7777 7 76 6 66 6 00 098 7 6 543 21 0 98 765432 1 098 76 5432 1 09 8 76 5 21 0 VTIN2 VTIN1 OVT# VID4 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 VCC FANPWM2 FANPWM1 VSS BEEP MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 SUSLED/GP35 KDAT KCLK VSB KBRST A20GATE KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 W83627HG 1 1 1 1 1 1 1 1 1122 22 2 2 22 2 2 3 33 3 3 33 33 1 2 34 5 67 8 90 1 2 3 4 5 6 7 8901 23 4 5 67 8 9 0 12 3 4 56 78 D D I M D D M D S WW V R R N OS S OI T DE C V V DABA BRE# # C DDE### ## P # EEX NN# 01 / S M I # / G P 2 7 T WR H RP D E A# A A K TD 0 A# ## D CP V P L S L L L L S L M S C D E AA A A K K E S I R R DD D D C I # C QI 3 2 1 0 HN L #R G KQ # V L L S P B A P PP P C F R L E U C D DD D C RE C S K 7 6 5 4 3 AS T Y # V ME ET ## - 11 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 6. PIN DESCRIPTION TYPE DESCRIPTION I/O8t I/O12t I/O24t I/O12tp3 I/O12ts I/O24ts I/O24tsp3 I/OD12t I/OD24t I/OD12ts I/OD16ts I/OD24ts I/OD12cs I/OD16cs I/OD12csd I/OD12csu O4 O8 O12 O16 O24 O12p3 O24p3 OD12 OD24 OD12p3 TTL level bi-directional pin with 8mA source-sink capability TTL level bi-directional pin with 12mA source-sink capability TTL level bi-directional pin with 24 mA source-sink capability 3.3V TTL level bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability TTL level bi-directional pin and open-drain output with 12mA sink capability TTL level bi-directional pin and open-drain output with 24mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 24mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and opendrain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and opendrain output with 12mA sink capability Output pin with 4 mA source-sink capability Output pin with 8 mA source-sink capability Output pin with 12 mA source-sink capability Output pin with 16 mA source-sink capability Output pin with 24 mA source-sink capability 3.3V output pin with 12 mA source-sink capability 3.3V output pin with 24 mA source-sink capability Open-drain output pin with 12 mA sink capability Open-drain output pin with 24 mA sink capability 3.3V open-drain output pin with 12 mA sink capability - 12 - W83627HF/ F/ HG/ G PIN DESCRIPTION, continued. TYPE DESCRIPTION INt INtp3 INtd INtu INts INtsp3 INc INcd INcs INcsu TTL level input pin 3.3V TTL level input pin TTL level input pin with internal pull down resistor TTL level input pin with internal pull up resistor TTL level Schmitt-trigger input pin 3.3V TTL level Schmitt-trigger input pin CMOS level input pin CMOS level input pin with internal pull down resistor CMOS level Schmitt-trigger input pin CMOS level Schmitt-trigger input pin with internal pull up resistor Note： Please refer to Section 11.2 DC CHARACTERISTICS for details. 6.1 LPC Interface PIN I/O FUNCTION SYMBOL CLKIN PME# PCICLK LDRQ# SERIRQ LAD[3：0] LFRAME# LRESET# SUSCLKIN 18 19 21 22 23 24-27 29 30 75 INt3 OD12p3 INtsp3 O12p3 I/O12tp3 I/O12tp3 INtsp3 INtsp3 INtsp3 System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input. Generated PME event. PCI clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. 32khz clock input, for CIR only. - 13 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 6.2 FDC Interface PIN I/O FUNCTION SYMBOL DRVDEN0 DRVDEN1 SMI# IRQIN1 GP27 INDEX# 1 2 OD24 OD12 OD12 INt I/OD12t Drive Density Select bit 0. Drive Density Select bit 1.（Default） System Management Interrupt Interrupt channel input. General purpose I/O port 2 bit 7. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 500 ohm resistor. The resistor can be disabled by bit 7 of LD0-CRF0（FIPURDWN）. Motor A On. When set to 0, this pin enables disk drive 0. Drive Select B. When set to 0, this pin enables disk drive B. 0V to +5V amplitude fan tachometer input Drive Select A. When set to 0, this pin enables disk drive A. Motor B On. When set to 0, this pin enables disk drive 1. Fan speed control. Use the Pulse Width Modulation（PWM） technical knowledge to control the Fan's RPM. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion 3 INcsu MOA# DSB# FANIN3 DSA# MOB# FANPWM3 DIR# 4 5 6 7 OD24 OD24 I/O24ts OD24 OD24 OD24 8 OD24 STEP# WD# WE# TRACK0# 9 10 11 13 OD24 OD24 OD24 INcsu Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K ohm resistor.The resistor can be disabled by bit 7 of L0-CRF0（FIPURDWN）. Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K ohm resistor. The resistor can be disabled by bit 7 of L0-CRF0 （FIPURDWN）. WP# 14 INcsu - 14 - W83627HF/ F/ HG/ G FDC Interface, continued. SYMBOL PIN I/O FUNCTION RDATA# 15 INcsu The read data input signal from the FDD. This input pin is pulled up internally by a 1 K ohm resistor. The resistor can be disabled by bit 7 of L0-CRF0 （FIPURDWN）. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 HEAD# 16 OD24 DSKCHG# 17 INcsu Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K ohm resistor. The resistor can be disabled by bit 7 of L0-CRF0 （FIPURDWN）. 6.3 Multi-Mode Parallel Port The following pins have alternate functions (Printer Mode and Extension FDD Mode), which are selected by CR28 and LD1-CRF0 setting. SYMBOL PIN I/O FUNCTION SLCT 31 INts PRINTER MODE： An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. WE2# OD12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PE 32 INts PRINTER MODE： An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. WD2# OD12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC. Publication Release Date: June 09, 2006 Revision 2.27 - 15 - W83627HF/ F/ HG/ G Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION BUSY 33 INts PRINTER MODE： An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. MOB2# OD12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. ACK# 34 INts PRINTER MODE： An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DSB2# OD12 EXTENSION FDD MODE： This pin is for the Extension FDD B; its functions are the same as the DSB# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the DSB# pin of FDC. PD7 35 I/O12ts PRINTER MODE： PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DSA2# OD12 EXTENSION FDD MODE： This pin is a tri-state output. EXTENSION 2FDD MODE： This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC. - 16 - W83627HF/ F/ HG/ G Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION PD6 36 I/O12ts PRINTER MODE： PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. MOA2# OD12 EXTENSION FDD MODE： This pin is a tri-state output. EXTENSION. 2FDD MODE： MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. PD5 37 I/O12ts PRINTER MODE： PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE： This pin is a tri-state output. EXTENSION 2FDD MODE： This pin is a tri-state output. PD4 38 I/O12ts PRINTER MODE： PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DSKCHG2# INts EXTENSION FDD MODE： This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. PD3 39 I/O12ts PRINTER MODE： PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. RDATA2# INts EXTENSION FDD MODE： RDATA2# This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE： RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. - 17 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION PD2 40 I/O12ts PRINTER MODE： PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. WP2# INts EXTENSION FDD MODE： WP2# This pin is for Extension FDD B; its function is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE： WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. It is pulled high internally. PD1 41 I/O12ts PRINTER MODE： PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. TRAK02# INts EXTENSION FDD MODE： TRAK02# This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE： TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. PD0 42 I/O12ts PRINTER MODE： PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. INDEX2# INts EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. - 18 - W83627HF/ F/ HG/ G Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION SLIN# 43 OD12 PRINTER MODE： SLIN# Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. STEP2# OD12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. INIT# 44 OD12 PRINTER MODE： Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DIR2# OD12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. ERR# 45 INts PRINTER MODE： An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. HEAD2# OD12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the HEAD# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC. - 19 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Multi-Mode Parallel Port, continued. SYMBOL PIN I/O FUNCTION AFD# 46 OD12 PRINTER MODE： An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DRVDEN0 OD12 EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. STB# 47 OD12 PRINTER MODE： An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE： This pin is a tri-state output EXTENSION 2FDD MODE： This pin is a tri-state output. - 20 - W83627HF/ F/ HG/ G 6.4 Serial Port Interface PIN I/O FUNCTION SYMBOL CTSA# CTSB# DSRA# DSRB# RTSA# HEFRAS 49 78 50 79 51 INt Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. INt Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 （HEFRAS）. A 4.7 k ohm is recommended if intends to pull up. （select 4EH as configuration I/O port′s address） UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as PNPCVS# , which provides the power-on value for CR24 bit 0, A 4.7k ohm is recommended if intends to pull up.（This bit is used to clear the default value of FDC, UARTs, and LPT setting） UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 （PENKBC）. A 4.7 k ohm resistor is recommended if intends to pull up. （ enable KBC） UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the poweron value for CR24 bit 6 （EN48）. A 4.7 k ohm resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. O8C INcd DTRA# PNPCVS# 52 O8C INcd RTSB# DTRB# SINA SINB# SOUTA PENKBC 80 81 53 82 54 O8C O8C INt O8C INcd SOUTB PEN48 DCDA# DCDB# RIA# RIB# 83 O8C INcd 56 84 57 85 INt INt - 21 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 6.5 KBC Interface PIN I/O FUNCTION SYMBOL KBLOCK# GA20M KBRST KCLK 58 59 60 62 INtu O16 O16 I/OD16ts I/OD16cs I/OD16ts I/OD16cs I/OD16ts I/OD16cs I/OD16ts I/OD16cs Keyboard inhibits control input. This pin is after system reset. Internal pull high. （KBC P17） Gate A20 output. This pin is high after system reset. （KBC P21） Keyboard reset. This pin is high after system reset. （KBC P20） Keyboard Clock. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level. Keyboard Data. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level. PS2 Mouse Clock. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level. PS2 Mouse Data. For G and J version, this pin is CMOS level. For UD-Mask A-version, this pin is TTL level. KDAT 63 MCLK 65 MDAT 66 6.6 ACPI Interface PIN I/O FUNCTION SYMBOL PSOUT# PSIN VBAT 67 68 74 OD12 IN c d PWR Panel Switch Output. This signal is used for Wake-Up system from S5c o l d state. This pin is pulse output, active low. Panel Switch Input. This pin is high active with an internal pull down resistor. Battery voltage input. - 22 - W83627HF/ F/ HG/ G 6.7 Hardware Monitor Interface SYMBOL CASEOPEN# （For W83627HF only, all these pins in W83627F are NC.） PIN I/O FUNCTION 76 94 95 96 98 99 100 101 102 103 104 105 106110 111113 116 115 118 INt AIN AIN AIN AIN AIN AIN PWR AIN AIN AIN OD24 INt CASE OPEN. An active low input from an external device when case is opened. This signal can be latched if pin VBAT is connect to battery, even W83627HF is power off. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. Reference Voltage for temperature measuration. Temperature sensor 3 input. It is used for temperature measuration. Temperature sensor 2 input. It is used for CPU1 temperature measuration. Temperature sensor 1 input. It is used for system temperature measuration. Over temperature Shutdown Output. It indicated the VTIN2 or VTIN3 is over temperature limit. Voltage Supply readouts from Pentium II. 0V to +5V amplitude fan tachometer input. -5VIN -12VIN +12VIN +3.3VIN VCOREB VCOREA VREF VTIN3 VTIN2 VTIN1 OVT# VID[4：0] FANIO[3：1] I/O12ts Alternate Function： Fan on-off control output. These multifunctional pins can be programmable input or output. Fan speed control. Use the Pulse Width Modulatuion （PWM） technic knowledge to control the Fan's RPM. Beep function for hardware monitor. This pin is low after system reset. FANPWM1 FANPWM2 BEEP O12 OD12 - 23 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 6.8 Game Port & MIDI Port PIN I/O FUNCTION SYMBOL MSI GP20 MSO IRQIN0 GPSA2 GP17 GPSB2 GP16 GPY1 GP15 GPY2 GP14 P16 GPX2 GP13 P15 GPX1 GP12 P14 GPSB1 GP11 P13 GPSA1 GP10 P12 119 120 121 INtu I/OD12t O8C Inc INcsu I/OD12csu MIDI serial data input .（Default） General purpose I/O port 2 bit 0. MIDI serial data output. （Default） Alternate Function input： Interrupt channel input. Active-low, Joystick I switch input 2. This pin has an internal pull-up resistor. （Default） General purpose I/O port 1 bit 7. Active-low, Joystick II switch input 2. This pin has an internal pull-up resistor. （Default） General purpose I/O port 1 bit 6. Joystick I timer pin. This pin connects to Y positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 5. Joystick II timer pin. This pin connects to Y positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 4. Alternate Function Output： KBC P16 I/O port. Joystick II timer pin. This pin connects to X positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 3. Alternate Function Output： KBC P15 I/O port. Joystick I timer pin. This pin connects to X positioning variable resistors for the Joystick. （Default） General purpose I/O port 1 bit 2. Alternate Function Output： KBC P14 I/O port. Active-low, Joystick II switch input 1. （Default） General purpose I/O port 1 bit 1. Alternate Function Output： KBC P13 I/O port. Active-low, Joystick I switch input 1. （Default） General purpose I/O port 1 bit 0. Alternate Function Output： KBC P12 I/O port. 122 INcsu I/OD12csu 123 I/OD12csd I/OD12cs 124 I/OD12csd I/OD12cs 125 I/OD12csd I/OD12cs 126 I/OD12csd I/OD12cs 127 INcsu I/OD12csu INcsu I/OD12csu 128 - 24 - W83627HF/ F/ HG/ G 6.9 6.9.1 General Purpose I/O Port General Purpose I/O Port 1 （Power source is Vcc） See section 7.8 6.9.2 General Purpose I/O Port 2 （Power source is Vcc） PIN I/O FUNCTION SYMBOL GP20 MSI GP21 SCL GP22 SDA GP23 PLED GP24 WDTO GP25 IRRX GP26 IRTX GP27 SMI# ( IRQIN1) DRVDEN1 119 I/OD12t INt General purpose I/O port 2 bit 0. MIDI serial data input. Schmitt trigger input with internal pull-up resistor. General purpose I/O port 2 bit 1. Serail Bus Clock.（availiable for W83627HF only） General purpose I/O port 2 bit 2. Serial Bus Data.（availiable for W83627HF only） General purpose I/O port 2 bit 3. Power LED output, this signal will be logical low after system reset. General purpose I/O port 2 bit 4. Watch Dog Timer Output. High level indicates that Watch Dog Timer time-out occurs. General purpose I/O port 2 bit 5. Infrared Receiver Input. General purpose I/O port 2 bit 6. Infrared Transmitter Output. General purpose I/O port 2 bit 7. System Management Interrupt. (Interrupt channel input. For C version only) Drive Density Select bit 1.（Default） 92 I/OD12t INts I/OD12t I/OD12ts I/OD12t OD12 91 90 89 I/OD12t O12 88 I/OD12t INts I/OD12t O12 I/OD24t OD24 INt OD24 87 2 - 25 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 6.9.3 General Purpose I/O Port 3 （Power souce is VSB） PIN I/O FUNCTION SYMBOL GP30 SLP_SX# GP31 PWRCTL# GP32 PWROK GP33 RSMRST# GP34 CIRRX# GP35 SUSLED 73 72 I/OD12t INts I/OD12t O12 General purpose I/O port 3 bit 0. Chipset suspend C status input. General purpose I/O port 3 bit 1. Power On Control. Active low signal that informs system to turn main power. General purpose I/O port 3 bit 2. Power OK. Active (High) level indicates VDD is ready. General purpose I/O port 3 bit 3. Resume Reset. Active (High) level indicates VSB is ready. General purpose I/O port 3 bit 4. Consumer IR receiving input. This pin can Wake-Up system from S5cold.（Default） General purpose I/O port 3 bit 5. Suspend LED output, it can program to flash when suspend state.This function can work without VCC. （Default） 71 I/OD12t OD12 70 I/OD12t OD12 69 I/OD12t INts 64 I/OD24t O24 6.10 POWER PINS PIN FUNCTION SYMBOL VCC VSB VCC3V AVCC AGND VSS 12, 48, 77, 114 61 28 97 93 20, 55, 86, 117 +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. Do not leave this pin unconnected. Connect it to VCC if the system does not provide standby power +3.3V power supply for driving 3V on host interface. Analog VCC input. Internally supplier to all analog circuitry. Internally connected to all analog circuitry. The ground reference for all analog inputs.. Ground. - 26 - W83627HF/ F/ HG/ G 7. HARDWARE MONITOR 7.1 General Description The W83627HF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83627HF provides both LPC and I2CTM serial bus interface to access hardware. An 8-bit analog-to-digital converter（ADC）was built inside W83627HF. The W83627HF can simultaneously monitor 9 analog voltage inputs, 3 fan tachometer inputs, 3 remote temperature, one caseopen detection signal. The remote temperature sensing can be performed by thermistors, or 2N3904 NPN-type transistors, or directly from IntelTM Deschutes CPU thermal diode output. Also the W83627HF provides： 2 PWM（pulse width modulation）outputs for the fan speed control; beep tone output for warning; SMI#（through serial IRQ）, OVT#, GPO# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or IntelTM LDCM （LanDesk Client Management）, or other management application software. Also the users can set up the upper and lower limits （alarm thresholds） of these monitored parameters and to activate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters are out of the preset range. Additionally, 5 VID inputs are provided to read the VID of CPU （i.e. PentiumTM II） if applicable. This is to provide the Vcore voltage correction automatically. Also W83627HF uniquely provides an optional feature： early stage （before BIOS was loaded） beep warning. This is to detect if the fatal elements present --- Vcore or +3.3V voltage fail, and the system can not be boomed up. 7.2 Access Interface The W83627HF provides two interface for microprocessor to read/write hardware monitor internal registers. 7.2.1 LPC interface The first interface uses LPC Bus to access which the ports of low byte （bit2~bit0） are defined in the port 5h and 6h. The other higher bits of these ports is set by W83627HF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following： Port 295h： Index port. Port 296h： Data port. The register structure is showed as the Figure 8.1 - 27 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Configuration Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h VID/Fan Divisor Register 47h Serial Bus Address 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID/Device ID 49h Temperature 2, 3 Serial Bus Address 4Ah Control Register 4Bh~4Dh Select Bank for 50h~5Fh Reg. 4Eh Winbond Vendor ID 4Fh BANK 0 R-T Table Value BEEP Control Register Winbond Test Register 50h~58h BANK 1 Temperature 2 Control/Staus Registers 50h~56h BANK 2 Temperature 3 Control/Staus Registers 50h~56h BANK 4 Additional Control/Staus Registers 50h~5Ch BANK 5 Additional Limit Value & Value RAM 50h~57h ISA Data Bus ISA Address Bus Port 5h Index Register Port 6h Data Register Figure 8.1 ： ISA interface access diagram - 28 - W83627HF/ F/ HG/ G 7.2.2 I2C interface The second interface uses I2C Serial Bus. W83627HF hardware monitor has three serial bus address. That is, the first address defined at CR[48h] can read/write all registers excluding Bank 1 and Bank 2 temperature sensor 2/3 registers. The second address defined at CR[4Ah] bit2-0 only read/write temperature sensor 2 registers, and the third address defined at CR[4Ah] bit6-4 only can access （read/write）temperature sensor 3 registers. 7.2.2.1 The first serial bus access timing is shown as follow ： 0 7 8 0 7 8 (a) Serial bus write to internal address register followed by the data byte SCL SDA Start By Master 0 1 0 1 1 0 1 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte 7 8 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Stop by Master Frame 3 Data Byte (b) Serial bus write to internal address register only 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 0 1 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Stop by Master Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte (c) Serial bus read from a register with the internal address register prefer to desired location 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 0 1 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 Ack by Stop by Master Master Frame 1 Serial Bus Address Byte 0 Frame 2 Data Byte - 29 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 7.2.2.2 The serial bus timing of the temperature 2 and 3 are shown as follow ： (a) Typical 2-byte read from preset pointer location （Temp, TOS, THYST） 0 SCL SDA Start By Master 7 8 0 ... ... D1 7 8 0 ... ... D1 7 0 1 0 1 1 0 1 R/W Ack by 782D D7 D0 Ack by Master D7 D0 Ack by Master Stop by Master Frame 1 Serial Bus Address Byte Frame 2 MSB Data Byte Frame 3 LSB Data Byte (b) Typical pointer set followed by immediate read for 2-byte register（Temp, TOS, THYST） 0 SCL SDA Start By Master 7 8 0 4 1 0 0 1 A2 A1 A0 R/W Ack by 782D 0 0 0 0 0 0 D1 D0 Ack by 782D Frame 1 Serial Bus Address Byte Frame 2 Pointer Byte 0 SCL SDA Start By Master 7 8 0 1 0 0 1 A2 A1 A0 R/W Ack by 782D D7 ... ... 7 8 0 D1 D0 Ack by Master D7 ... ... 7 D1 D0 No Ack by Master Stop by Master Frame 3 Serial Bus Address Byte 0 Frame 4 MSB Data Byte Frame 5 LSB Data Byte (c) Typical read 1-byte from configuration register with preset pointer 0 SCL SDA Start By Master 7 8 0 7 8 1 0 0 1 A2 A1 A0 R/W Ack by 782D D7 D6 D5 D4 D3 D2 D1 D0 No Ack by Master Stop by Master Frame 1 Serial Bus Address Byte Frame 2 Data Byte - 30 - W83627HF/ F/ HG/ G (d) Typical pointer set followed by immediate read from configuration register 0 SCL SDA 0 Start By Master 7 8 0 1 0 1 1 0 1 R/W Ack by 782D D7 ... ... 7 8 0 D1 D0 Ack by Master D7 ... ... 7 D1 D0 Ack Stop b Maste Frame 1 Serial Bus Address By Frame 2 MSB Data Byte Frame 3 by Master LSB Data Byte (e) Temperature 2/3 configuration register Write 0 SCL SDA Start By Master 7 8 0 4 1 0 0 1 A2 A1 A0 R/W Ack by 782D 0 0 0 0 0 0 D1 D0 Ack by 782D Frame 1 Serial Bus Address Byte Frame 2 Pointer Byte 0 SCL SDA Start By Master 7 8 0 1 0 0 1 A2 A1 A0 R/W Ack by 782D D7 ... ... 7 8 0 D1 D0 Ack by Master D7 ... ... 7 D1 D0 No Ack by Master Stop by Master Frame 3 Serial Bus Address Byte 0 Frame 4 MSB Data Byte Frame 5 LSB Data Byte (f) SCL SDA Temperature 2/3 TOS and THYST write 0 7 8 0 7 8 1 Start By Master 0 0 1 A2 A1 A0 R/W Ack by 782D D7 D6 D5 D4 D3 D2 D1 D0 No Ack by Master Stop by Master Frame 1 Serial Bus Address Byte Frame 2 Data Byte - 31 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 7.3 Analog Inputs The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage, +3.3V, battery and 5VSB voltage can directly connected to these analog inputs. The +12V,-12V and -5V voltage inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 8.2 shows. VCOREA VCOREB +3.3VIN AVCC(+5V) VBAT 5VSB R1 V1 Positive Input R2 +12VIN Pin 100 Pin 99 Pin Pin Pin Pin 98 97 74 61 Positive Inputs Pin 96 8-bit ADC with 16mV LSB Negative Input V2 V3 R5 R3 N12VIN N5VIN Pin 95 Pin 94 R6 R 10K, 1% R4 VREF VTIN3 Pin 102 Pin 103 Pin 104 Pin 101 Typical Thermister Connection RTHM 10K, 25 C VTIN2 VTIN1 **The Connections of VTIN1 and VTIN2 are same as VTIN3 Figure. 8.2 7.3.1 Monitor over 4.096V voltage： The input voltage +12VIN can be expressed as following equation. 12VIN = V1 × R2 R1 + R2 The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximun input range of the 8-bit ADC. The Pin 97 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83627HF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The values of two serial resistors are 34K ohms and 50K ohms so that input voltage to ADC is 2.98V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as follows. - 32 - W83627HF/ F/ HG/ G Vin = VCC × 50 KΩ ≅ 2.98V 50 KΩ + 34 KΩ where VCC is set to 5V. The Pin 61 is connected to 5VSB voltage. W83627HF monitors this voltage and the internal two serial resistors are 17K Ω and 33K Ω so that input voltage to ADC is 3.3V which less than 4.096V of ADC maximum input voltage. 7.3.2 Monitor negative voltage： The negative voltage should be connected two series resistors and a positive voltage VREF （is equal to 3.6V）. In the Figure 8.2, the voltage V2 and V3 are two negative voltage which they are 12V and -5V respectively. The voltage V2 is connected to two serial resistors then is connected to another terminal VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a posedge voltage if the scales of the two serial resirtors are carefully selected. It is recommanded from Winbond that the scale of two serial resistors are R3=232K ohm and R4=56K ohm. The input voltage of node N12VIN can be calculated by following equation. N 12VIN = (VREF + V2 ) × ( 232 KΩ ) + V2 232 KΩ + 56 KΩ Where VREF is equal 3.6V. If the V2 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative votage and the express equation is shown as follows. V2 = N 12VIN − VREF × β 1− β Where β is 232K/（232K+56K）. If the N2VIN is 0.567 then the V2 is approximately equal to -12V. The another negative voltage input V3 （approximate -5V） also can be evaluated by the similar method and the serial resistors can be selected with R5=120K ohms and R6=56K ohms by the Winbond recommended. The expression equation of V3 With -5V voltage is shown as follows. V3 = N 5VIN − VREF × γ 1− γ Where the γ is set to 120K/ （ 120K+56K ） . If the monitored ADC value in the N5VIN channel is 0.8635, VREF is 3.6V and the parameter γ is 0.6818 then the negative voltage of V3 can be evalated to be -5V. - 33 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 7.3.3 Temperature Measurement Machine The temperature data format is 8-bit two's-complement for sensor 2 and 9-bit two's-complement for sensor 1. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1 CR[50h] and the LSB from the Bank1 CR[51h] bit 7. The format of the temperature data is show in Table 1. Table 1. TEMPERATURE 8-BIT DIGITAL OUTPUT 8-BIT BINARY 8-BIT HEX 9-BIT DIGITAL OUTPUT 9-BIT BINARY 9-BIT HEX +125°C +25°C +1°C +0.5°C +0°C -0.5°C -1°C -25°C -55°C 0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001 7Dh 19h 01h 00h FFh E7h C9h 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h 7.3.3.1 Monitor temperature from thermistor： The W83627HF can connect three thermistors to measure three different envirment temperature. The specification of thermistor should be considered to （1） β value is 3435K, （2） resistor value is 10K ohms at 25°C. In the Figure 8.2, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF （Pin 101）. 7.3.3.2 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 The W83627HF can alternate the thermistor to Pentium IITM （Deschutes） thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 8.3. The pin of Pentium IITM D- is connected to power supply ground （GND） and the pin D+ is connected to pin VTINx in the W83627HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base （B） and Collector （C） in the 2N3904 should be tied togeter to act as a thermal diode. - 34 - W83627HF/ F/ HG/ G VREF R=30K, 1% Bipolar Transistor Temperature Sensor VTINx C=3300pF C B E R=30K, 1% 2N3904 W83627HF OR Pentium II CPU Therminal Diode D+ C=3300pF D- VTINx Figure. 8.3 7.4 7.4.1 FAN Speed Count and FAN Speed Control Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 8.4. Determine the fan counter according to： Count = 1.35 × 10 6 RPM × Divisor In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation. RPM = 1.35 × 10 6 Count × Divisor The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, PRM, and count. Publication Release Date: June 09, 2006 Revision 2.27 - 35 - W83627HF/ F/ HG/ G Table 2. DIVISOR NOMINAL PRM TIME PER REVOLUTION COUNTS 70% RPM TIME FOR 70% 1 2 （default） 4 8 16 32 64 128 +12V 8800 4400 2200 1100 550 275 137 68 +5V Pull-up resister 4.7K Ohms 6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms 153 153 153 153 153 153 153 153 +12V 6160 3080 1540 770 385 192 96 48 9.74 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms diode +12V FAN Out GND diode +12V Pull-up resister 4.7K Ohms Fan Input Pin 111-113 14K~39K FAN Out GND Fan Input Pin 111-113 FAN Connector W83627HF FAN Connector 10K W83627HF Fan with Tach Pull-Up to +5V Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator +12V +12V diode +12V FAN Out GND Pull-up resister > 1K +12V Fan Input 3.9V Zener Pin 111-113 FAN Out diode Pull-up resister < 1K or totem-pole output Fan Input > 1K Pin 111-113 GND FAN Connector W83627HF 3.9V Zener FAN Connector W83627HF Fan with Tach Pull-Up to +12V and Zener Clamp Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Zener Clamp Figure. 8.4 - 36 - W83627HF/ F/ HG/ G 7.4.2 Fan speed control The W83627HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty − cycle(%) = Programmed 8 - bit Register Value × 100% 255 The PWM clock frequency also can be program and defined in the Bank0.CR5C. The application circuit is shown as follows. +12V R1 R2 D NMOS S + C FAN PNP Transistor G PWM Clock Input Figure. 8.5 - 37 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 7.5 7.5.1 SMI# interrupt mode Voltage SMI# mode： SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. （See Figure 8.6） Figure. 8.6 SMI# Two-Times Interrupt Mode 7.5.2 Fan SMI# mode： SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. （See Figure 8.7） Figure. 8.7 Two-Times Interrupt Mode - 38 - W83627HF/ F/ HG/ G 7.5.3 Temperature 1 SMI# modes The W83627HF temperature sensor 1 SMI# interrupt has two modes （1）Comparator Interrupt Mode Setting the THYST （Temperature Hysteresis） limit to 127°C will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds TO （Over Temperature） Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. （See Figure 8.8 ） Figure. 8.8 Temperature 1 SMI# Comparator Interrupt Mode （2）Two-Times Interrupt Mode Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Two-Times Interrupt Mode. Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will not occur. （See Figure 8.9） Figure. 8.9 Temperature 1 SMI# Two-Times Interrupt Mode - 39 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 7.5.4 Temperature 2, 3 SMI# modes： The W83627HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. （1）Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. （ See Figure 8.10 ） Figure. 8.10 Temperature 2, 3 SMI# Comparator Interrupt Mode （2）Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will not occur. （See Figure 8.11 ） Figure. 8.11 Temperature 2, 3 SMI# Two-Times Interrupt Mode - 40 - W83627HF/ F/ HG/ G 7.6 OVT# interrupt mode The W83627HF OVT# signal is only related to temperature sensor 2 and 3（VTIN2 / VTIN3）. They have two modes： （1）Comparator Mode： Setting Bank1/2 CR[52h] bit 2 to 0 will set OVT# signal to comparator mode. Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST.（See Figure 8.12） （2）Interrupt Mode： Setting Bank1/2 CR[52h] bit 2 to 1 will set OVT# signal to interrupt mode. Setting Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding TO, then reset, if the temperature remains above THYST, the OVT# will not be activated again.（See Figure 8.12） Figure. 8.12 OVT# Interrupt Mode - 41 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 7.7 REGISTERS AND RAM Port x5h 00h Bit 6：0 Read/write , Bit 7： Read Only 8 bits Address Register （Port x5h） Data Port： Power on Default Value Attribute： Size： 7 6 5 4 3 2 1 0 Data Bit7： Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC bus transaction. With checking this bit, multiple LPC drivers can use W83627HF hardware monitor without interfering with each other or a Serial Bus driver. It is the user's responsibility not to have a Serial Bus and LPC bus operations at the same time. This bit is： Set： with a write to Port x5h or when a Serial Bus transaction is in progress. Reset： with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus transaction is finished. Bit 6-0： Read/Write BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Busy （Power On default 0） A6 Address Pointer （Power On default 00h） A5 A4 A3 A2 A1 A0 - 42 - W83627HF/ F/ HG/ G Address Pointer Index （A6-A0） REGISTERS AND RAM A6-A0 IN HEX POWER ON VALUE OF REGISTERS IN BINARY NOTES Configuration Register Interrupt Status Register 1 Interrupt Status Register 2 SMI#Ý Mask Register 1 SMIÝ Mask Register 2 NMI Mask Register 1 NMI Mask Register 2 VID/Fan Divisor Register Serial Bus Address Register VID4 & Device ID Register Temperature 2 and Temperature 3 Serial Bus Address Register Pin Control Register IRQ/OVT# Property Select Register FAN IN/OUT and BEEP Control Register Register 50h-5Fh Bank Select Register 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 00001000 00000000 00000000 00000000 00000000 00000000 01000000 = 0101; = VID3-VID0 = 0 ; = 0101101 = 0000001; = VID4 = 00000001 = 01000100 = 00000000 = 00010101 = 1 ; Auto-increment to the address of NMI Mask Register 2 after a read or write to Port x6h Auto-increment to the address of SMIÝ Mask Register 2 after a read or write to Port x6h. Auto-increment to the address of Interrupt Status Register 2 after a read or write to Port x6h. 4Ah 4Bh 4Ch 4Dh 4Eh = Reserved ; = 000 - 43 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Address Pointer Index（A6-A0）, continued REGISTERS AND RAM A6-A0 IN HEX POWER ON VALUE OF REGISTERS IN BINARY NOTES Winbond Vendor ID Register 4Fh = 01011100 （High Byte） = 10100011 （LOW BYTE） Auto-increment to the next location after a read or write to Port x6h and stop at 1Fh. Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh. POST RAM Value RAM Value RAM 00-1Fh 20-3Fh 60-7Fh Bank1 50h-56h Bank2 50h-56h Bank4 50h-5Dh Temperature 2 Registers Temperature 3 Registers Additional Configuration Registers Data Register （Port x6h） Data Port： Power on Default Value： Attribute： Size： Port x6h 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0： Data to be read from or to be written to RAM and Register. - 44 - W83627HF/ F/ HG/ G Configuration Register - Index 40h Register Location： 40h Power on Default Value： Attribute： Size： 7 01h Read/write 8 bits 6 5 4 3 2 1 0 START SMI#Enable RESERVED INT_Clear RESERVED RESERVED RESERVED INITIALIZATION Bit 7： A one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. Bit 6： Reserced Bit 5： Reserved Bit 4： Reserved Bit 3： A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2： Reserved Bit 1： A one enables the SMI# Interrupt output. Bit 0： A one enables startup of monitoring operations, a zero puts the part in standby mode. Note： The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. Interrupt Status Register 1 - Index 41h Register Location： Power on Default Value： Attribute： Size： 7 41h 00h Read Only 8 bits 6 5 4 3 2 1 0 VCOREA VCOREB +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 - 45 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Bit 7： A one indicates the fan count limit of FAN2 has been exceeded. Bit 6： A one indicates the fan count limit of FAN1 has been exceeded. Bit 5： A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2. Bit 4： A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1. Bit 3： A one indicates a High or Low limit of +5VIN has been exceeded. Bit 2： A one indicates a High or Low limit of +3.3VIN has been exceeded. Bit 1： A one indicates a High or Low limit of VCOREB has been exceeded. Bit 0： A one indicates a High or Low limit of VCOREA has been exceeded. Interrupt Status Register 2 - Index 42h Register Location： Power on Default Value： Attribute： Size： 7 6 42h 00h Read Only 8 bits 5 4 3 2 1 0 +12VIN -12VIN -5VIN FAN3 Chassis Intrusion Temp3 Reserved Reserved Bit 7-6： Reserved.This bit should be set to 0. Bit 5： A “1” indicates a High limit of VTIN3 has been exceeded from temperature sensor 3. Bit 4： A “1” indicates Chassis Intrusion Event Occur. When CASEOPEN#（Pin 76）gone logic low, this bit will be set “1”. Bit 3： A “1” indicates the fan count limit of FAN3 has been exceeded. Bit 2： A “1” indicates a High or Low limit of -5VIN has been exceeded. Bit 1： A “1” indicates a High or Low limit of -12VIN has been exceeded. Bit 0： A “1” indicates a High or Low limit of +12VIN has been exceeded. - 46 - W83627HF/ F/ HG/ G SMI# Mask Register 1 - Index 43h Register Location： Power on Default Value： Attribute： Size： 7 43h 00h Read/Write 8 bits 6 5 4 3 2 1 0 VCOREA VCOREB +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 Bit 7-0： A one disables the corresponding interrupt status bit for SMI interrupt. SMI# Mask Register 2 - Index 44h Register Location： Power on Default Value： Attribute： Size： 7 44h 00h Read/Write 8 bits 6 5 4 3 2 1 0 +12VIN -12VIN -5VIN FAN3 Chassis Intrusion TEMP3 Reserved Reserved Bit 7-6： Reserved. This bit should be set to 0. Bit 5-0： A one disables the corresponding interrupt status bit for SMI interrupt. - 47 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Reserved Register - Index 45h This register is reserved. Chassis Clear Register - Index 46h （Not available for A Version） Register Location： Power on Default Value： Attribute： Size： 7 46h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear Bit 7： Clear Chassis Intrusion Event. Write “1” will make Hardware Monitor Register Index 42, bit 4 cleared to “0”）. This bit self clears after clearing Chassis Intrusion event. For W83627HF A Version, Clear Chassis Intrusion Event has been changed form this bit to LDA CRE6[6]. Bit 6-0：Reserved, and should be set to 0. VID/Fan Divisor Register - Index 47h Register Location： Attribute： Size： 47h Read/Write 8 bits 7 6 5 4 3 2 1 0 Power on Default Value： is 0101, is mapped to VID VID0 VID1 VID2 VID3 FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1 Bit 7-6： FAN2 Speed Control. - 48 - W83627HF/ F/ HG/ G Bit 5-4： FAN1 Speed Control. Bit 3-0： The VID inputs Note: Please refer to Bank0 CR[5Dh] , Fan divisor table. Serial Bus Address Register - Index 48h Register Location： 48h Power on Default Value： Size： 7 6 2Dh 8 bits 5 4 3 2 1 0 Serial Bus Address Reserved Bit 7： Read Only - Reserved. Bit 6-0： Read/Write - Serial Bus address . Value RAM ⎯ Index 20h- 3Fh or 60h - 7Fh （auto-increment） ADDRESS A6-A0 ADDRESS A6-A0 WITH AUTO-INCREMENT DESCRIPTION 20h 21h 22h 23h 24h 25h 26h 27h 28h 60h 61h 62h 63h 64h 65h 66h 67h 68h VCOREA reading VCOREB reading +3.3VIN reading +5VIN reading +12VIN reading -12VIN reading -5VIN reading VTIN1 reading FAN1 reading Note： This location stores the number of counts of the internal clock per revolution. FAN2 reading 29h 69h Note： This location stores the number of counts of the internal clock per revolution. - 49 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Value RAM ⎯ Index 20h- 3Fh or 60h - 7Fh （auto-increment）, continued ADDRESS A6-A0 ADDRESS A6-A0 WITH AUTO-INCREMENT DESCRIPTION FAN3 reading 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh Note： This location stores the number of counts of the internal clock per revolution. VCOREA High Limit, default value is defined by Vcore Voltage +0.2v. VCOREA Low Limit, default value is defined by Vcore Voltage -0.2v. VCOREB High Limit. VCOREB Low Limit. +3.3VIN High Limit +3.3VIN Low Limit +5VIN High Limit +5VIN Low Limit +12VIN High Limit +12VIN Low Limit -12VIN High Limit -12VIN Low Limit -5VIN High Limit -5VIN Low Limit Temperature sensor 1 （VTIN1） High Limit Temperature sensor 1 （VTIN1） Hysteresis Limit FAN1 Fan Count Limit Note： It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN2 Fan Count Limit 3Ch 7Ch Note： It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN3 Fan Count Limit 3Dh 3E- 3Fh 7Dh 7E- 7Fh Note： It is the number of counts of the internal clock for the Low Limit of the fan speed. Reserved Setting all ones to the high limits for voltages and fans （0111 1111 binary for temperature） means interrupts will never be generated except the case when voltages go below the low limits. Voltage ID（VID4）& Device ID Register - Index 49h - 50 - W83627HF/ F/ HG/ G Register Location： Power on Default Value： Size： 7 49h is 000,0001 binary, is mapped to VID 8 bits 6 5 4 3 2 1 0 VID4 DID Bit 7-1： Read Only - Device ID Bit 0 ： Read/Write - The VID4 inputs. Temperature 2 and Temperature 3 Serial Bus Address Register - Index 4Ah Register Location： Power on Default Value： Attribute： Size： 4Ah 01h Read/Write 8 bits 7 6 5 4 3 2 1 0 I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3 Bit 7： Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3. Bit 6-4： Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Bit 3： Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2. Bit 2-0： Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. - 51 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Pin Control Register - Index 4Bh Register Location： Power on Default Value： Attribute： Size： 4Bh 44h Read/Write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3DIV_B0 FAN3DIV_B1 Bit 7-6：Fan3 speed divisor. Please refer to Bank0 CR[5Dh] , Fan divisor table. Bit 5-4：Select A/D Converter Clock Input. = 00 - default. ADC clock select 22.5 KHz. = 01- ADC clock select 5.6 Khz.（22.5K/4） = 10 - ADC clock select 1.4Khz.（22.5K/16） = 11 - ADC clock select 0.35 Khz.（22.5K/64） Bit 3-2：Clock Input Select. = 00 - Pin 3 （CLKIN） select 14.318M Hz clock. = 01 - Default. Pin 3 （CLKIN） select 24M Hz clock. = 10 - Pin 3 （CLKIN） select 48M Hz clock . = 11 - Reserved. Pin3 no clock input. Bit 1-0：Reserved. User defined. - 52 - W83627HF/ F/ HG/ G IRQ/OVT# Property Select Register - Index 4Ch Register Location： Power on Default Value： Attribute： Size： 4Ch 00h Read/Write 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved OVTPOL DIS_OVT1 DIS_OVT2 Reserved T23_INTMode Reserved Bit 7： Reserved. User Defined. Bit 6： Set to 1, the SMI# output type of Temperature 2 and 3 is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. （default 0） Bit 5： Reserved. User Defined. Bit 4： Disable temperature sensor 3 over-temperature （OVT） output if set to 1. Default 0, enable OVT2 output through pin OVT#. Bit 3： Disable temperature sensor 2 over-temperature （OVT） output if set to 1. Default 0, enable OVT1 output through pin OVT#. Bit 2： Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1： Reserved. Bit 0： Reserved. - 53 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location： Power on Default Value： Attribute： Size： 7 6 4Dh 15h Read/Write 8 bits 5 4 3 2 1 0 FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 RESERVED DIS_ABN Bit 7： Disable power-on abnormal the monitor voltage including V-Core A and +3.3V. If these voltage exceed the limit value, the pin （Open Drain） of BEEP will drives 300Hz and 600Hz frquency signal. Write 1, the frequency will be disabled. Default is 0. After power on, the system should set 1 to this bit to 1 in order to disable BEEP. Bit 6： Reserved. Bit 5： FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high signal. Write 0, pin 18 always generates logic low signal. This bit default 0. Bit 4： FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0, this pin 18 acts as FAN control signal and the output value of FAN control is set by this register bit 5. Bit 3： FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high signal. Write 0, pin 19 always generates logic low signal. This bit default 0. Bit 2： FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0, this pin 19 acts as FAN control signal and the output value of FAN control is set by this register bit 3. Bit 1： FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high signal. Write 0, pin 20 always generates logic low signal. This bit default 0. Bit 0： FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0, this pin 20 acts as FAN control signal and the output value of FAN control is set by this register bit 1. - 54 - W83627HF/ F/ HG/ G Register 50h ~ 5Fh Bank Select Register - Index 4Eh （No Auto Increase） Register Location： Power on Default Value： Attribute： Size： 4Eh 80h Read/Write 8 bits 7 6 5 4 3 2 1 0 BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS Bit 7： HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3： Reserved. This bit should be set to 0. Bit 2-0： Index ports 0x50~0x5F Bank select. Winbond Vendor ID Register - Index 4Fh （No Auto Increase） Register Location： Power on Default Value： Attribute： Size： 4Fh = 5CA3h Read Only 16 bits 15 8 7 0 VIDH VIDL Bit 15-8： Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0： Vendor ID Low Byte if CR4E.bit7=0. Default A3h. - 55 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Winbond Test Register - Index 50h ~ 55h （Bank 0） These registers are reserved for Winbond internal use. BEEP Control Register 1 - Index 56h （Bank 0） Register Location： Power on Default Value： Attribute： Size： 7 56h 00h Read/Write 8 bits 6 5 4 3 2 1 0 EN_VCA_BP EN_VCB_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP Bit 7： Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 6： Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 5： Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 4： Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 3： Enable BEEP output from VDD （+5V）, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output. Bit 2： Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value. Bit 1： Enable BEEP output from VCOREB. Write 1, enable BEEP output, which is default value. Bit 0： Enable BEEP Output from VCOREA if the monitor value exceed the limits value. Write 1, enable BEEP output, which is default value - 56 - W83627HF/ F/ HG/ G BEEP Control Register 2 - Index 57h （Bank 0） Register Location： Attribute： Size： 57h Read/Write 8 bits 7 6 5 4 3 2 1 0 Power on Default Value： 80h EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP EN_T3_BP Reserved EN_GBP Bit 7： Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6： Reserved. This bit should be set to 0. Bit5： Enable BEEP Output from Temperature Sensor 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 4： Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable BEEP output. Default is 0. Bit 3： Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default is 0. Bit 2： Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output. Bit 1： Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output. Bit 0： Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output. - 57 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Chip ID Register - Index 58h （Bank 0） Register Location： Power on Default Value： Attribute： Size： 7 6 58h 21h Read Only 8 bits 5 4 3 2 1 0 CHIPID Bit 7： Winbond Chip ID number. Read this register will return 21h. Reserved Register - Index 59h （Bank 0） Register Location： Power on Default Value： Attribute： Size： 7 6 59h 70h Read/Write 8 bits 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved Bit 7： Reserved Bit 6： Temperature sensor diode 3. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode. Bit 5： Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode. Bit 4： Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode. Bit 3-0： Reserved - 58 - W83627HF/ F/ HG/ G PWMOUT1 Control Register - Index 5Ah （Bank 0） Register Location： Power on default value： Attribute： Size： 7 6 5Ah FFh Read/Write 8 bits 5 4 3 2 1 0 PWM1_DUTY Bit 7： PWMOUT1 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%. PWMOUT2 Control Register - Index 5Bh （Bank 0） Register Location： Power on default value： Attribute： Size： 7 6 5Bh FFh Read/Write 8 bits 5 4 3 2 1 0 PWM2_DUTY Bit 7： PWMOUT2 duty cycle control. Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%. - 59 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G PWMOUT1/2 Clock Select Register - Index 5Ch （Bank 0） Register Location： Power on Default Value： Attribute： Size： 5Ch 11h Read/Write 8 bits 7 6 5 4 3 2 1 0 PWM1CLKSEL PWM1CLKSEL PWM1CLKSEL Reserved PWM2CLKSEL PWM2CLKSEL PWM2CLKSEL Reserved Bit 7： Reserved Bit 6-4： PWMOUT2 clock selection. The clock defined frequency is same as PWMOUT1 clock selection. Bit 3： Reserved Bit 2-0： PWMOUT1 clock Selection. = 000： 46.87K Hz = 001： 23.43K Hz （Default） = 010： 11.72K Hz = 011： 5.85K Hz = 100： 2.93K Hz - 60 - W83627HF/ F/ HG/ G VBAT Monitor Control Register - Index 5Dh （Bank 0） Register Location： Power on Default Value： Attribute： Size： 5Dh 00h Read/Write 8 bits 7 6 5 4 3 2 1 0 EN_VBAT_MNT DIODES1 DIODES2 DIODES3 RESERVE FANDIV1_B2 FANDIV2_B2 FANDIV3_B2 Bit 7： Fan3 divisor Bit 2. Bit 6： Fan2 divisor Bit 2. Bit 5： Fan1 divisor Bit 2. Bit 4： Reserved. Bit 3： Temperature sensor 3 select into thermal diode such as Pentium II CPU supported. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 2： Sensor 2 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 1： Sensor 1 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 0： Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300ms for W83627HF hardware monitor. Fan divisor table ： BIT 2 BIT 1 BIT 0 FAN DIVISOR BIT 2 BIT 1 BIT 0 FAN DIVISOR 0 0 0 0 0 0 1 1 0 1 0 1 1 2 4 8 1 1 1 1 0 0 1 1 0 1 0 1 16 32 64 128 - 61 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Reserved Register - Index 5Eh （Bank 0） This register is reserved. Reserved Register - Index 5Fh （Bank 0） This register is reserved. VTIN2 Reading（High Byte） - Index 50h （Bank 1） Register Location： Attribute： Size： 50h Read Only 8 bits 7 6 5 4 3 2 1 0 TEMP2 Bit 7： Temperature of sensor 2, which is high byte. VTIN2 Reading（Low Byte）- Index 51h （Bank 1） Register Location： Attribute： Size： 51h Read Only 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP2 Bit 7： Temperature of sensor2, which is low byte. Bit 6-0： Reserved. - 62 - W83627HF/ F/ HG/ G VTIN2 Configuration Register - Index 52h （Bank 1） Register Location： Power on Default Value Size： 52h 00h 8 bits 7 6 5 4 3 2 1 0 STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5： Read - Reserved. This bit should be set to 0. Bit 4-3： Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2： Read - Reserved. This bit should be set to 0. Bit 1： Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0： Read/Write - When set to 1 the sensor will stop monitor. VTIN2 Hysteresis（High Byte）Register - Index 53h （Bank 1） Register Location： Power on Default Value Attribute： Size： 7 6 53h 4Bh Read/Write 8 bits 5 4 3 2 1 0 THYST2 Bit 7-0： Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. - 63 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G VTIN2 Hysteresis （Low Byte） Register - Index 54h （Bank 1） Register Location： Power on Default Value Attribute： Size： 54h 00h Read/Write 8 bits 7 6 5 4 3 2 1 0 Reserved THYST2 Bit 7： Hysteresis temperature bit 0, which is low Byte. Bit 6-0： Reserved. VTIN2 Over-temperature（High Byte）Register - Index 55h （Bank 1） Register Location： Power on Default Value Attribute： Size： 55h 50h Read/Write 8 bits 7 6 5 4 3 2 1 0 TOVF2 Bit 7-0： Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. - 64 - W83627HF/ F/ HG/ G VTIN2 Over-temperature（Low Byte）Register - Index 56h （Bank 1） Register Location： Power on Default Value Attribute： Size： 56h 00h Read/Write 8 bits 7 6 5 4 3 2 1 0 Reserved TOVF2 Bit 7： Over-temperature bit 0, which is low Byte. Bit 6-0： Reserved. VTIN3 Reading（High Byte）Register - Index 50h （Bank 2） Register Location： Attribute： Size： 50h Read Only 8 bits 7 6 5 4 3 2 1 0 TEMP2 Bit 7-0： Temperature of sensor 2, which is high byte. - 65 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G VTIN3 Reading（Low Byte）Register - Index 51h （Bank 2） Register Location： Attribute： Size： 51h Read Only 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP2 Bit 7： Temperature of sensor2, which is low byte. Bit 6-0： Reserved. VTIN3 Configuration Register - Index 52h （Bank 2） Register Location： Power on Default Value： Attribute： Size： 7 52h 00h Read/Write 8 bits 6 5 4 3 2 1 0 STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5： Read - Reserved. This bit should be set to 0. Bit 4-3： Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2： Read - Reserved. This bit should be set to 0. Bit 1： Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected. Bit 0： Read/Write - When set to 1 the sensor will stop monitor. - 66 - W83627HF/ F/ HG/ G VTIN3 Hysteresis（High Byte）Register - Index 53h （Bank 2） Register Location： Power on Default Value： Attribute： Size： 7 6 53h 4Bh Read/Write 8 bits 5 4 3 2 1 0 THYST3 Bit 7-0： Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. VTIN3 Hysteresis（Low Byte）Register - Index 54h （Bank 2） Register Location： Power on Default Value： Attribute： Size： 54h 00h Read/Write 8 bits 7 6 5 4 3 2 1 0 Reserved THYST3 Bit 7： Hysteresis temperature bit 0, which is low Byte. Bit 6-0： Reserved. - 67 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G VTIN3 Over-temperature（High Byte）Register - Index 55h （Bank 2） Register Location： Power on Default Value： Attribute： Size： 55h 50h Read/Write 8 bits 7 6 5 4 3 2 1 0 TOVF3 Bit 7-0： Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. VTIN3 Over-temperature（Low Byte）Register - Index 56h（Bank 2） Register Location： Power on Default Value： Attribute： Size： 7 56h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved TOVF3 Bit 7： Over-temperature bit 0, which is low Byte. Bit 6-0： Reserved. - 68 - W83627HF/ F/ HG/ G Interrupt Status Register 3 - Index 50h （BANK4） Register Location： Power on Default Value： Attribute： Size： 7 50h 00h Read Only 8 bits 6 5 4 3 2 1 0 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2： Reserved. Bit 1： A one indicates a High or Low limit of VBAT has been exceeded. Bit 0： A one indicates a High or Low limit of 5VSB has been exceeded. SMI# Mask Register 3 - Index 51h （BANK 4） Register Location： Power on Default Value： Attribute： Size： 7 51h 00h Read/Write 8 bits 6 5 4 3 2 1 0 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2： Reserved. Bit 1： A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0： A one disables the corresponding interrupt status bit for SMI interrupt. - 69 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Reserved Register - Index 52h （Bank 4） This register is reserved for Winbond internal use. BEEP Control Register 3 - Index 53h （Bank 4） Register Location： Power on Default Value： Attribute： Size： 7 53h 00h Read/Write 8 bits 6 5 4 3 2 1 0 EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved Bit 7-6： Reserved. Bit 5： User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. （Default 0） Bit 4-2： Reserved. Bit 1： Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value. Bit 0： Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value. Temperature Sensor 1 Offset Register - Index 54h （Bank 4） Register Location： Power on Default Value： Attribute： Size： 7 6 54h 00h Read/Write 8 bits 5 4 3 2 1 0 OFFSET1 Bit 7-0： Temperature 1 base temperature. The temperature is added by both monitor value and offset value. - 70 - W83627HF/ F/ HG/ G Temperature Sensor 2 Offset Register - Index 55h （Bank 4） Register Location： Power on Default Value： Attribute： Size： 7 6 55h 00h Read/Write 8 bits 5 4 3 2 1 0 OFFSET2 Bit 7-0：Temperature 2 base temperature. The temperature is added by both monitor value and offset value. Temperature Sensor 3 Offset Register - Index 56h （Bank 4） Register Location： Power on Default Value： Attribute： Size： 7 6 56h 00h Read/Write 8 bits 5 4 3 2 1 0 OFFSET3 Bit 7-0： Temperature 3 base temperature. The temperature is added by both monitor value and offset value. Reserved Register - Index 57h ~ 58h These registers are reserved for Winbond internal use. - 71 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Real Time Hardware Status Register I - Index 59h （Bank 4） Register Location： Power on Default Value： Attribute： Size： 7 6 59h 00h Read Only 8 bits 5 4 3 2 1 0 VCOREA_STS VCOREB_STS +3.3VIN_STS +5VIN_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS Bit 7： FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6： FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 5： Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4： Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 3： +5V Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is in the limit range. Bit 2： +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of +3.3V is in the limit range. Bit 1： VCOREB Voltage Status. Set 1, the voltage of VCOREB is over the limit value. Set 0, the voltage of VCOREB is in the limit range. Bit 0： VCOREA Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the voltage of VCORE A is in the limit range. - 72 - W83627HF/ F/ HG/ G Real Time Hardware Status Register II - Index 5Ah （Bank 4） Register Location： Power on Default Value： Attribute： Size： 7 6 5Ah 00h Read Only 8 bits 5 4 3 2 1 0 +12VIN_STS -12VIN_STS -5VIN_STS FAN3_STS CASE_STS TEMP3_STS Reserved Reserved Bit 7-6： Reserved Bit 5： Temperature sensor 3 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4： Case Open Status. Acts like Index 42[4], when Chassis Intrusion Event occurs, this bit will be set 1. Until the event is cleared, this bit returns to 0. Bit 3： FAN3 Voltage Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Bit 2： -5V Voltage Status. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is during the limit range. Bit 1： -12V Voltage Status. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of 12V is during the limit range. Bit 0： +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range. Real Time Hardware Status Register III - Index 5Bh （Bank 4） Register Location： Power on Default Value： Attribute： Size： 5Bh 00h Read Only 8 bits - 73 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 7 6 5 4 3 2 1 0 5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2： Reserved. Bit 1： VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Bit 0： 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of 5VSB is in the limit range. Reserved Register - Index 5Ch （Bank 4） This register is reserved for Winbond internal use. VID Output Register - Index 5Dh （Bank 4） Register Location： Power on Default Value： Attribute： Size： 7 5Dh = 0000,0000h Read/Write 8 bits 6 5 4 3 2 1 0 VIDOUT_0 VIDOUT_1 VIDOUT_2 VIDOUT_3 VIDOUT_4 Reserved Reserved VIDOUT_EN Bit 7： VID Output Enable. Set 1, enable VID pins to output. Set 0, disable VID pins to output. Default is 0. Bit 6-5： Reserved. Bit 4-0： Set 1, VID pins drive a 1 . Set 0, VID pins drive a 0. Default is 0. - 74 - W83627HF/ F/ HG/ G Value RAM 2⎯ Index 50h - 5Ah （auto-increment） （BANK 5） ADDRESS A6-A0 AUTO-INCREMENT DESCRIPTION 50h 51h 52h 53h 54h 55h 56h 57h Winbond Test Register - Index 50h （Bank 6） This register is reserved for Winbond internal use. 5VSB reading VBAT reading Reserved Reserved 5VSB High Limit 5VSB Low Limit. VBAT High Limit VBAT Low Limit - 75 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 8. SERIAL IRQ W83627HF supports a serial IRQ scheme. This allows a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame. 8.1 Start Frame There are two modes of operation for the IRQSER Start frame： Quiet mode and Continuous mode. In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and then tristates it. This brings all the states machines of the peripherals from idle to active states. The host controller will then take over driving IRQSER signal low in the next clock and will continue driving the IRQSER low for programmable 3 to 7 clock periods. This makes the total number of clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the IRQSER high for one clock and then tri-states it. In the Continuous mode, only the host controller initiates the START frame to update IRQ/Data line information. The host controller drives the IRQSER signal low for 4 to 8 clock periods. Upon a reset, the IRQSER signal is defaulted to the Continuous mode for the host controller to initiate the first Start frame. 8.2 IRQ/Data Frame Once the start frame has been initiated, all the peripherals must start counting frames based on the rsing edge of the start pulse. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 8-1. - 76 - W83627HF/ F/ HG/ G Table 8-1 IRQSER Sampling periods IRQ/DATA FRAME SIGNAL SAMPLED # OF CLOCKS PAST START 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 32：22 IRQ0 IRQ1 SMI 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 95 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned 8.3 Stop Frame After all IRQ/Data Frames have completed, the host controller will terminate IRQSER by a Stop frame. Only the host controller can initiate the Stop frame by driving IRQSER low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the next IRQSER cycle's Sample mode is the Quiet mode. If the Stop Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode. - 77 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 9. CONFIGURATION REGISTER 9.1 Plug and Play Configuration The W83627HF/F uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83627HF/F, there are eleven Logical Devices（from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility）which correspond to eleven individual functions ： FDC （ logical device 0 ） , PRT （ logical device 1 ） , UART1 （logical device 2）, UART2（logical device 3）, KBC（logical device 5）, CIR（Consumer IR, logical device 6）, GPIO1（logical device 7）, GPIO2（logical device 8）, GPIO3（logical device 9）, ACPI （logical device A）, and hardware monitor （logical device B）. Each Logical Device has its own configuration registers （above CR30）. Host can access those registers by writing an appropriate logical device number into logical device select register at CR7. 9.1.1 9.1.1.1 Compatible PnP Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS（CR26 bit 6）can be used to select one out of these two methods of entering the Extended Function mode as follows： HEFRAS ADDRESS AND VALUE 0 1 write 87h to the location 2Eh twice write 87h to the location 4Eh twice After Power-on reset, the value on RTSA （pin 51）is latched by HEFRAS of CR26. In Compatible PnP, a specific value（87h）must be written twice to the Extended Functions Enable Register（I/O port address 2Eh or 4Eh）. Secondly, an index value （02h, 07h ~ FFh）must be written to the Extended Functions Index Register（I/O port address 2Eh or 4Eh same as Extended Functions Enable Register）to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register（I/O port address 2Fh or 4Fh）. After programming of the configuration register is finished, an additional value（AAh）should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configura- - 78 - W83627HF/ F/ HG/ G tion registers. The designer can also set bit 5 of CR26（LOCKREG）to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset （pin MR = 1）. A warm reset will not affect the configuration registers. 9.1.1.2 Extended Functions Enable Registers （EFERs） After a power-on reset, the W83627HF/F enters the default operating mode. Before the W83627HF /Fenters the extended function mode, a specific value must be programmed into the Extended Function Enable Register（EFER）so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh （as described in previous section）. 9.1.1.3 Extended Function Index Registers （EFIRs）, Extended Function Data Registers （EFDRs） After the extended function mode is entered, the Extended Function Index Register（EFIR）must be loaded with an index value （02h, 07h-FEh） to access Configuration Register 0（CR0）, Configuration Register 7（CR07）to Configuration Register FE（CRFE）, and so forth through the Extended Function Data Register（EFDR）. The EFIRs are write-only registers with port address 2Eh or 4Eh （as described in section 12.2.1）on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh （as described in section 9.2.1） on PC/AT systems. 9.1.2 Configuration Sequence To program W83627HF/F configuration registers, the following configuration sequence must be followed： （1） Enter the extended function mode （2） Configure the configuration registers （3） Exit the extended function mode 9.1.2.1 Enter the extended function mode To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers（EFERs, i.e. 2Eh or 4Eh）. 9.1.2.2 Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register（EFIR） and Extended Function Data Register（EFDR）. EFIR is located at the same address as EFER, and EFDR is located at address （EFIR+1）. First, write the Logical Device Number（i.e.,0x07）to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip（Global）Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write （or read） the desired configuration register through EFDR. - 79 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 9.1.2.3 Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. 9.1.2.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS（CR26 bit 6）is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write | ;----------------------------------------------------------------------------------MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX,2EH MOV AL,AAH OUT DX,AL - 80 - W83627HF/ F/ HG/ G 9.2 Chip（Global）Control Register BIT DESCRIPTION CR02 （Default 0x00） 7-1 0 Reserved. SWRST --> Soft Reset. CR07 Bit 7 - 0 ： Logical Device Number CR20 Bit 7 - 0 ： Device ID = 0x52 （read only）. CR21 Bit 7 - 0 ： Device Rev （read only）. VERSION DEVICE REV G J UD-A CR22 （Default 0xff） BIT 17 3A 41 DESCRIPTION 7 6 Reserved. HMPWD 0： Power down 1： No Power down URBPWD 0： Power down 1： No Power down URAPWD 0： Power down 1： No Power down PRTPWD 0： Power down 1： No Power down Reserved. FDCPWD 0： Power down 1： No Power down 5 4 3 2-1 0 - 81 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CR23 （Default 0x00） BIT DESCRIPTION 7-1 0 Reserved. IPD （Immediate Power Down）. When set to 1, it will put the whole chip into power down mode immediately. CR24 （Default 0b1s000s0s） BIT DESCRIPTION 7 EN16SA 0： 12 bit Address Qualification 1： 16 bit Address Qualification 6 CLKSEL 0： The clock input on Pin 1 should be 24 Mhz. 1： The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB （pin 83）. 5-3 2 Reserved ENKBC（Read Only） 0： KBC is disabled after hardware reset. 1： KBC is enabled after hardware reset. This bit is set/reset by power-on setting pin SOUTA（pin 54）. 1 0 Reserved PNPCVS 0： The Compatible PnP address select registers have default values. 1： The Compatible PnP address select registers have no default value. When trying to make a change to this bit, new value of PNPCVS must be complementary to the old one to make an effective change. For example, the user must set PNPCVS to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCVS is 1. The corresponding power-on setting pin is NDTRA （pin 52）. CR25 （Default 0x00） BIT DESCRIPTION 7-6 5 4 3 2-1 0 Reserved URBTRI. UART2 output pin tri-stated. URATRI. UART1 output pin tri-stated. PRTTRI. Parallel port output pin tri-stated. Reserved FDCTRI. FDC output pin tri-stated. - 82 - W83627HF/ F/ HG/ G CR26 （Default 0b0s000000） BIT DESCRIPTION 7 SEL4FDD 0： Select two FDD mode. 1： Select four FDD mode. 6 HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is NRTSA （pin 51）. HEFRAS Address and Value 0： Write 87h to the location 2E twice. 1： Write 87h to the location 4Etwice. 5 LOCKREG 0： Enable R/W Configuration Registers 1： Disable R/W Configuration Registers. 4 3 Reserve DSFDLGRQ 0： Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ 1： Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ 2 DSPRLGRQ 0： Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ 1： Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ 1 DSUALGRQ 0： Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selectingIRQ 1： Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ 0 DSUBLGRQ 0： Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ 1： Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ - 83 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CR28 （Default 0x00） BIT DESCRIPTION 7-3 2-0 Reserved. PRTMODS2 - PRTMODS0 0xx： Parallel Port Mode 100： Reserved 101： External FDC Mode 110： Reserved 111： External two FDC Mode CR29 （GPIO3 multiplexed pin selection register. VBAT powered. Default 0x00） BIT DESCRIPTION 7 PIN64S 0： SUSLED （SUSLED control bits are in CRF3 of Logical Device 9） 1： GP35 6 PIN69S 0： CIRRX# 1： GP34 5 PIN70S 0： RSMRST# 1： GP33 4 PIN71S 0： PWROK 1： GP32 3 PIN72S 0： PWRCTL# 1： GP31 2 PIN 73S 0： SLP_SX# 1： GP30 1 0 Reserved Reserved - 84 - W83627HF/ F/ HG/ G CR2A （GPIO multiplexed pin selection register 1. VCC powered. Default 0X7C） BIT DESCRIPTION 7 Port Select（select Game Port or General Purpose I/O Port 1） 0： Game Port 1： General Purpose I/O Port 1（pin121~128 select function GP10~GP17 or KBC Port 1） 6 PIN128S 0： 8042 P12 1： GP10 PIN127S 0： 8042 P13 1： GP11 PIN126S 0： 8042 P14 1： GP12 PIN125S 0： 8042 P15 1： GP13 PIN124S 0： 8042 P16 1： GP14 PIN120S 0： MSO （MIDI Serial Output） 1： IRQIN0 （select IRQ resource through CRF4 Bit 7-4 of Logical Device 8） PIN119S 0： MS1 （MIDI Serial Input） 1： GP20 5 4 3 2 1 1 - 85 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CR2B（GPIO multiplexed pin selection register 2. VCC powered. Default 0XC0） BIT DESCRIPTION 7 PIN92S 0： SCL 1： GP21 6 PIN91S 0： SDA 1： GP22 5 PIN90S 0： PLED （PLED0 control bits are in CRF5 of Logical Device 8） 1： GP23 4 PIN89S 0： WDTO （Watch Dog Timer is controlled by CRF5, CRF6, CRF7 of Logical Device 8） 1： GP24 3 PIN88S 0： IRRX 1： GP25 2 PIN87S 0： IRTX 1： GP26 1-0 PIN 2S 00： DRVDEN1 01： SMI# 10： IRQIN1（select IRQ resource through CRF4 Bit 7-4 of Logical Device8） 11： GP27 CR2C （Default 0x00） Reserved CR2E （Default 0x00） Test Modes： Reserved for Winbond. CR2F （Default 0x00） Test Modes： Reserved for Winbond. - 86 - W83627HF/ F/ HG/ G 9.3 Logical Device 0 （FDC） BIT DESCRIPTION CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactived CR60, CR 61 （Default 0x03, 0xf0 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select FDC I/O base address [0x100：0xFF8] on 8 bytes boundary. CR70 （Default 0x06 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for FDC. CR74 （Default 0x02 if PNPCVS = 0 during POR, default 0x04 otherwise） BIT DESCRIPTION 7-3 2-0 Reserved. These bits select DRQ resource for FDC. 000： DMA0 001： DMA1 010： DMA2 011： DMA3 100 ~ 111： No DMA active - 87 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CRF0 （Default 0x0E） FDD Mode Register BIT DESCRIPTION 7 FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. 0： The internal pull-up resistors of FDC are turned on.（Default） 1： The internal pull-up resistors of FDC are turned off. 6 INTVERTZ This bit determines the polarity of all FDD interface signals. 0： FDD interface signals are active low. 1： FDD interface signals are active high. 5 DRV2EN （PS2 mode only） When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. 4 Swap Drive 0, 1 Mode 0： No Swap （Default） 1： Drive and Motor sel 0 and 1 are swapped. 3-2 Interface Mode 11： AT Mode （Default） 10： Reserved 01： PS/2 00： Model 30 1 FDC DMA Mode 0： Burst Mode is enabled 1： Non-Burst Mode （Default） 0 Floppy Mode 0： Normal Floppy Mode （Default） 1： Enhanced 3-mode FDD - 88 - W83627HF/ F/ HG/ G CRF1 （Default 0x00） BIT DESCRIPTION 7-6 Boot Floppy 00： FDD A 01： FDD B 10： FDD C 11： FDD D 5-4 3-2 Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Density Select 00： Normal （Default） 01： Normal 10： 1 （Forced to logic 1） 11： 0 （Forced to logic 0） 1 DISFDDWR 0： Enable FDD write. 1： Disable FDD write（forces pins WE, WD stay high）. SWWP 0： Normal, use WP to determine whether the FDD is write protected or not. 1： FDD is always write-protected. 0 CRF2 （Default 0xFF） BIT DESCRIPTION 7-6 5-4 3-2 1-0 FDD D Drive Type FDD C Drive Type FDD B Drive Type FDD A Drive Type - 89 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CRF4 （Default 0x00） FDD0 Selection： BIT DESCRIPTION 7 6 Reserved. Precomp. Disable. 1： Disable FDC Precompensation. 0： Enable FDC Precompensation. 5 4-3 Reserved. DRTS1, DRTS0： Data Rate Table select （Refer to TABLE A）. 00： Select Regular drives and 2.88 format 01： 3-mode drive 10： 2 Meg Tape 11： Reserved 2 1-0 Reserved. DTYPE0, DTYPE1： Drive Type select （Refer to TABLE B）. CRF5 （Default 0x00） FDD1 Selection： Same as FDD0 of CRF4. TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 DATA RATE DRATE1 DRATE0 SELECTED DATA RATE MFM FM SELDEN 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K --250K 150K 125K --250K 250K 125K --250K --125K 1 1 0 0 1 1 0 0 1 1 0 0 - 90 - W83627HF/ F/ HG/ G TABLE B DTYPE0 0 0 1 1 DTYPE1 0 1 0 1 DRVDEN0（pin 1） DRVDEN1（pin 2） SELDEN DRATE1 SELDEN DRIVE TYPE 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” （3-MODE） DRATE0 DRATE0 DRATE0 DRATE1 DRATE0 9.4 Logical Device 1 （Parallel Port） BIT DESCRIPTION CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactived CR60, CR 61 （Default 0x03, 0x78 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select Parallel Port I/O base address. [0x100：0xFFC] on 4 byte boundary（EPP not supported）or [0x100：0xFF8] on 8 byte bounda （all modes supported, EPP is only available when the base address is on 8 byte boundary）. CR70 （Default 0x07 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for Parallel Port. CR74 （Default 0x04） BIT DESCRIPTION 7-3 2-0 Reserved. These bits select DRQ resource for Parallel Port. 000： DMA0 001： DMA1 010： DMA2 011： DMA3 100 ~ 111： No DMA active - 91 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CRF0 （Default 0x3F） BIT DESCRIPTION 7 6-3 2-0 Reserved. ECP FIFO Threshold. Parallel Port Mode （CR28 PRTMODS2 = 0） 100：Printer Mode （Default） 000：Standard and Bi-direction（SPP）mode 001：EPP - 1.9 and SPP mode 101：EPP - 1.7 and SPP mode 010：ECP mode 011：ECP and EPP - 1.9 mode 111：ECP and EPP - 1.7 mode - 92 - W83627HF/ F/ HG/ G 9.5 Logical Device 2 （UART A） BIT DESCRIPTION CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactived CR60, CR 61 （Default 0x03, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select Serial Port 1 I/O base address [0x100：0xFF8] on 8 byte boundary. CR70 （Default 0x04 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for Serial Port 1. CRF0 （Default 0x00） BIT DESCRIPTION 7-2 1-0 Reserved. SUACLKB1, SUACLKB0 00： UART A clock source is 1.8462 Mhz （24MHz/13） 01： UART A clock source is 2 Mhz （24MHz/12） 10： UART A clock source is 24 Mhz （24MHz/1） 11： UART A clock source is 14.769 Mhz （24mhz/1.625） - 93 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 9.6 Logical Device 3 （UART B） BIT DESCRIPTION CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactived CR60, CR 61 （Default 0x02, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise） These two registers select Serial Port 2 I/O base address [0x100：0xFF8] on 8 byte boundary. CR70 （Default 0x03 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for Serial Port 2. CRF0 （Default 0x00） BIT DESCRIPTION 7-4 3 Reserved. RXW4C 0： No reception delay when IR is changed from TX mode to RX mode. 1： Reception delays 4 characters time （40 bit-time） when SIR is changed from TX mode to RX mode. TXW4C 0： No transmission delay when SIR is changed from RX mode to TX mode. 1： Transmission delays 4 characters time （40 bit-time） when SIR is changed from RX mode to TX mode. SUBCLKB1, SUBCLKB0 00： UART B clock source is 1.8462 Mhz （24MHz/13） 01： UART B clock source is 2 Mhz （24MHz/12） 10： UART B clock source is 24 Mhz （24MHz/1） 11： UART B clock source is 14.769 Mhz （24mhz/1.625） 2 1-0 - 94 - W83627HF/ F/ HG/ G CRF1 （Default 0x00） BIT DESCRIPTION 7 6 Reserved. IRLOCSEL. IR I/O pins' location select. 0： Through SINB/SOUTB. 1： Through IRRX/IRTX. 5 4 3 IRMODE2. IR function mode selection bit 2. IRMODE1. IR function mode selection bit 1. IRMODE0. IR function mode selection bit 0. IR MODE IR FUNCTION IRTX IRRX 00X 010* 011* 100 101 110 111* Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR tri-state Active pulse 1.6 μS Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Note： The notation is normal mode in the IR function. BIT DESCRIPTION 2 HDUPLX. IR half/full duplex function select. 0： The IR function is Full Duplex. 1： The IR function is Half Duplex. TX2INV 0： the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. 1： inverse the SOUTB pin of UART B function or IRTX pin of IR function. RX2INV. 0： the SINB pin of UART B function or IRRX pin of IR function in normal condition. 1： Inverse the SINB pin of UART B function or IRRX pin of IR function 1 0 - 95 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 9.7 Logical Device 5 （KBC） BIT DESCRIPTION CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） 7-1 0 Reserved. Logic device activation control. 1： Active 0： Inactived CR60, CR 61 （Default 0x00, 0x60 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the first KBC I/O base address [0x100：0xFFF] on 1 byte boundary. CR62, CR 63 （Default 0x00, 0x64 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the second KBC I/O base address [0x100：0xFFF] on 1 byte boundary. CR70 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for KINT （keyboard）. CR72 （Default 0x0C if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for MINT （PS2 Mouse） CRF0 （Default 0x80） BIT DESCRIPTION 7-6 KBC clock rate selection 00： Select 6MHz as KBC clock input. 01： Select 8MHz as KBC clock input. 10： Select 12Mhz as KBC clock input. 11： Select 16Mhz as KBC clock input. 5-3 2 1 0 Reserved. 0： Port 92 disable. 1： Port 92 enable. 0： Gate20 software control. 1： Gate20 hardware speed up. 0： KBRST software control. 1： KBRST hardware speed up. - 96 - W83627HF/ F/ HG/ G 9.8 Logical Device 6 （CIR） BIT DESCRIPTION CR30 （Default 0x00） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactived CR60, CR 61 （Default 0x00, 0x00） These two registers select CIR I/O base address [0x100：0xFF8] on 8 byte boundary. CR70 （Default 0x00） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for CIR. 9.9 Logical Device 7 （Game Port, MIDI Port and GPIO Port 1） BIT DESCRIPTION CR30 （Default 0x00） 7-3 2 Reserved MIDI Port activation control 1： Enable（MIDI Port will be active individually even though CR30[0] is set “0”） 0： Disbale 1 Game Port activation control 1： Enable（Game Port will be active individually even though CR30[0] is set “0”） 0： Disable 0 Logic device activation control 1： Active 0： Inactived CR60, CR 61 （Default 0x02, 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the Game Port base address [0x100：0xFFF] on 1 byte boundary. CR62, CR 63 （Default 0x03, 0x30 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the MIDI Port base address [0x100：0xFFF] on 2 byte boundary. - 97 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CR70 （Default 0x09 if PNPCVS = 0 during POR, default 0x00 otherwise） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for MIDI Port. CRF0 （GP10-GP17 I/O selection register. Default 0xFF） When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 （GP10-GP17 data register. Default 0x00） If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 （GP10-GP17 inversion register. Default 0x00） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 （Reserved） This register is reserved. 9.10 Logical Device 8 （GPIO Port 2 and Watch Dog Timer） BIT DESCRIPTION CR30 （Default 0x00） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactive CRF0 （GP20-GP27 I/O selection register. Default 0xFF） When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 （GP20-GP27 data register. Default 0x00） If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 （GP20-GP27 inversion register. Default 0x00） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 98 - W83627HF/ F/ HG/ G CRF3 （Default 0x00） BIT DESCRIPTION 7-4 3-0 These bits select IRQ resource for IRQIN1. These bits select IRQ resource for IRQIN0. CRF4 （Reserved） This register is reserved.. CRF5 （PLED mode register. Default 0x00） BIT DESCRIPTION 7-6 PLED mode select 00： Power LED pin is tri-stated. 01： Power LED pin is drived low. 10： Power LED pin is a 1Hz toggle pulse with 50 duty cycle 11： Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. 5-4 3 Reserved WDTO count mode select 0： Second 1： Minute 2 Enable the rising edge of keyboard Reset（P20）to force Time-out event. 0： Disable 1： Enable 1-0 Reserved CRF6 （Default 0x00） Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. If the Bit 7 and Bit 6 are set, any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previously-loaded non-zero value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. BIT DESCRIPTION 7-0 0x00 Time-out Disable 0x01 Time-out occurs after 1 sec / min 0x02 Time-out occurs after 2 sec / min 0x03 Time-out occurs after 3 sec / min . . . . 0xFF Time-out occurs after 255 sec / min Publication Release Date: June 09, 2006 Revision 2.27 - 99 - W83627HF/ F/ HG/ G CRF7 （Default 0x00） BIT DESCRIPTION 7 Mouse interrupt reset Enable or Disable 1： Watch Dog Timer is reset upon a Mouse interrupt 0： Watch Dog Timer is not affected by Mouse interrupt Keyboard interrupt reset Enable or Disable 1： Watch Dog Timer is reset upon a Keyboard interrupt 0： Watch Dog Timer is not affected by Keyboard interrupt Force Watch Dog Timer Time-out, Write only 1： Force Watch Dog Timer time-out event; this bit is self-clearing. Watch Dog Timer Status, R/W 1： Watch Dog Timer time-out occurred 0： Watch Dog Timer counting These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI. 6 5 4 3 -0 9.11 Logical Device 9 （GPIO Port 3, VSB powered） BIT DESCRIPTION CR30 （Default 0x00） 7-1 0 Reserved Logic device activation control 1： Active 0： Inactived CRF0 （GP30-GP35 I/O selection register. Default 0xFF Bit 7-6： Reserve） When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 （GP30-GP35 data register. Default 0x00 Bit 7-6： Reserve） If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 （GP30-GP35 inversion register. Default 0x00 Bit 7-6： Reserve） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 100 - W83627HF/ F/ HG/ G CRF3 （SUSLED mode register. Default 0x00） BIT DESCRIPTION 7-6 Select Suspend LED mode.（VSB powered） 00： Suspend LED pin is drived low. 01： Suspend LED pin is tri-stated. 10： Suspend LED pin is a 1Hz toggle pulse with 50 duty cycle. 11： Suspend LED pin is a 1/4Hz toggle pulse with 50 duty cycle. 5-0 Reserved. 9.12 Logical Device A （ACPI） BIT DESCRIPTION CR30 （Default 0x00） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactive CR70 （Default 0x00） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resources for PME . CRE0 （Default 0x00） BIT DESCRIPTION 7 DIS-PANSW_IN. Disable panel switch input to turn system power supply on. 0： PANSW_IN is wire-ANDed and connected to PANSW_OUT. 1： PANSW_IN is blocked and can not affect PANSW_OUT. 6 ENKBWAKEUP. Enable Keyboard to wake-up system via PANSW_OUT. 0： Disable Keyboard wake-up function. 1： Enable Keyboard wake-up function. 5 ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT. 0： Disable Mouse wake-up function. 1： Enable Mouse wake-up function. 4 MSRKEY. Select Mouse Left/Right Botton to wake-up system via PANSW_OUT. 0： Select click on Mouse Left-botton to wake the system up. 1： Select click on Mouse right-botton to wake the system up. - 101 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CRE0 （Default 0x00）, continued BIT DESCRIPTION 3 ENCIRWAKEUP. Enable CIR to wake-up system via PANSW_OUT. 0： Disable CIR wake-up function. 1： Enable CIR wake-up function. 2 KB/MS Swap. Enable Keyboard/Mouse port-swap. 0： Keyboard/Mouse ports are not swapped. 1： Keyboard/Mouse ports are swapped. 1 MSXKEY. Select either single or double click to wake-up the system. 0： Indicates mouse double click can wake the system up. 1： Indicates mouse single click can wake the system up. 0 KBXKEY. Enable any character received from Keyboard to wake-up the system 0： Only predetermined specific key combination can wake up the system. 1： Any character received from Keyboard can wake up the system. CRE1（Default 0x00）Keyboard Password Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or predetermined key Register is to be read or written via CRE2. CRE2 Keyboard Password Wake-Up Data Register This register holds the value of wake-up key register indicated by CRE1. W83627HF supports at most 5-key password wake-up function. CRE1 is an index register to indicate which byte of key code storage (0X00 ~ 0X0E) is going to be read or written. According to IBM 101/102 keyboard specification, a complete key code contains a 1-byte make code and a 2byte break code. For example.The make code of Key “0” is 0x45, and the corresponding break code is 0xF0, 0x45. The approach to implement Keyboard Password Wake-up function is to fill key codes into the password storage. Assume that we want to set “012” as the password. The storage must be filled as below. Please note that index 0x09 ~ 0x0e must be filled as 0x00 since the password has only three words. Index Data 00 1E 01 F0 02 1E 03 16 04 F0 05 16 06 45 07 F0 08 45 09 00 0A 00 1B 00 0C 00 0D 00 0E 00 First-pressed key “0” Second-pressed key “1” Third-pressed key “2” - 102 - W83627HF/ F/ HG/ G CRE3 Keyboard/Mouse Wake-Up Status Register（Read Only） BIT DESCRIPTION 7-6 5 4 3 2 1 0 Reserved. When 1 is VSB Power Loss status. PWRLOSS_STS. This bit is set when power loss occurs. This bit is control by CRE4[7] CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared by reading this register. PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by reading this register. MOUSE_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. KB_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. CRE4 （Default 0x00） BIT DESCRIPTION 7 Power loss control bit 2. 0： Indicates that PWRCTL#（Pin 72）outputs logic low after PSOUT# issues a low pluse. 1： Indicates that PWRCTL# will output logic low after resum from AC power loss if SLP_SX（Pin 73）is logic high. 6-5 Power loss control bit 00： System always turn off when come back from power loss state. 01： System always turn on when come back from power loss state. 10： System turn on/off when come back from power loss state depend on the state before power loss. 11： Reserved. 4 Suspend clock source select 0： Use internal clock source. 1： Use external suspend clock source（32.768KHz）. 3 Keyboard wake-up type select for wake-up the system from S1/S2. 0： Password or Hot keys programmed in the registers. 1： Any key. Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs. 0： Disable. 1： Enable. 2 1-0 Reserved. - 103 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CRE5 （Default 0x00） BIT DESCRIPTION 7 6-0 Reserved Compared Code Length. When the compared codes are storaged in the data register, these data length should be written to this register. CRE6 （Default 0x00） BIT DESCRIPTION 7 6 Reserved Chassis Status Clear.（availibale for A Version only） 1： Clear CASEOPEN#（Pin 76）event. 0： Disable clear function. Set this bit to “1” will make hardware monitor register index 42, bit 4 cleared unceasingly. Therefore, next Case-open Event can not be triggered again until this bit Is cleared to “0”. This bit is available for W83627HF A Version only, please refer to Hardware Monitor Register Index 46, bit 7 for other version. CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz divided by（ CIR Baud Rate Divisor + 1）. 5-0 CRE7 （Default 0x00） BIT DESCRIPTION 7 6 5 4 3 Reaerved. Reserved. Reserved. Reserved. SELWDTORST. Watch Dog Timer Reset Control. 0： Indicates that Watch Dog Timer is reset by LPC_RST. 1： Indicates that Watch Dog Timer is reset by PWR_OK. 2 1 Reset CIR Power-On function. After using CIR power-on, the software should write logical 1 to restart CIR power-on function. Invert RX Data. 1： Inverting RX Data. 0： Not inverting RX Data. 0 Enable Demodulation. 1： Enable received signal to demodulate. 0： Disable received signal to demodulate. - 104 - W83627HF/ F/ HG/ G CRF0 （Default 0x00） BIT DESCRIPTION 7 CHIPPME. Chip level auto power management enable. 0： Disable the auto power management functions 1： Enable the auto power management functions. CIRPME. Consumer IR port auto power management enable. 0： Disable the auto power management functions 1： Enable the auto power management functions. MIDIPME. MIDI port auto power management enable. 0： Disable the auto power management functions 1： Enable the auto power management functions. Reserved. Return zero when read. PRTPME. Printer port auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. FDCPME. FDC auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. URAPME. UART A auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. URBPME. UART B auto power management enable. 0： Disable the auto power management functions. 1： Enable the auto power management functions. 6 5 4 3 2 1 0 CRF1 （Default 0x00） BIT DESCRIPTION 7 WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. 0： the chip is in the sleeping state. 1： the chip is in the working state. 6-5 4 3-0 Devices' trap status. Reserved. Return zero when read. Devices' trap status. - 105 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CRF3 （Default 0x00） BIT DESCRIPTION 7-6 5-0 5 4 3 2 1 0 Reserved. Return zero when read. Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. MOUIRQSTS. MOUSE IRQ status. KBCIRQSTS. KBC IRQ status. PRTIRQSTS. printer port IRQ status. FDCIRQSTS. FDC IRQ status. URAIRQSTS. UART A IRQ status. URBIRQSTS. UART B IRQ status. CRF4 （Default 0x00） BIT DESCRIPTION 7-6 5-0 5 4 3 1 0 Reserved. Return zero when read. These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a1. Writing a 0 has no effect. HMIRQSTS. Hardware monitor IRQ status. WDTIRQSTS. Watch dog timer IRQ status. CIRIRQSTS. Consumer IR IRQ status. IRQIN1STS. IRQIN1 status. IRQIN0STS. IRQIN0 status. CRF6 （Default 0x00） BIT DESCRIPTION 7-6 5-0 Reserved. Return zero when read. Enable bits of the SMI / PME generation due to the device's IRQ. These bits enable the generation of a SMI / PME interrupt due to any IRQ of the devices. SMI / PME logic output =（MOUIRQEN and MOUIRQSTS）or（KBCIRQEN and KBCIRQSTS）or（PRTIRQEN and PRTIRQSTS）or（FDCIRQEN and FDCIRQSTS） or（URAIRQEN and URAIRQSTS）or（URBIRQEN and URBIRQSTS）or （HMIRQEN and HMIRQSTS）or（WDTIRQEN and WDTIRQSTS）or （IRQIN3EN and IRQIN3STS）or（IRQIN2EN and IRQIN2STS）or （IRQIN1EN and IRQIN1STS）or（IRQIN0EN and IRQIN0STS） 5 MOUIRQEN. 0： Disable the generation of an SMI / PME interrupt due to MOUSE's IRQ. 1： Enable the generation of an SMI / PME interrupt due to MOUSE's IRQ. - 106 - W83627HF/ F/ HG/ G CRF6 （Default 0x00）, continued. BIT DESCRIPTION 4 KBCIRQEN. 0： Disable the generation of an SMI / PME interrupt due to KBC's IRQ. 1： Enable the generation of an SMI / PME interrupt due to KBC's IRQ. PRTIRQEN. 0： Disable the generation of an SMI / PME interrupt due to printer port's IRQ. 1： Enable the generation of an SMI / PME interrupt due to printer port's IRQ. FDCIRQEN. 0： Disable the generation of an SMI / PME interrupt due to FDC's IRQ. 1： Enable the generation of an SMI / PME interrupt due to FDC's IRQ. URAIRQEN. 0： Disable the generation of an SMI / PME interrupt due to UART A's IRQ. 1： Enable the generation of an SMI / PME interrupt due to UART A's IRQ. URBIRQEN. 0： Disable the generation of an SMI / PME interrupt due to UART B's IRQ. 1： Enable the generation of an SMI / PME interrupt due to UART B's IRQ. 3 2 1 0 CRF7 （Default 0x00） BIT DESCRIPTION 7-6 5-0 5 Reserved. Return zero when read Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ. HMIRQEN. 0： Disable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. 1： Enable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. 4 WDTIRQEN. 0： Disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. 1： Enable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. 3 CIRIRQEN. 0： Disable the generation of an SMI / PME interrupt due to CIR's IRQ. 1： Enable the generation of an SMI / PME interrupt due to CIR's IRQ 2 MIDIIRQEN. 0： Disable the generation of an SMI / PME interrupt due to MIDI's IRQ. 1： Enable the generation of an SMI / PME interrupt due to MIDI's IRQ. - 107 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G CRF7 （Default 0x00）, continued BIT DESCRIPTION 1 IRQIN1EN. 0： Disable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. 1： Enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. 0 IRQIN0EN. 0： Disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. 1： Enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. CRF9 （Default 0x00） BIT DESCRIPTION 7-3 2 Reserved. Return zero when read. PME_EN： Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that： this bit is valid only when SMIPME_OE = 1. 0： The power management events will generate an SMI event 1： The power management events will generate an PME event. 1 0 Reserved. SMIPME_OE： This is the SMI and PME output enable bit. 0： Neither SMI nor PME will be generated. Only the IRQ status bit is set. 1： An SMI or PME event will be generated. CRFE, FF （Default 0x00） Reserved for Winbond test. 9.13 Logical Device B （Hardware Monitor） BIT DESCRIPTION CR30 （Default 0x00） 7-1 0 Reserved. Logic device activation control 1： Active 0： Inactived CR60, CR 61 （Default 0x00, 0x00） These two registers select Hardware Monitor base address [0x100：0xFFF] on 8-byte boundary. - 108 - W83627HF/ F/ HG/ G CR70 （Default 0x00） BIT DESCRIPTION 7-4 3-0 Reserved. These bits select IRQ resource for Hardware Monitor. CRF0 （Default 0x00） BIT DESCRIPTION 7-1 0 Reserved. Disable initial abnormal beep （VcoreA and +3.3 V） 0： Enable power-on abnormal beep 1： Disable power-on abnormal beep - 109 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 10. SPECIFICATIONS 10.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage （5V） Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature -0.5 to 7.0 -0.5 to VDD+0.5 2.2 to 4.0 0 to +70 -55 to +150 V V V °C °C Note： Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 10.2 DC CHARACTERISTICS （Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V） PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage IBAT IBAT 2.4 2.0 uA mA VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected. I/O8t - TTL level bi-directional pin with 8mA source-sink capability VIL VIH VOL VOH ILIH ILIL VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 2.4 +10 -10 0.8 2.0 0.4 0.8 V V V V μA μA V V V V μA μA IOL = 12 mA IOH = -12 mA VIN = 5V VIN = 0V IOL = 8 mA IOH = - 8 mA VIN = 5V VIN = 0V I/O12t - TTL level bi-directional pin with 12mA source-sink capability - 110 - W83627HF/ F/ HG/ G DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O24t - TTL level bi-directional pin with 24mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V μA μA V V 0.4 2.4 +10 -10 V V μA μA V V V 0.4 2.4 +10 -10 V V μA μA V V V 0.4 2.4 +10 V V μA VDD=5V IOL = 24 mA IOH = -24 mA VIN = 5V VDD=5V IOL = 12 mA IOH = -12 mA VIN = 5V VIN = 0V IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V IOL = 24 mA IOH = -24 mA VIN = 5V VIN = 0V I/O12tp3 – 3.3V TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.0 0.8 I/O12ts - TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 I/O24ts - TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage VtVt+ VTH VOL VOH ILIH 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 - 111 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS Input Low Leakage ILIL -10 μA V V V VIN = 0V I/O24tsp3 – 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 VDD=3.3V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V V V μA μA V V V μA μA I/OD12t - TTL level bi-directional pin and open-drain output with 12mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 0.8 IOL = 12 mA VIN = 5V VIN = 0V I/OD24t - TTL level bi-directional pin and open-drain output with 24mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 0.8 V V V μA μA IOL = 24 mA VIN = 5V VIN = 0V I/OD12ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V μA μA VDD=5V IOL = 12 mA VIN = 5V VIN = 0V - 112 - W83627HF/ F/ HG/ G DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/OD24ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V μA μA VDD=5V IOL = 24 mA VIN = 5V VIN = 0V I/OD12cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V μA μA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5V VIN = 0 V I/OD16cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 16mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V μA μA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 16 mA VIN = 5V VIN = 0 V - 113 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/OD12csd - CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V μA μA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5V VIN = 0 V I/OD12csu - CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VtVt+ VTH VOL ILIH ILIL VOL VOH VOL VOH 2.4 2.4 0.4 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 0.4 1.7 3.8 V V V V μA μA V V V V VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5V VIN = 0 V IOL = 4 mA IOH = -4 mA IOL = 8 mA IOH = -8 mA O4 - Output pin with 4mA source-sink capability O8 - Output pin with 8mA source-sink capability O12 - Output pin with 12mA source-sink capability Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VOL VOH VOL VOH 2.4 2.4 0.4 0.4 V V V V IOL = 12 mA IOH = -12 mA IOL = 16 mA IOH = -16 mA O16 - Output pin with 16mA source-sink capability - 114 - W83627HF/ F/ HG/ G DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS O24 - Output pin with 24mA source-sink capability Output Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Output Low Voltage Output Low Voltage Output Low Voltage INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V μA μA V V +10 -10 μA μA V V +10 -10 μA μA VIN = 5V VIN = 0 V VIN = 3.3V VIN = 0 V VIN = 5V VIN = 0 V VOL VOH VOL VOL VOL VOL VOL 2.4 0.4 0.4 0.4 0.4 0.4 0.4 V V V V V V V IOL = 24 mA IOH = -24 mA IOL = 12 mA IOL = 24 mA IOL = 12 mA IOL = 24 mA IOL = 12 mA O12p3 - 3.3V output pin with 12mA source-sink capability O24p3 - 3.3V output pin with 24mA source-sink capability OD12 - Open drain output pin with 12mA sink capability OD24 - Open drain output pin with 24mA sink capability OD12p3 - 3.3V open drain output pin with 12mA sink capability INtp3 - 3.3V TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 0.8 INtd - TTL level input pin with internal pull down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 0.8 - 115 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS INtu - TTL level input pin with internal pull up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V μA μA V V V +10 -10 μA μA V V V +10 -10 μA μA V V +10 -10 μA μA V V +10 -10 μA μA VIN = 5V VIN = 0 V VIN = 5V VIN = 0 V VIN = 5V VIN = 0 V INts- TTL level Schmitt-trigger input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5V VIN = 0 V INtsp3 - 3.3 V TTL level Schmitt-trigger input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INc- CMOS level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 3.5 1.5 VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V INcd- CMOS level input pin with internal pull down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 3.5 1.5 - 116 - W83627HF/ F/ HG/ G DC CHARACTERISTICS, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS INcs- CMOS level Schmitt-trigger input pin Input Low Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVTH ILIH ILIL 1.3 1.5 1.5 2 +10 -10 1.7 V V μA μA V V V +10 -10 μA μA VDD = 5 V VDD = 5 V VIN = 5 V VIN = 0 V INcsu - CMOS level Schmitt-trigger input pin with internal pull up resistor Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 1.7 3.8 VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5V VIN = 0 V - 117 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 11. APPLICATION CIRCUITS 11.1 Parallel Port Extension FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram 11.2 Parallel Port Extension 2FDD JP13 WE2/SLCT WD2/PE 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension 2FDD Connection Diagram - 118 - W83627HF/ F/ HG/ G 11.3 Four FDD Mode - 119 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 12. ORDERING INSTRUCTION PART NO. KBC FIRMWARE REMARKS TM TM TM TM W83627HF-AW W83627F-AW W83627HG-AW W83627G-AW AMIKEY-2 AMIKEY-2 AMIKEY-2 AMIKEY-2 13. HOW TO READ THE TOP MARKING inbond W83627HF-AW 821A2B282012345BC inbond W83627HG-AW © AM. MEGA. 87-96 821A2B282012345BC © AM. MEGA. 87-96 inbond W83627F-AW © AM. MEGA. 87-96 821A2B282012345BC inbond W83627G-AW © AM. MEGA. 87-96 821A2B282012345BC 1st line： Winbond logo 2nd line： the type number： W83627HF-AW, W83627F-AW, W83627HG-AW, W83627G-AW （the “G” means Pb-free package） 3rd line： the source of KBC F/W -- American Megatrends IncorporatedTM 4th line： the tracking code 821 A 2 C 282012345BC 821： packages made in '98, week 21 A： assembly house ID; A means ASE, S means SPIL.... etc. 2： Winbond internal use. B： IC revision; A means version A, B means version B 282012345： wafer production series lot number BC： Winbond internal use. - 120 - W83627HF/ F/ HG/ G 14. PACKAGE DIMENSIONS （128-pin QFP） HE E 102 65 Symbol Dimension in mm Dimension in inch Min 0.25 2.57 0.10 0.10 13.90 19.90 Nom 0.35 2.72 0.20 0.15 14.00 20.00 0.50 Max 0.45 2.87 0.30 0.20 14.10 20.10 Min 0.010 0.101 0.004 0.004 0.547 0.783 Nom 0.014 0.107 0.008 0.006 0.551 0.787 0.020 Max 0.018 0.113 0.012 0.008 0.555 0.791 103 64 D HD 128 39 1 e b 38 A1 A2 b c D E e HD HE L L1 y 0 c 17.00 23.00 0.65 17.20 23.20 0.80 1.60 17.40 23.40 0.95 0.669 0.905 0.025 0.677 0.913 0.031 0.063 0.685 0.921 0.037 0.08 0 7 0 0.003 7 Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. A A2 See Detail F Seating Plane A1 L L1 Detail F y 5. PCB layout please use the "mm". - 121 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G 15. APPENDIX A ： DEMO CIRCUIT PLED VCC3V SMBDATA VCC3V SMBCLK -5VIN -12VIN +12VIN Voltage SENSING +3.3VIN VCOREB VCOREA VREF VTIN3 AVCC AGND (To monitor battery voltage, this input should be connected directly to battery) BAT VCC CAP NP R10 4.7K R2 300 R11 4.7K R1 300 R3 10K 3VSB R7 0 R12 10K IRRX IRTX RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# CASEOPEN# SUSCLK SLP_SX# From ICH S3 or S5 signal. 5VSB PWRCTL# PWROK COMB & IR Temperature Sensing To Power supply for turn ON VCC. Indicated the VCC is OK. R4 10K C5 0.1u R5 10K R8 0 VCC3V 3VSB RSMRST# CIRRX PANSWIN R6 10K 3VSB PANSWOUT# For Wake Up Function MDAT MCLK C2 VCC CAP NP 0.1u C1 CAP NP 0.1u 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 U1 C6 CAP NP 0.1u 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Keyboard & PS2 Mouse. VCC3V R13 4.7K Temperature Sensing Fan Speed Seneing & Speed Control VTIN2 VTIN1 OVT# VID4 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 FANPWM2 FANPWM1 BEEP MSI MSO GPSA2 GPSB2 GPY1 GPY2 GPX2 GPX1 GPSB1 GPSA1 MIDI PORT GAME PORT 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VTIN3 VREF VCOREA VCOREB +3.3VIN AVCC +12VIN -12VIN -5VIN AGND SCL/GP21 SDA/GP22 PLED/GP23 WDTO/GP24 IRRX/GP25 IRTX/GP26 VSS RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# VCC CASEOPEN# SUSCLKIN VBAT SLP_SX#/GP30 PWRCTL#/GP31 PWROK/GP32 RSMRST#/GP33 CIRRX/GP34 PSIN# PSOUT# MDAT MCLK VTIN2 VTIN1 OVT# VID4 VID3 VID2 VID1 VID0 FANIO3 FANIO2 FANIO1 VCC FANPWM2 FANPWM1 VSS BEEP MSI/GP20 MSO/IRQIN0 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/P16/GP14 GPX2/P15/GP13 GPX1/P14/GP12 GPSB1/P13/GP11 GPSA1/P12/GP10 W83627HF SUSLED/GP35 KDAT KCLK VSB KBRST GA20M KBLOCK# RIA# DCDA# VSS SOUTA SINA DTRA# RTSA# DSRA# CTSA# VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 5VSB SUSLED KDAT KCLK SOFTRST A20M# KEYLOCK# RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# AFD# ERR# INIT# SLIN# GND COMA VCC DRVDEN0 DRVDEN1/IRQIN1/ INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# VCC TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN PME# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 VCC3V LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 C4 CAP NP 0.1u Printer PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD[0..7] PD[0..7] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 RWC# DS1# INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# 1 OSC1 NC OUTPUT 24/48MHz 5 PME# PCICLK LDRQ# SERIRQ LDA[0..3] LFRAME# LRESET# R14 R VCC3V GND R15 4.7K LAD3 LAD2 LAD1 LAD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VCC C3 CAP NP 0.1u GND ACK# BUSY PE SLCT VCC3V HEADER 17X2 FDC VCC3V R Winbond Electronic Corp. Title Size B Date: 4.7K LAD[0..3] W83627HF CIRCUIT (LPC I/O + H/W) Document Number W83627HF + FDC Monday, August 05, 2002 Sheet 1 of 6 Rev 0.4 - 122 - W83627HF/ F/ HG/ G SUSPEND LED CIRCUIT R25 R IOVSB 150 D3 LED Q1 NPN IOVSB R21 4.7K SUSLED MDAT R22 4.7K FUSE F1 L4 FB L3 J2 1 2 3 4 5 6 HEADER 6 POWER LED CIRCUIT R27 R VCC 150 LED R28 R 4.7K PLED D4 Q2 NPN MCLK C11 47P C10 47P FB PS2 MOUSE VCC IOVSB R19 4.7K R20 4.7K L1 KDAT KCLK C9 VBAT 47P C8 47P FB L2 FB C7 .1UF J1 1 2 3 4 5 6 HEADER 5 BATTERY CIRCUIT KEYBOARD BT1 BATTERY R16 1K C13 0.1UF 3 2 1 R18 VCC JP4 HEAD3 150 KEYLOCK# JP3 1 2 3 4 5 HEADER 5 JP5:1-2 Clear CMOS 2-3 Enable ONNOW functions KEYLOCK PANEL SWITCH 5VSB IOVSB CIRCUIT R17 OnNow or Wake_up function power R26 OFF, D2,D3 ON: Wake_up fuction 0 JP2 D1 VCC 5817 C14 10u IOVSB R26 ON, D2,D3 OFF:NO Wake_up fuction R24 100 PANSWIN R23 10K 1 2 HEADER 2 C12 0.1uF D2 5VSB 5817 WINBOND ELECTRONICS CORP. Title W83627HF CIRCUIT (LPC I/O + H/M) Rev 0.4 Sheet 2 of 6 Size Document Number CustomKB & PS2 MOUSE & POWER Date: Monday, August 05, 2002 - 123 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G COM PORT VCC RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# 20 16 15 13 19 18 17 14 12 11 U2 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 (SOP20) +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V NRTSA NDTRA NSOUTA NRIA NCTSA NDSRA NSINA NDCDA -12V IR/CIR CONNECTOR NDCDA NSOUTA GND NRTSA NRIA J3 1 3 5 7 9 2 4 6 8 10 NSINA NDTRA NDSRA NCTSA VCC J5 1 2 3 4 5 CN2X5 6 7 8 9 10 CIRRX IOVSB CN2X5B COMA (UARTA) IRRX IRTX VCC RTSB# DTRB# SOUTB RIB# CTSB# DSRB# SINB DCDB# 20 16 15 13 19 18 17 14 12 11 U3 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 (SOP20) +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V NRTSB NDTRB NSOUTB NRIB NCTSB NDSRB NSINB NDCDB -12V NDCDB NSOUTB GND NRTSB NRIB J4 1 3 5 7 9 2 4 6 8 10 NSINB NDTRB NDSRB NCTSB THE IOVSB OF PIN 8 IS FOR CIR WAKE-UP FUNCTION. CN2X5B COMB (UARTB) PRT PORT 1 3 5 7 PD[0..7] PD0 PD1 PD2 PD3 1 3 5 7 RPACK1 2 4 6 8 VCC 1 RP2 10P9R-4.7K VCC 1 RP1 10P9R-4.7K 2 3 4 5 6 7 8 9 10 STB# AFD# INIT# SLIN# PD[0..7] 2 3 4 5 6 7 8 9 10 33 RPACK2 2 4 6 8 33 PD4 PD5 PD6 PD7 1 3 5 7 RPACK3 2 4 6 8 33 ERR# ACK# BUSY PE SLCT C15 180 C16 180 C17 180 C18 180 C19 180 C20 180 C21 180 C22 180 C23 180 C24 180 C25 180 C26 180 C27 180 C28 180 C29 180 C30 180 C31 180 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J6 DB25 WINBOND ELECTRONICS CORP. Title W83627HF CIRCUIT (LPC I/O + H/W) Size Document Number CustomCOM & IR & LPT PORT Date: Monday, August 05, 2002 Sheet 3 of 6 Rev 0.4 - 124 - W83627HF/ F/ HG/ G GAME & MIDI PORT CIRCUIT VCC VCC R78 L5 R INDUCTOR 100K P1 VCC R39 R 2.2K VCC R40 R 2.2K VCC R41 R 2.2K VCC R42 R 2.2K MSI GPSA2 GPSB2 GPY1 GPY2 MSO GPX2 GPX1 GPSB1 GPSA1 R29 R 2.2K R30 R 2.2K R31 R 2.2K R32 R 2.2K R33 R 2.2K R34 R 2.2K 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 CONNECTOR DB15 R38 R 1M CAP NP 0.01U C39 CAP NP 0.01U C38 R37 R 1M CAP NP 0.01U C37 R36 R 1M CAP NP 0.01U C36 R35 R 1M CAP NP 0.01U C33 CAP NP 0.01U C32 CAP NP 0.01U C34 CAP NP 0.01U C35 CAP NP 150P C40 WINBOND ELECTRONICS CORP. Title W83627HF CIRCUIT (LPC I/O + H/W) Rev 0.4 Sheet 4 of 6 Size Document Number CustomGAME & MIDI Date: Monday, August 05, 2002 - 125 - Publication Release Date: June 09, 2006 Revision 2.27 W83627HF/ F/ HG/ G Hardware Monitor circuits Temperature Sensing VREF R61 10K 1% Voltage Sensing R43 CPUVCOA (for other) CPUVCOB (for system) VCC3V 10K R44 10K R45 10K R R R VCOREA VCOREB +3.3VIN VREF R73 56K 1% R74 -12V 232K 1% -12VIN THERMISTOR R62 10K 1% T RT1 T 10K 1% 10K 1% RT2 -5VIN R75 56K 1% R76 -5V 120K 1% VTIN3 VTIN1 THERMISTOR +12V R60 VTIN2 AGND 30K D+ DC43 CAPACITOR NON-POL 3300p D+ D- R46 28K 1% R +12VIN R47 10K 1% R AGND (from Deschutes) PWM Circuit for FAN speed control +12V R58 R57 4.7K 1K Q6 PNP 3906 JP7 + 3 2 1 HEADER 3 D7 1N4148 R56 4.7K R55 27K R54 10K Beep Circuits VCC R67 100 LS1 R66 10K SPEAKER FANIO1 BEEP Q3 3904 FANPWM1 R59 510 Q4 MOSFET N 2N7002 C41 10u +12V R50 R49 4.7K 1K Q7 PNP 3906 D6 1N4148 Case Open Circuits R51 4.7K R52 27K R53 10K R77 VBAT R 1M FANIO2 CASEOPEN# FANPWM2 R48 510 Q5 MOSFET N 2N7002 C42 10u JP6 + 3 2 1 HEADER 3 S1 CASEOPEN SW CPU Voltage ID output 3VCC R68 10K R69 10K R70 10K R71 10K R72 10K Fan Speed Input Circuit +12V AVCC D5 1N4148 JP5 3 2 1 HEADER 3 Title R63 4.7K AGND R64 27K R65 10K FANIO3 L6 VCC FB L7 FB Winbond Electronic Corp. PIIVID4 PIIVID3 PIIVID2 PIIVID1 PIIVID0 VID4 VID3 VID2 VID1 VID0 W83627HF CIRCUIT (LPC I/O+ H/W) Rev 0.4 Sheet 5 of 6 Size Document Number CustomHardware Monitor Date: Monday, August 05, 2002 - 126 - W83627HF/ F/ HG/ G Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 127 - Publication Release Date: June 09, 2006 Revision 2.27