W83697HG

W83697HF/HG Data Sheet W INBOND LPC I/O W INBOND LPC I/O W 83697HF W83697HG Date: May 30, 2005 Revision: A1 -i- Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Table of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 2 BLOCK DIAGRAM FOR W83697HF .......................................................................................... 5 PIN CONFIGURATION FOR W83697HF................................................................................... 6 PIN DESCRIPTION.................................................................................................................... 7 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6. 6.1 6.2 6.3 LPC Interface .................................................................................................................. 8 FDC Interface ................................................................................................................. 9 Multi-Mode Parallel Port ............................................................................................... 10 Serial Port Interface ...................................................................................................... 15 Infrared Port .................................................................................................................. 16 Flash ROM Interface..................................................................................................... 16 Hardware Monitor Interface .......................................................................................... 17 Game Port & MIDI Port................................................................................................. 18 POWER PINS ............................................................................................................... 19 General Description ...................................................................................................... 20 Access Interface ........................................................................................................... 20 6.2.1 6.3.1 6.3.2 6.3.3 LPC interface..................................................................................................................20 Monitor over 4.096V voltage:..........................................................................................23 Monitor negative voltage:................................................................................................23 Temperature Measurement Machine..............................................................................24 Fan speed count.............................................................................................................25 Fan speed control...........................................................................................................27 Voltage SMI# mode : ......................................................................................................28 Fan SMI# mode : ............................................................................................................28 The W83697HF temperature sensor 1 SMI# interrupt has two modes: ..........................29 HARDWARE MONITOR ........................................................................................................... 20 Analog Inputs ................................................................................................................ 22 6.4 FAN Speed Count and FAN Speed Control ................................................................. 25 6.4.1 6.4.2 6.5 SMI# interrupt mode ..................................................................................................... 28 6.5.1 6.5.2 6.5.3 6.5.4 The W83697HF temperature sensor 2 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. ...................................................................................................30 6.6 OVT# interrupt mode .................................................................................................... 31 6.6.1 The W83697HF temperature sensor 2 Over-Temperature (OVT#) has the following modes 31 6.7 7. REGISTERS AND RAM ............................................................................................... 32 CONFIGURATION REGISTER ................................................................................................ 62 - ii - W83697HF/ HG 7.1 7.2 Plug and Play Configuration ......................................................................................... 62 Compatible PnP............................................................................................................ 62 7.2.1 7.2.2 7.2.3 Extended Function Registers..........................................................................................62 Extended Functions Enable Registers (EFERs) .............................................................63 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) 63 Enter the extended function mode..................................................................................63 Configurate the configuration registers ...........................................................................63 Exit the extended function mode ....................................................................................63 Software programming example .....................................................................................64 7.3 Configuration Sequence ............................................................................................... 63 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 8. 8.1 8.2 9. 9.1 9.2 9.3 10. 11. 12. 13. 14. Chip (Global) Control Register ..................................................................................... 65 Logical Device 0 (FDC)................................................................................................. 70 Logical Device 1 (Parallel Port) .................................................................................... 73 Logical Device 2 (UART A)........................................................................................... 74 Logical Device 3 (UART B)........................................................................................... 75 Logical Device 6 (CIR).................................................................................................. 76 Logical Device 7 (Game Port GPIO Port 1).................................................................. 77 Logical Device 8 (MIDI Port and GPIO Port 5) ............................................................. 78 Logical Device 9 (GPIO Port 2 ~ GPIO Port 4 ) ........................................................... 80 Logical Device A (ACPI) ............................................................................................... 82 Logical Device B (Hardware Monitor)........................................................................... 87 Absolute Maximum Ratings .......................................................................................... 88 DC CHARACTERISTICS.............................................................................................. 88 Parallel Port Extension FDD ......................................................................................... 96 Parallel Port Extension 2FDD ....................................................................................... 97 Four FDD Mode ............................................................................................................ 97 SPECIFICATIONS .................................................................................................................... 88 APPLICATION CIRCUITS ........................................................................................................ 96 ORDERING INSTRUNCTION .................................................................................................. 98 HOW TO READ THE TOP MARKING...................................................................................... 98 PACKAGE DIMENSIONS ......................................................................................................... 99 APPENDIX A : DEMO CIRCUIT ............................................................................................. 100 REVISION HISTORY .............................................................................................................. 105 - iii - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 1. GENERAL DESCRIPTION The W83697HF is evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chip-set. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83697HF's integration of Game Port and MIDI Port. It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. The disk drive adapter functions of W83697HF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83697HF greatly reduces the number of components required for interfacing with floppy disk drives. The W83697HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83697HF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83697HF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR (Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols). The W83697HF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows TM 95/98 , which makes system resource allocation more efficient than ever. The W83697HF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode (VCC is off). The W83697HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide, and meet the requirements of ACPI. The W83697HF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, They are very important for a entertainment or consumer computer. The W83697HF provides Flash ROM interface. That can support up to 4M legacy flash ROM. The W83697HF support hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. Moreover, W83697HF support the Smart Fan control system, including the thermal CruiseTM” and speed CruiseTM” functions. Smart Fan can make system more stable and user friendly. -1- Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 2. FEATURES General • • • • • • • • Meet LPC Spec. 1.01 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) Include all the features of Winbond I/O W83877TF Integrate Hardware Monitor functions Compliant with Microsoft PC98/PC99 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input FDC • • • • • • • • • • • • • Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and under run conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98 driver UART • • • Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz • • • • -2- W83697HF/ HG • • • • Infrared Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Support Consumer IR with Wake-Up function. • • • • • • • Parallel Port Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port Enhanced printer port back-drive current protection • • • Game Port Support two separate Joysticks Support every Joystick two axes (X,Y) and two buttons (S1,S2) controllers • • • • MIDI Port The baud rate is 31.25 K baud rate 16-byte input FIFO 16-byte output FIFO • • Flash ROM Interface Support up to 4M flash ROM • • • • General Purpose I/O Ports 48 programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, watch dog timer output, power LED output, infrared I/O pins, suspend LED output, Beep output Functional in power down mode -3- Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Hardware Monitor Functions • • • • • • • • • • • • • • Smart fan control system, support thermal CruiseTM” and speed CruiseTM” 2 thermal inputs from optionally remote thermistors or 2N3904 transistors or PentiumTM II/III thermal diode output 6 positive voltage inputs (typical for +12V, -12V, +5V, -5V, +3.3V, Vcore) 2 intrinsic voltage monitoring (typical for Vbat, +5VSB) 2 fan speed monitoring inputs 2 fan speed control Build in Case open detection circuit WATCHDOG comparison of all monitored values Programmable hysteresis and setting points for all monitored items Over temperature indicate output Automatic Power On voltage detection Beep Issue SMI#, IRQ, OVT# to activate system protection Winbond Hardware DoctorTM Support Intel LDCMTM / Acer ADMTM compatible Package • 128-pin PQFP -4- W83697HF/ HG 3. BLOCK DIAGRAM FOR W83697HF LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ LPC Interface Joystick interface signals MSI MSO General-purpose I/O pins Hardware monitor channel and Vref Flash ROM interface signals Game Port MIDI FDC Floppy drive interface signals Serial port A, B interface signals IRRX IRTX URA, B GPIO IR HM CIR CIRRX# Printer port interface signals Flash ROM PRT ACPI -5- Publication Release Date: May 30, 2005 Revision A1 VTIN2 VTIN1 AVCC VREF VCORE +3.3VIN +12VIN -12VIN -5VIN AGND FANIO2 FANIO1 FANPWM2 FANPWM1 OVT#/S MI# BEEP MSI/GP51/WDTO# MSO/GP 50/PLED GPAS2/GP17 GPBS2/GP16 GPAY /GP15 GPBY /GP14 GPB X/GP13 GPA X/GP12 GPBS1/GP11 GPAS1/GP10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 4. PIN CONFIGURATION FOR W83697HF W83697HF -6- D RVDEN0 INDEX# MOA# DSB# VCC DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# D SKCHG# CLKIN GND PCICLK LDRQ# SERIRQ VCC3 LAD3 LAD2 LAD1 LAD0 LFRAME# LRESET# SLCT PE BUSY ACK# ERR# SLIN# PD7 PD6 PD5 PD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VBAT CASEOPEN# CIRRX VSB PME# ME MW#/GP52 ME MR#GP53 ROMCS#/GP54 XDO/GP2 0 XD1/GP21 XD2/GP22 XD3/GP23 GND XD4/GP24 XD5/GP25 XD6/GP26 XD7/GP27 XA0/G P30 XA1/G P31 XA2/G P32 XA3/G P33 XA4/G P34 XA5/G P35 XA6/G P36 XA7/G P37 XA8/G P40 XA9/G P41 VCC XA1 0/GP42 XA1 1/GP43 XA1 2/GP44 XA1 3/GP45 XA1 4/GP46 XA1 5/GP47 XA1 6/GP55 XA1 7/GP56 XA1 8/GP57 IRTX W83697HF/ HG IRRX I RRX RIB# DCDB# SOUTB/PEN48 GND SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA/PENROM# SINA DTRA#/PNPCSV# RTSA#/HEFRAS DSRA# CTSA# STB# VCC AFD# INIT# PD0 PD1 PD2 PD3 W83697HF/ HG 5. PIN DESCRIPTION Note: Please refer to Section 10.2 DC CHARACTERISTICS for details PIN DESCRIPTION I/O8t I/O12t I/O24t I/O12tp3 I/O12ts I/O24ts I/O24tsp3 I/OD12t I/OD24t I/OD24c I/OD24a I/OD12ts I/OD24ts I/OD12cs I/OD16cs I/OD24cs I/OD12csd I/OD12csu O4 O8 O12 O16 O24 O12p3 O24p3 OD8 OD12 OD24 OD12p3 INt INtp3 TTL level bi-directional pin with 8mA source-sink capability TTL level bi-directional pin with 12mA source-sink capability TTL level bi-directional pin with 24 mA source-sink capability 3.3V TTL level bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability TTL level bi-directional pin and open-drain output with 12mA sink capability TTL level bi-directional pin and open-drain output with 24mA sink capability CMOS level bi-directional pin and open-drain output with 24mA sink capability Bi-directional pin with analog input and open-drain output with 24mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 24mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 24mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open-drain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open-drain output with 12mA sink capability Output pin with 4 mA source-sink capability Output pin with 8 mA source-sink capability Output pin with 12 mA source-sink capability Output pin with 16 mA source-sink capability Output pin with 24 mA source-sink capability 3.3V output pin with 12 mA source-sink capability 3.3V output pin with 24 mA source-sink capability Open-drain output pin with 8 mA sink capability Open-drain output pin with 12 mA sink capability Open-drain output pin with 24 mA sink capability 3.3V open-drain output pin with 12 mA sink capability TTL level input pin 3.3V TTL level input pin -7- Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG PIN DESCRIPTION, Continued. PIN DESCRIPTION INtd INtu INts INtsp3 INc INcu INcd INcs INcsu TTL level input pin with internal pull down resistor TTL level input pin with internal pull up resistor TTL level Schmitt-trigger input pin 3.3V TTL level Schmitt-trigger input pin CMOS level input pin CMOS level input pin with internal pull up resistor CMOS level input pin with internal pull down resistor CMOS level Schmitt-trigger input pin CMOS level Schmitt-trigger input pin with internal pull up resistor 5.1 LPC Interface SYMBOL PIN I/O FUNCTION CLKIN PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# LRESET# 17 98 19 20 21 23-26 27 28 INtp3 OD12p3 INtsp3 O12p3 I/O12tp3 I/O12tp3 INtsp3 INtsp3 System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input. Generated PME event. PCI clock 33 MHz input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. -8- W83697HF/ HG 5.2 FDC Interface SYMBOL PIN I/O FUNCTION DRVDEN0 1 OD24 Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Publication Release Date: May 30, 2005 Revision A1 INDEX# 2 INcsu MOA# DSB# DSA# MOB# 3 4 6 7 OD24 OD24 OD24 OD24 OD24 OD24 OD24 OD24 INcsu DIR# 8 STEP# WD# WE# TRAK0# 9 10 11 12 WP# 13 INcsu RDATA# HEAD# 14 15 INcsu OD24 DSKCHG# 16 INcsu -9- W83697HF/ HG 5.3 Multi-Mode Parallel Port The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL PIN I/O FUNCTION SLCT 29 INts WE2# OD12 PRINTER MODE: An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WE2# This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE: WE2# This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC. PE 30 INts OD12 WD2# - 10 - W83697HF/ HG 5.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O FUNCTION INt BUSY 31 OD12 MOB2# INts ACK# 32 DSB2# OD12 ERR# INts 33 HEAD2# OD12 PRINTER MODE: An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: MOB2# This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2# This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. PRINTER MODE: ACK# An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSB2# This pin is for the Extension FDD B; its functions is the same as the DSB# pin of FDC. EXTENSION 2FDD MODE: DSB2# This pin is for Extension FDD A and B; its function is the same as the DSB# pin of FDC. PRINTER MODE: ERR# An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC. - 11 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 5.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O FUNCTION SLIN# 34 OD12 STEP2# OD12 INIT# 43 OD12 DIR2# OD12 AFD# 44 OD12 DRVDEN0 OD12 PRINTER MODE: SLIN# Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: STEP2# This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. PRINTER MODE: INIT# Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DIR2# This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE: DIR2# This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. PRINTER MODE: AFD# An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. - 12 - W83697HF/ HG 5.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O FUNCTION STB# 46 OD12 PD0 42 I/O12ts INDEX2# INts PD1 41 I/O12ts TRAK02# INts PD2 40 I/O12ts INts PRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: INDEX2# This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: INDEX2# This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: TRAK02# This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2# This pin is for Extension FDD B; its function is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. It is pulled high internally. - 13 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 5.3 Multi-Mode Parallel Port, continued SYMBOL PIN I/O FUNCTION PD3 39 I/O12ts RDATA2# INts PD4 38 I/O12ts DSKCHG2# INts PD5 37 I/O12ts PD6 36 I/O12ts - MOA2# OD12 PD7 35 I/O12ts DSA2# OD12 PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2# This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSKCHG2# This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2# This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC. - 14 - W83697HF/ HG 5.4 Serial Port Interface SYMBOL PIN I/O FUNCTION CTSA# CTSB# DSRA# DSRB# RTSA# HEFRAS 47 55 48 56 49 INt INt O8 Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 kΩ is recommended if intends to pull up. (select 4EH as configuration I/O port′s address) UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV#, which provides the power-on value for CR24 bit 0 (PNPCSV#). A 4.7 kΩ is recommended if intends to pull up. (clear the default value of FDC, UARTs, and PRT) UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power on reset , this pin is pulled down internally and is defined as PENROM#, which provides the power on value for CR24 bit 1. A 4.7kΩ is recommended if intends to pull up . UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 kΩ resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. INcd RTSB# DTRA# PNPCSV# 57 50 O8 O8 INcd DTRB# SINA SINB SOUTA PENROM# SOUTB PEN48 DCDA# DCDB# RIA# RIB# 58 51 59 52 O8 INt O8 INcd 61 O8 INcd 53 62 54 63 INt INt - 15 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 5.5 Infrared Port SYMBOL PIN I/O FUNCTION IRRX IRTX CIRRX# 64 65 100 INts O12 INt Alternate Function Input: Infrared Receiver input. General purpose I/O port 3 bit 6. Alternate Function Output: Infrared Transmitter Output. General purpose I/O port 3 bit 7. Consumer IR receiving input. This pin can Wake-Up system from S5cold. 5.6 Flash ROM Interface SYMBOL PIN I/O FUNCTION XA18-XA16 GP57-GP55 XA15-XA10 GP47-GP42 XA9-XA8 GP41-GP40 XA7-XA0 GP37-GP30 XD7-XD4 GP27-GP24 XD3-XD0 GP23-GP20 ROMCS# GP54 MEMR# GP53 MEMW# GP52 66-68 69-74 76-77 78-85 86-89 91-94 95 96 97 O12 I/OD12t O12 I/OD12t O12 I/OD12t O12 I/OD12t I/O12t I/OD12t I/O12t I/OD12t O12 I/OD12t O12 I/OD12t O12 I/OD12t Flash ROM interface Address[18:16] General purpose I/O port 5 bit7-5 Flash ROM interface Address[15:10] General purpose I/O port 4 bit7-2 Flash ROM interface Address[9:8] General purpose I/O port 4 bit1-0 Flash ROM interface Address[7:0] General purpose I/O port 3 bit7-0 Flash ROM interface Data Bus[7:4] General purpose I/O port 2 bit7-4 Flash ROM interface Data Bus [3:0] General purpose I/O port 2 bit3-0 Flash ROM interface Chip Select General purpose I/O port 5 bit4 Flash ROM interface Memory Read Enable General purpose I/O port 5 bit3 Flash ROM interface Memory Write Enable General purpose I/O port 5 bit2 - 16 - W83697HF/ HG 5.7 Hardware Monitor Interface SYMBOL CASEOPEN# PIN I/O FUNCTION 101 102 103 104 106 107 108 109 110 111 113114 INt Power AIN AIN AOUT AIN AIN AIN AIN AIN I/O12ts CASE OPEN. An active low signal from an external device when case is opened. Battery Voltage Input Temperature sensor 2 input. It is used for CPU temperature detect. Temperature sensor 1 input. It is used for system temperature detect. Reference Voltage Output. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to +5V amplitude fan tachometer input. Alternate Function: Fan on-off control output. These multifunctional pins can be programmable input or output. VBAT VTIN2 VTIN1 VREF VCORE +3.3VIN +12VIN -12VIN -5VIN FANIO[2:1] FANPWM[2:1] OVT# / SMI# BEEP 115116 117 O12 OD24 OD24 Fan speed control. Use the Pulse Width Modulation (PWM) knowledge to control the Fan's RPM. Over temperature Shutdown Output. It indicated the VTIN1 or VTIN2 is over temperature limit. System Management Interrupt. Beep function for hardware monitor. This pin is low after system reset. 118 OD8 - 17 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 5.8 Game Port & MIDI Port SYMBOL PIN I/O FUNCTION MSI GP51 WDTO# MSO GP50 PLED GPAS2 GP17 GPBS2 GP16 GPAY GP15 GPBY GP14 GPBX GP13 GPAX GP12 GPBS1 GP11 GPAS1 GP10 119 INt I/OD12t O12 120 O12 I/OD12t O12 121 INcsu I/OD12csu MIDI serial data input . General purpose I/O port 5 bit 1. Alternate Function : Watch dog timer output. MIDI serial data output. General purpose I/O port 5 bit 0. Alternate Function Output(Default) Power LED output, this signal is low after system reset. Active-low, Joystick I switch input 2. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 7. Active-low, Joystick II switch input 2. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 6. Joystick I timer pin. this pin connect to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 5. Joystick II timer pin. this pin connect to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 4. Joystick II timer pin. this pin connect to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 3. Joystick I timer pin. this pin connect to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 2. Active-low, Joystick II switch input 1. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 1. Active-low, Joystick I switch input 1. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 0. 122 INcsu I/OD12csu 123 I/OD12cs I/OD12cs 124 I/OD12cs I/OD12cs 125 I/OD12cs I/OD12cs 126 I/OD12cs I/OD12cs 127 INcsu I/OD12csu 128 INcsu I/OD12csu - 18 - W83697HF/ HG 5.9 POWER PINS SYMBOL PIN FUNCTION VCC VSB VCC3V AVCC AGND GND 5, 45, 75, 99 22 105 112 18, 60, 90, +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. +3.3V power supply for driving 3V on host interface. Analog VCC input. Internally supplier to all analog circuitry. Internally connected to all analog circuitry. The ground reference for all analog inputs.. Ground. - 19 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 6. HARDWARE MONITOR 6.1 General Description The W83697HF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83697HF provides LPC interface to access hardware . An 8-bit analog-to-digital converter (ADC) was built inside W83697HF. The W83697HF can simultaneously monitor 7 analog voltage inputs, 2 fan tachometer inputs, 2 remote temperature, one case-open detection signal. The remote temperature sensing can be performed by thermistors, or 2N3904 NPN-type transistors, or directly from IntelTM Deschutes CPU thermal diode output. Also the W83697HF provides: 2 PWM (pulse width modulation) outputs for the fan speed control; beep tone output for warning; SMI#(through serial IRQ) , OVT#, GPO# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or IntelTM LDCM (LanDesk Client Management), or other management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters is out of the preset range. 6.2 Access Interface The W83697HF provides two interface for microprocessor to read/write hardware monitor internal registers. 6.2.1 LPC interface The first interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports is set by W83697HF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. The register structure is showed as the Figure 9.1 - 20 - W83697HF/ HG Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h Fan Divisor Register 47h Device ID 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID/Device ID 49h Temperature 2, 3 Serial Bus Address 4Ah Control Register 4Bh~4Dh Select Bank for 50h~5Fh Reg. 4Eh Winbond Vendor ID 4Fh BANK 0 R-T Table Value BEEP Control Register Winbond Test Register 50h~58h BANK 1 Temperature 2 Control/Staus Registers 50h~56h BANK 2 Reserved 50h~56h B ANK 4 Additional Control/Staus Registers 50h~5Ch BANK 5 Additional Limit Value & Value RAM 50h~57h ISA Data Bus ISA Address Bus Port 5h Index Register Port 6h Data Register Figure 9.1 : ISA interface access diagram - 21 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 6.3 Analog Inputs The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage ,+3.3V ,battery and 5VSB voltage can directly connected to these analog inputs. The +12V,-12V and -5V voltage inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 9.2 shows. VCOREA VCOREB Positive Inputs +3.3VIN VBAT 5VSB R1 V1 Positive Input R2 +12VIN AVCC(+5V) Pin 100 Pin 99 Pin 98 Pin 97 Pin 74 Pin 61 Pin 96 8-bit ADC with 16mV LSB V2 Negative Input V3 R3 R5 N12VIN N5VIN Pin 95 Pin 94 R6 R 10K, 1% R4 VREF VTIN3 Pin 102 Pin 103 Pin 104 Pin 101 Typical Thermister Connectio R THM 10K, 25 C VTIN2 VTIN1 **The Connections of VTIN1 and VTI are same as VTIN3 Figure. 9.2 - 22 - W83697HF/ HG 6.3.1 Monitor over 4.096V voltage: The input voltage +12VIN can be expressed as following equation. 12VIN = V1 × R2 R1 + R2 The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximun input range of the 8-bit ADC. The Pin 97 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83697HF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The value of two serial resistors are 34K ohms and 50K ohms so that input voltage to ADC is 2.98V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as follows. Vin = VCC × 50 KΩ ≅ 2.98V 50 KΩ + 34 KΩ where VCC is set to 5V. The Pin 61 is connected to 5VSB voltage. W83697HF monitors this voltage and the internal two serial resistors are 17K Ω and 33K Ω so that input voltage to ADC is 3.3V which less than 4.096V of ADC maximum input voltage. 6.3.2 Monitor negative voltage: The negative voltage should be connected two series resistors and a positive voltage VREF (is equal to 3.6V). In the Figure 9.2, the voltage V2 and V3 are two negative voltage which they are -12V and 5V respectively. The voltage V2 is connected to two serial resistors then is connected to another terminal VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a posedge voltage if the scales of the two serial resirtors are carefully selected. It is recommanded from Winbond that the scale of two serial resistors are R3=232K ohms and R4=56K ohm. The input voltage of node N12VIN can be calculated by following equation. N 12VIN = (VREF + V2 ) × ( 232 KΩ ) + V2 232 KΩ + 56 KΩ where VREF is equal 3.6V. If the V2 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative votage and the express equation is shown as follows. V2 = N 12VIN − VREF × β 1− β Where β is 232K/(232K+56K). If the N2VIN is 0.567 then the V2 is approximately equal to -12V. - 23 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG The another negative voltage input V3 (approximate -5V) also can be evaluated by the similar method and the serial resistors can be selected with R5=120K ohms and R6=56K ohms by the Winbond recommended. The expression equation of V3 With -5V voltage is shown as follows. V3 = N 5VIN − VREF × γ 1− γ Where the γ is set to 120K/(120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635, VREF=3.6V and the parameter γ is 0.6818 then the negative voltage of V3 can be evalated to be -5V. 6.3.3 Temperature Measurement Machine The temperature data format is 8-bit two's-complement for sensor 2 and 9-bit two's-complement for sensor 1. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1 CR[50h] and the LSB from the Bank1 CR[51h] bit 7. The format of the temperature data is show in Table 1. 8-BIT DIGITAL OUTPUT 8-BIT BINARY 8-BIT HEX 9-BIT DIGITAL OUTPUT 9-BIT BINARY 9-BIT HEX TEMPERATURE +125°C +25°C +1°C +0.5°C +0°C -0.5°C -1°C -25°C -55°C 0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001 7Dh 19h 01h 00h FFh E7h C9h Table 2. 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h 6.3.3.1. Monitor temperature from thermistor: The W83697HF can connect three thermistors to measure three different envirment temperature. The specification of thermistor should be considered to (1) β value is 3435K, (2) resistor value is 10K ohms at 25°C. In the Figure 9.2, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF (Pin 101). 6.3.3.2. Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 The W83697HF can alternate the thermistor to Pentium IITM (Deschutes) thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 9.3. The pin of Pentium IITM D- is connected to power supply ground (GND) and the pin D+ is connected to pin VTINx in the W83697HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied togeter to act as a thermal diode. - 24 - W83697HF/ HG VREF R=30K, 1% Bipolar Transistor Temperature Sensor VTINx C=3300pF C B E R=30K, 1% 2N3904 W83627HF OR Pentium II CPU Therminal Diode D+ C=3300pF D- VTINx Figure 9.3 6.4 FAN Speed Count and FAN Speed Control 6.4.1 Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 9.4. Determine the fan counter according to: Count = 1.35 × 10 6 RPM × Divisor In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation. 1.35 × 10 6 RPM = Count × Divisor The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, PRM, and count. - 25 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG NOMINAL PRM TIME PER REVOLUTION TIME FOR 70% DIVISOR COUNTS 70% RPM 1 2 (default) 4 8 16 32 64 128 8800 4400 2200 1100 550 275 137 68 6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms Table 1. 153 153 153 153 153 153 153 153 6160 3080 1540 770 385 192 96 48 9.74 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms +12V +5V +12V Pull-up resister diode +12V FAN Out GND Fan Input Pin 111-113 4.7K Ohms diode +12V Pull-up resister 4.7K Ohms 14K~39K FAN Out GND Fan Input Pin 111-113 FAN Connector W83627HF FAN Connector 10K W83627HF Fan with Tach Pull-Up to +5V Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator +12V +12V diode +12V FAN Out GND Pull-up resister > 1K +12V Pin 111-113 FAN Out diode Pull-up resister < 1K or totem-pole output Fan Input Pin 111-113 > 1K Fan Input 3.9V Zener GND FAN Connector W83627HF 3.9V Zener FAN Connector W83627HF Fan with Tach Pull-Up to +12V and Zener Clamp Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Zener Clamp Figure 9.4 - 26 - W83697HF/ HG 6.4.2 Fan speed control The W83697HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty − cycle(%) = Programmed 8 - bit Register Value × 100% 255 The PWM clock frequency also can be program and defined in the Bank0.CR5C . The application circuit is shown as follows. +12V R1 R2 D G PWM Clock Input S NMOS + C FAN PNP Transistor Figure 9.5 - 27 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 6.5 SMI# interrupt mode 6.5.1 Voltage SMI# mode : SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 9.6 ) 6.5.2 Fan SMI# mode : SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 9.7 ) High limit Low limit Fan Count limit SMI# * * * * SMI# * * *Interrupt Reset when Interrupt Status Registers are read Figure 9.6 Figure 9.7 - 28 - W83697HF/ HG 6.5.3 The W83697HF temperature sensor 1 SMI# interrupt has two modes: (1) Comparator Interrupt Mode Setting the THYST (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. (Figure 9.8 ) (2) Two-Times Interrupt Mode Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Two-Times Interrupt Mode. Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 9.9 ) THYST 127'C TOI TOI THYST SMI# * * * * SMI# * * * *Interrupt Reset when Interrupt Status Registers are read Figure 9.8 Figure 9.9 - 29 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 6.5.4 The W83697HF temperature sensor 2 programmed at CR[4Ch] bit 6. SMI# interrupt has two modes and it is (1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. ( Figure 9.10 ) (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 9.11 ) TOI TOI THYST THYST SMI# * * * * * SMI# * * * *Interrupt Reset when Interrupt Status Registers are read Figure 9.10 Figure 9.11 - 30 - W83697HF/ HG 6.6 OVT# interrupt mode The OVT# signal is only related with temperature sensor 2 (VTIN2 ). 6.6.1 The W83697HF temperature sensor 2 Over-Temperature (OVT#) has the following modes (1) Comparator Mode : Setting Bank1/2 CR[52h] bit 2 to 0 will set OVT# signal to comparator mode. Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. ( Figure 9.12) (2) Interrupt Mode: Setting Bank1/2 CR[52h] bit 2 to 1 will set OVT# signal to interrupt mode. Setting Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding TO , then reset, if the temperature remains above THYST , the OVT# will not be activated again.( Figure 9.12) To THYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) * * * * *Interrupt Reset when Temperature 2/3 is read - 31 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 6.7 REGISTERS AND RAM Address Register (Port x5h) Data Port: Power on Default Value Attribute: Size: Port x5h 00h Bit 6:0 Read/write , Bit 7: Read Only 8 bits 7 6 5 4 3 2 1 0 Data Bit7: Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC bus transaction. With checking this bit, multiple LPC drivers can use W83697HF hardware monitor without interfering with each other or a Serial Bus driver. It is the user's responsibility not to have a Serial Bus and LPC bus operations at the same time. This bit is: Set: with a write to Port x5h or when a Serial Bus transaction is in progress. Reset: with a write or read from Port x6h if it is set by a write to Port x5h. Bit 6-0: Read/Write Bit 7 Busy (Power On default 0) A6 A5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Pointer (Power On default 00h) A4 A3 A2 A1 A0 - 32 - W83697HF/ HG Address Pointer Index (A6-A0) REGISTERS AND RAM A6-A0 IN HEX POWER ON VALUE OF REGISTERS: IN BINARY NOTES Configuration Register Interrupt Status Register 1 Interrupt Status Register 2 SMI#Ý Mask Register 1 SMIÝ Mask Register 2 NMI Mask Register 1 NMI Mask Register 2 Fan Divisor Register Reserved Device ID Register Reserved Reserved SMI#/OVT# Property Select Register FAN IN/OUT and BEEP Control Register Register 50h-5Fh Bank Select Register 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 00001000 00000000 00000000 00000000 00000000 00000000 01000000 = 0101; = 0000001 AUTO-INCREMENT TO THE ADDRESS OF NMI MASK REGISTER 2 AFTER A READ OR WRITE TO PORT X6H Auto-increment to the address of SMIÝ Mask Register 2 after a read or write to Port x6h. Auto-increment to the address of Interrupt Status Register 2 after a read or write to Port x6h. = 00000000 = 00010101 = 1 ; = Reserved ; = 000 = 01011100 (High Byte) = 10100011 (Low Byte) Winbond Vendor ID Register 4Fh - 33 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Address Pointer Index (A6-A0), continued REGISTERS AND RAM A6-A0 IN HEX POWER ON VALUE OF REGISTERS: IN BINARY NOTES POST RAM Value RAM Value RAM Temperature 2 Registers Reserved Additional Configuration Registers 00-1Fh 20-3Fh 60-7Fh Bank1 50h-56h Bank2 50h-56h Bank4 50h5Dh Auto-increment to the next location after a read or write to Port x6h and stop at 1Fh. Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh. - 34 - W83697HF/ HG Data Register (Port x6h) Data Port: Power on Default Value Attribute: Size: Port x6h 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0: Data to be read from or to be written to RAM and Register. Configuration Register  Index 40h Register Location: Power on Default Value Attribute: Size: 8 bits 7 6 5 40h 01h Read/write 4 3 2 1 0 START SMI#Enable RESERVED INT_Clear RESERVED RESERVED RESERVED INITIALIZATION Bit 7: A one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. Bit 6: Reserced Bit 5: Reserved Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. - 35 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Interrupt Status Register 1 Index 41h Register Location: Power on Default Value Attribute: Size: 7 41h 00h Read Only 8 bits 6 5 4 3 2 1 0 VCORE Reserved +3.3VIN AVCC TEMP1 TEMP2 FAN1 FAN2 Bit 7: A one indicates the fan count limit of FAN2 has been exceeded. Bit 6: A one indicates the fan count limit of FAN1 has been exceeded. Bit 5: A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2. Bit 4: A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1. Bit 3: A one indicates a High or Low limit of +5VIN has been exceeded. Bit 2: A one indicates a High or Low limit of +3.3VIN has been exceeded. Bit 1: Reserved Bit 0: A one indicates a High or Low limit of VCORE has been exceeded. Interrupt Status Register 2  Index 42h Register Location: Power on Default Value Attribute: Size: 7 6 42h 00h Read Only 8 bits 5 4 3 2 1 0 +12VIN -12VIN -5VIN Reserved CaseOpen Reserved Reserved Reserved - 36 - W83697HF/ HG Bit 7-6:Reserved.This bit should be set to 0. Bit 5: Reserved. Bit 4: A one indicates case has been opened. Bit 3: Reserved. Bit 2: A one indicates a High or Low limit of -5VIN has been exceeded. Bit1: A one indicates a High or Low limit of -12VIN has been exceeded. Bit0: A one indicates a High or Low limit of +12VIN has been exceeded. SMI# Mask Register 1  Index 43h Register Location: Power on Default Value Attribute: Size: 7 43h 00h Read/Write 8 bits 6 5 4 3 2 1 0 VCORE Reserved +3.3VIN AVCC TEMP1 TEMP2 FAN1 FAN2 Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. SMI# Mask Register 2  Index 44h Register Location: Power on Default Value Attribute: Size: 7 6 44h 00h Read/Write 8 bits 5 4 3 2 1 0 +12VIN -12VIN -5VIN Reserved CaseOpen Reserved Reserved Reserved Bit 7-6: Reserved. This bit should be set to 0. Bit 5-0: A one disables the corresponding interrupt status bit for SMI interrupt. - 37 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Reserved Register  Index 45h Chassis Clear Register -- Index 46h Register Location: Power on Default Value Attribute: Size: 7 6 46h 00h Read/Write 8 bits 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear Bit 7: Set 1 , clear case open event. This bit self clears after clearing case open event. Bit 6-0:Reserved. This bit should be set to 0. Fan Divisor Register  Index 47h Register Location: 47h Power on Default Value 5fh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1 Bit 7-6: FAN2 Speed Control. Bit 5-4: FAN1 Speed Control. Bit 3-0: Reserved Note : Please refer to Bank0 CR[5Dh] , Fan divisor table. - 38 - W83697HF/ HG Value RAM  Index 20h- 3Fh or 60h - 7Fh (auto-increment) ADDRESS A6A0 ADDRESS A6-A0 WITH AUTO-INCREMENT DESCRIPTION 20h 21h 22h 23h 24h 25h 26h 27h 28h 60h 61h 62h 63h 64h 65h 66h 67h 68h VCORE reading Reserved +3.3VIN reading AVCC(+5V) reading +12VIN reading -12VIN reading -5VIN reading Temperature sensor 1 reading FAN1 reading Note: This location stores the number of counts of the internal clock per revolution. FAN2 reading Note: This location stores the number of counts of the internal clock per revolution. VCORE High Limit VCORE Low Limit Reserved Reserved +3.3VIN High Limit +3.3VIN Low Limit AVCC(+5V) High Limit AVCC(+5V) Low Limit +12VIN High Limit +12VIN Low Limit -12VIN High Limit 29h 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 69h 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h - 39 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Value RAM  Index 20h- 3Fh or 60h - 7Fh (auto-increment), continued ADDRESS A6A0 ADDRESS A6-A0 WITH AUTO-INCREMENT DESCRIPTION 36h 37h 38h 39h 3Ah 3Bh 76h 77h 78h 79h 7Ah 7Bh -12VIN Low Limit -5VIN High Limit -5VIN Low Limit Temperature sensor 1 (VTIN1) High Limit Temperature sensor 1 (VTIN1) Hysteresis Limit FAN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN2 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. Reserved. Reserved 3Ch 3Dh 3E- 3Fh 7Ch 7Dh 7E- 7Fh Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. Device ID Register - Index 49h Register Location: Power on Default Value Size: 7 49h is 000,0001 binary 8 bits 6 5 4 3 2 1 0 Reserved DID Bit 7-1: Read Only - Device ID Bit 0 : Reserved Reserved - Index 4Bh - 40 - W83697HF/ HG SMI#/OVT# Property Select Register- Index 4Ch Register Location: Power on Default Value Attribute: Size: 7 6 4Ch 00h Read/Write 8 bits 5 4 3 2 1 0 Reserved Reserved OVTPOL DIS_OVT Reserved Reserved T2_INTMode Reserved Bit 7: Reserved. User Defined. Bit6: Set to 1, the SMI# output type of Temperature 2(VTIN2) is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0) Bit5: Reserved. User Defined. Bit 4: Reserved Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable OVT# (Temp 2) output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. Bit 0: OVT# mode select. Set 1 to ACPI Mode, Set 0 to Comparator or Interrupt mode. Default 0. FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location: Power on Default Value Attribute: Size: 4Dh 15h Read/Write 8 bits - 41 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 7 6 5 4 3 2 1 0 FANINC1 FANOPV1 FANINC2 FANOPV2 Reserved Reserved Reserved Reserved Bit 7~4: Reserved. Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 113 always generate logic high signal. Write 0, pin 113 always generates logic low signal. This bit default 0. Bit 2: FAN 2 Input Control. Set to 1, pin 113 acts as FAN clock input, which is default value. Set to 0, this pin 113 acts as FAN control signal and the output value of FAN control is set by this register bit 3. Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 114 always generate logic high signal. Write 0, pin 114 always generates logic low signal. This bit default 0. Bit 0: FAN 1 Input Control. Set to 1, pin 114 acts as FAN clock input, which is default value. Set to 0, this pin 114 acts as FAN control signal and the output value of FAN control is set by this register bit 1. Register 50h ~ 5Fh Bank Select Register - Index 4Eh Register Location: Power on Default Value Attribute: Size: 7 6 4Eh 80h Read/Write 8 bits 5 4 3 2 1 0 BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select. - 42 - W83697HF/ HG Winbond Vendor ID Register - Index 4Fh (No Auto Increase) Register Location: Power on Default Value Attribute: Size: 15 4Fh = 5CA3h Read Only 16 bits 8 7 0 VIDH VIDL Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h. Winbond Test Register -- Index 50h - 55h (Bank 0) BEEP Control Register 1-- Index 56h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 56h 00h Read/Write 8 bits 5 4 3 2 1 0 EN_VC_BP Reserved EN_V33_BP EN_AVCC_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 - 43 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 3: Enable BEEP output from AVCC (+5V), Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 2: Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value. Bit 1: Reserved Bit 0: Enable BEEP Output from VCORE if the monitor value exceed the limits value. Write 1, enable BEEP output, which is default value BEEP Control Register 2-- Index 57h (Bank 0) Register Location: Attribute: Size: 57h Read/Write 8 bits 7 6 5 4 3 2 1 0 Power on Default Value 80h EN_V12_BP EN_NV12_BP EN_NV5_BP Reserved EN_CASO_BP Reserved Reserved EN_GBP Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6: Reserved. This bit should be set to 0. Bit5: Reserved Bit 4: Enable BEEP output for case open if case opend. Write 1, enable BEEP output. Default 0. Bit 3: Reserved Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. - 44 - W83697HF/ HG Chip ID -- Index 58h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 58h 60h Read Only 8 bits 5 4 3 2 1 0 CHIPID Bit 7: Winbond Chip ID number. Read this register will return 60h. Register -- Index 59h (Bank 0) Register Location: 59h Power on Default Value =0 and = 111 and = 0000 Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 Reserved Reserved Bit 7-6: Reserved Bit 5: Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode. Bit 4: Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904 Bipolar mode. Bit 3-0: Reserved - 45 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Reserved -- Index 5Ah (Bank 0) Reserved -- Index 5Bh (Bank 0) Reserved -- Index 5Ch (Bank 0) ACPI Temperature Increment Register -- Index 5Fh (Bank 0) Register Location: 5Fh Power on Default Value = 0x00 Attribute: Read/Write Size: 7 bits Bit 7 6-0 Name Reserved DIFFREG[6:0] Attribute Reserved Read/Write Description Reserved ACPI Temperature Increment Register. If set to this register to non-zero value, the OVT# signal will be activated at pointer of the temperature of times of DIFFREG. VBAT Monitor Control Register -- Index 5Dh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 6 5Dh 00h Read/Write 8 bits 5 4 3 2 1 0 EN_VBAT_MNT DIODES1 DIODES2 Reserved Reserved FANDIV1_B2 FANDIV2_B2 Reserved Bit 7: Reserved. Bit 6: Fan2 divisor Bit 2. Bit 5: Fan1 divisor Bit 2. Bit 4 –3 : Reserved. Bit 2: Sensor 2 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 1: Sensor 1 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300ms for W83697HF hardware monitor. - 46 - W83697HF/ HG Fan divisor table : BIT 2 BIT 1 BIT 0 FAN DIVISOR BIT 2 BIT 1 BIT 0 FAN DIVISOR 0 0 0 0 0 0 1 1 0 1 0 1 1 2 4 8 1 1 1 1 0 0 1 1 0 1 0 1 16 32 64 128 Reserved Register -- 5Eh (Bank 0) Reserved Register -- 5Fh (Bank 0) Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1) Register Location: Attribute: Size: 50h Read Only 8 bits 7 6 5 4 3 2 1 0 TEMP2 Bit 7: Temperature of sensor 2, which is high byte, means 1°C. Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: Attribute: Size: 51h Read Only 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP2 Bit 7: Temperature of sensor2, which is low byte, means 0.5°C. Bit 6-0: Reserved. Publication Release Date: May 30, 2005 Revision A1 - 47 - W83697HF/ HG Temperature Sensor 2 Configuration Register - Index 52h (Bank 1) Register Location: Power on Default Value Size: 7 6 52h 00h 8 bits 5 4 3 2 1 0 STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Read - Reserved. This bit should be set to 0. 　 Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 6 53h 4Bh Read/Write 8 bits 5 4 3 2 1 0 THYST2 Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. - 48 - W83697HF/ HG Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 54h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved THYST2 Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 6 55h 50h Read/Write 8 bits 5 4 3 2 1 0 TOVF2 Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. - 49 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 56h 00h Read/Write 8 bits 6 5 4 3 2 1 0 Reserved TOVF2 Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. Interrupt Status Register 3 -- Index 50h (BANK4) Register Location: Power on Default Value Attribute: Size: 7 50h 00h Read Only 8 bits 6 5 4 3 2 1 0 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2: Reserved. Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded. - 50 - W83697HF/ HG SMI# Mask Register 3 -- Index 51h (BANK 4) Register Location: Power on Default Value Attribute: Size: 7 51h 00h Read/Write 8 bits 6 5 4 3 2 1 0 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. Reserved Register -- Index 52h (Bank 4) BEEP Control Register 3-- Index 53h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 53h 00h Read/Write 8 bits 6 5 4 3 2 1 0 EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Bit 4-2: Reserved. Bit 1: Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value. Bit 0: Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value. - 51 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Temperature Sensor 1 Offset Register -- Index 54h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 6 54h 00h Read/Write 8 bits 5 4 3 2 1 0 OFFSET1 Bit 7-0: Temperature 1 base temperature. The temperature is added by both monitor value and offset value. Temperature Sensor 2 Offset Register -- Index 55h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 6 55h 00h Read/Write 8 bits 5 4 3 2 1 0 OFFSET2 Bit 7-0: Temperature 2 base temperature. The temperature is added by both monitor value and offset value. Reserved Register -- Index 57h--58h - 52 - W83697HF/ HG Real Time Hardware Status Register I -- Index 59h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 6 59h 00h Read Only 8 bits 5 4 3 2 1 0 VCORE_STS Reserved +3.3VIN_STS AVCC_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6: FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 5: Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4: Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 3: AVCC Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is in the limit range. Bit 2: +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of +3.3V is in the limit range. Bit 1: Reserved Bit 0: VCORE Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the voltage of VCORE A is in the limit range. Real Time Hardware Status Register II -- Index 5Ah (Bank 4) Register Location: Power on Default Value Attribute: Size: 5Ah 00h Read Only 8 bits - 53 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 7 6 5 4 3 2 1 0 +12VIN_STS -12VIN_STS -5VIN_STS Reserved CASE_STS Reserved Reserved Reserved Bit 7-6: Reserved Bit 5: Reserved Bit 4: Case Open Status. Set 1, the case open sensor is sensed the high value. Set 0 Bit 3: Reserved Bit 2: -5V Voltage Status. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is during the limit range. Bit 1: -12V Voltage Status. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of - 12V is during the limit range. Bit 0: +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range. Real Time Hardware Status Register III -- Index 5Bh (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 5Bh 00h Read Only 8 bits 6 5 4 3 2 1 0 5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved Bit 7-2: Reserved. Bit 1: VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of 5VSB is in the limit range. - 54 - W83697HF/ HG Reserved Register -- Index 5Ch (Bank 4) Reserved Register -- Index 5Dh (Bank 4) Value RAM 2 Index 50h - 5Ah (auto-increment) (BANK 5) ADDRESS A6-A0 AUTO-INCREMENT DESCRIPTION 50h 51h 52h 53h 54h 55h 56h 57h 5VSB reading VBAT reading Reserved Reserved 5VSB High Limit 5VSB Low Limit. VBAT High Limit VBAT Low Limit Winbond Test Register -- Index 50h (Bank 6) FAN 1 Pre-Scale Register--Index00h(Bank 0) Power on default [7:0] = 0000-0001 b BIT NAME READ/WRIT E DESCRIPTION 7 PWM_CLK_SEL1 Read/Write PWM Input Clock Select. This bit select Fan 1 input clock to pre-scale divider. 0: 24 MHz 1: 180 KHz 6-0 PRE_SCALE1[6:0] Read/Write Fan 1 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 1 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 01h : divider is 1 02h : divider is 2 03h : divider is 3 : : PWM frequency = (Input Clock / Pre-scale) / 256 - 55 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG FAN 1 Duty Cycle Select Register-- 01h (Bank 0) Power on default [7:0] 1111,1111 b BIT NAME READ/WRITE DESCRIPTION 7-0 F1_DC[7:0] Read/Write FanPWM1 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 1 control mode, read this register will return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle. FAN 2 Pre-Scale Register-- Index 02h Power on default [7:0] = 0000,0001 b BIT NAME READ/WRIT E DESCRIPTION 7 PWM_CLK_SEL2 Read/Write PWM 2 Input Clock Select. This bit select Fan 2 input clock to pre-scale divider. 0: 1 MHz 1: 125 KHz Fan 2 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 6-0 PRE_SCALE2[6:0] Read/Write 01h : divider is 1 02h : divider is 2 03h : divider is 3 : : PWM frequency = (Input Clock / Pre-scale) / 256 - 56 - W83697HF/ HG FAN2 Duty Cycle Select Register-- Index 03h Power on default [7:0] = 1111,1111 b BIT NAME READ/WRITE DESCRIPTION 7-0 F2_DC[7:0] Read/Write FanPWM2 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 2 control mode, read this register will return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is XX/256*100% during one cycle. FAN Configuration Register-- Index 04h Power on default [7:0] = 0000,0000 b BIT NAME READ/WRITE DESCRIPTION 7-2 5-4 Reserved FAN2_MODE Read/Write Read/Write Reserved FAN 2 PWM Control Mode. 00 - Manual PWM Control Mode. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved. 3-2 FAN1_MODE Read/Write FAN 1 PWM Control Mode. 00 - Manual PWM Control Mode. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved. 1 FAN2_OB Read/Write Enable Fan 2 as Output Buffer. Set to 0, FANPWM2 can drive logical high or logical low. Set to 1, FANPWM2 is open-drain Enable Fan 1 as Output Buffer. Set to 1, FANPWM1 can drive logical high or logical low. Set to 1, FANPWM1 is open-drain 0 FAN1_OB Read/Write - 57 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG VTIN1 Target Temperature Register/ Fan 1 Target Speed Register -- Index 05h Power on default [7:0] = 0000,0000 b CPUT1 target temperature register for Thermal Cruise mode. BIT NAME READ/WRITE DESCRIPTION 7 6-0 Reserved TEMP_TAR_T1[6:0] Read/Write Read/Write Reserved. VTIN1 Target Temperature. Only for Thermal Cruise Mode while CR84h bit3-2 is 01. Fan 1 target speed register for Fan Speed Cruise mode. BIT NAME READ/WRITE DESCRIPTION 7-0 SPD_TAR_FAN1[7 :0] Read/Write Fan 1 Target Speed Control. Only for Fan Speed Cruise Mode while CR84h bit3-2 is 10. VTIN2 Target Temperature Register/ Fan 2 Target Speed Register -- Index 06h Power on - [7:0] = 0000,0000 b CPUT2 target temperature register for Thermal Cruise mode. BIT NAME READ/WRITE DESCRIPTION 7 6-0 Reserved TEMP_TAR_T2[6: 0] Read/Write Read/Write Reserved. VTIN2 Target Temperature. Only for Thermal Cruise Mode while CR84h bit5-4 is 01. Fan 2 target speed register for Fan Speed Cruise mode. BIT NAME READ/WRITE DESCRIPTION 7-0 SPD_TAR_FAN2[7 :0] Read/Write Fan 2 Target Speed Control. Only for Fan Speed Cruise Mode while CR84h bit5-4 is 10. - 58 - W83697HF/ HG Tolerance of Target Temperature or Target Speed Register -- Index 07h Power on default [7:0] = 0001,0001 b Tolerance of CPUT1/CPUT2 target temperature register. BIT NAME READ/WRITE DESCRIPTION 7-4 3-0 TOL_T2[3:0] TOL_T1[3:0] Read/Write Read/Write Tolerance of VTIN2 Target Temperature. Only for Thermal Cruise mode. Tolerance of VTIN1 Target Temperature. Only for Thermal Cruise mode. Tolerance of Fan 1/2 target speed register. BIT NAME READ/WRITE DESCRIPTION 7-4 3-0 TOL_FS2[3:0] TOL_FS1[3:0] Read/Write Read/Write Tolerance of Fan 2 Target Speed Count. Only for Fan Speed Cruise mode. Tolerance of Fan 1 Target Speed Count. Only for Fan Speed Cruise mode. Fan 1 PWM Stop Duty Cycle Register -- Index 08h Power on default [7:0] = 0000,0001 b BIT NAME READ/WRITE DESCRIPTION 7-0 STOP_DC1[7:0] Read/Write In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this value. This register should be written a non-zero minimum PWM stop duty cycle. Fan 2 PWM Stop Duty Cycle Register -- 09h (Bank 0) Power on default [7:0] = 0000,0001 b BIT NAME READ/WRIT E DESCRIPTION 7-0 STOP_DC2[7:0] Read/Write In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this register value. This register should be written a non-zero minimum PWM stop duty cycle. - 59 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Fan 1 Start-up Duty Cycle Register -- Index 0Ah Power on default [7:0] = 0000,0001 b BIT NAME READ/WRITE DESCRIPTION 7-0 START_DC1[7:0] Read/Write In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle. Fan 2 Start-up Duty Cycle Register -- Index 0Bh Power on default [7:0] = 0000,0001 b BIT NAME READ/WRITE DESCRIPTION 7-0 START_DC2[7:0] Read/Write In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle. Fan 1 Stop Time Register -- Index 0Ch Power on default [7:0] = 0011,1100 b BIT NAME READ/WRITE DESCRIPTION 7-0 STOP_TIME1[7:0] Read/Write In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds. Fan 2 Stop Time Register -- Index 0Dh Power on default [7:0] = 0011,1100 b BIT NAME READ/WRITE DESCRIPTION 7-0 STOP_TIME2[7:0] Read/Write In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds. - 60 - W83697HF/ HG Fan Step Down Time Register -- Index 0Eh Power on defualt [7:0] = 0000,1010 b BIT NAME READ/WRITE DESCRIPTION 7-0 STEP_UP_T[7:0] Read/Write The time interval, which is 0.1 second unit, to decrease PWM duty in Smart Fan Control mode. Fan Step Up Time Register -- Index 0Fh Power on default [7:0] = 0000,1010 b BIT NAME READ/WRITE DESCRIPTION 7-0 STEP_DOWN_T[7:0] Read/Write The time interval, which is 0.1 second unit, to increase PWM duty in Smart Fan Control mode. - 61 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 7. CONFIGURATION REGISTER 7.1 Plug and Play Configuration The W83697HF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83697HF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), CIR (Consumer IR, logical device 6), GPIO1 (logical device 7), GPIO5(logical device 8),GPIO2 ~GPIO4(logical device 9), ACPI ((logical device A), and Hardware monitor (logical device B). Each Logical Device has its own configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7. 7.2 Compatible PnP 7.2.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS ADDRESS AND VALUE 0 1 write 87h to the location 2Eh twice write 87h to the location 4Eh twice After Power-on reset, the value on RTSA# (pin 49) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh). After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration - 62 - W83697HF/ HG registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 7.2.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83697HF enters the default operating mode. Before the W83697HF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section). 7.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh on PC/AT systems. 7.3 Configuration Sequence To program W83697HF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode 7.3.1 Enter the extended function mode To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh). 7.3.2 Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR. 7.3.3 Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. Publication Release Date: May 30, 2005 Revision A1 - 63 - W83697HF/ HG 7.3.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write | ;----------------------------------------------------------------------------------MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX,2EH MOV AL,AAH OUT DX,AL - 64 - W83697HF/ HG 7.4 Chip (Global) Control Register CR02 (Default 0x00, Write Only) Bit 7 - 1: Reserved. Bit 0: SWRST --> Soft Reset. CR07 Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x 60 (read only). CR21 Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev = 0x1X (read only). X : Version change number (Bit 3~0). CR22 (Default 0xff) Bit 7~ 5: Reserved. Bit 4: HMPWD = 0 Power down = 1 No Power down Bit 3: URBPWD = 0 Power down = 1 No Power down Bit 2: URAPWD = 0 Power down = 1 No Power down Bit 1: PRTPWD = 0 Power down = 1 No Power down Bit 0: FDCPWD = 0 Power down = 1 No Power down - 65 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG CR23 (Default 0x00) Bit 7 ~ 1: Reserved. Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. CR24 (Default 0x00) Bit 7 : Reserved. Bit 6: CLKSEL(Enable 48Mhz) = 0 The clock input on Pin 1 should be 24 Mhz. = 1 The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 61). Bit[5:4]: ROM size select =00 1M =01 2M =10 4M =11 Reserved Bit3:MEMW# Select (PIN97) = 0 MEMW# Disable = 1 MEMW# Enable Bit2:Reserved Bit1 : Enable Flash ROM Interface = 0 Flash ROM Interface is enabled after hardware reset = 1 Flash ROM Interface is disabled after hardware reset This bit is read only, and set/reset by power-on setting pin. The corresponding power-on setting pin is PENROM#(pin 52) Bit 0: PNPCSV# = 0 The Compatible PnP address select registers have default values. = 1 The Compatible PnP address select registers have no default value. The corresponding power-on setting pin is DTRA# (pin 50). CR25 (Default 0x00) Bit 7 ~ 4: Reserved Bit 3: URBTRI Bit 2: URATRI Bit 1: PRTTRI Bit 0: FDCTRI. - 66 - W83697HF/ HG CR26 (Default 0x00) Bit 7: SEL4FDD =0 =1 Select two FDD mode. Select four FDD mode. Bit 6: HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is RTSA #(pin 49). HEFRAS Address and Value = 0 Write 87h to the location 2E twice. = 1 Write 87h to the location 4E twice. Bit 5: LOCKREG = 0 Enable R/W Configuration Registers. = 1 Disable R/W Configuration Registers. Bit4: Reserved Bit 3: DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ Bit 2: DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ = 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ Bit 1: DSUALGRQ = 0Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0: DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ - 67 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG CR28 (Default 0x00) Bit 7 - 3: Reserved. Bit 2 - 0: PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR29 (GPIO1,5(50~51) & Game port & MIDI port Select default 0x00 ) Bit 7 : Port Select (select Game Port or General Purpose I/O Port 1) = 0 Game Port = 1 General Purpose I/O Port 1 (pin121~128 select function GP10~GP17) Bit [6:5] : (Pin119) 00 MSI 01 WDTO# 10 Reserved 11 GP51 Bit[4:3] : (Pin 120) 00 MSO 01 PLED 10 Reserved 11 GP50 Bit 2 :(Pin117) OVT# & SMI Select(Pin117) = 0 OVT# = 1 SMI# Bit 1~0 : Reserved - 68 - W83697HF/ HG CR2A(GPIO2 ~ 5& Flash ROM Interface Select Default 0xFF if PENROM# = 0 during POR, default 0x00 otherwise) Bit 7 : (PIN 86 ~89 & 91 ~94) = 0 GPIO 2 = 1 Flash IF (xD7 ~ XD0) Bit 6 : (PIN 78 ~ 85) = 0 GPIO 3 = 1 Flash IF (XA7 ~ XA0) Bit 5 : (PIN 69 ~ 74 & 76 ~77) = 0 GPIO 4 = 1 Flash IF (XA!5 ~ XA10 & XA7 ~ A0) Bit 4: (PIN 66 ~ 68 & 95 ~ 97) = 0 GPIO 5(GP52 ~ 57) = 1 Flash IF(XA18 ~ XA16 , ROMCS#, MEMR #, MEMW#) Bit 0~3 : Reserved - 69 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 7.5 Logical Device 0 (FDC) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit 7 - 3: Reserved. Bit 2 - 0: These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7: FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. =0 =1 The internal pull-up resistors of FDC are turned on.(Default) The internal pull-up resistors of FDC are turned off. Bit 6: INTVERTZ This bit determines the polarity of all FDD interface signals. =0 =1 FDD interface signals are active low. FDD interface signals are active high. Bit 5: DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. - 70 - W83697HF/ HG Bit 4: Swap Drive 0, 1 Mode =0 =1 = 11 No Swap (Default) Drive and Motor select 0 and 1 are swapped. AT Mode (Default) Bit 3 - 2 Interface Mode = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit 1: FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0: Floppy Mode = 0 Normal Floppy Mode (Default) = 1 Enhanced 3-mode FDD CRF1 (Default 0x00) Bit 7 - 6: Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit 3 - 2: Density Select = 00 Normal (Default) = 01 Normal = 10 1 ( Forced to logic 1) = 11 0 ( Forced to logic 0) Bit 1: DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD stay high). Bit 0: SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. = 1 FDD is always write-protected. - 71 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG CRF2 (Default 0xFF) Bit 7 - 6: FDD D Drive Type Bit 5 - 4: FDD C Drive Type Bit 3 - 2: FDD B Drive Type Bit 1 - 0: FDD A Drive Type CRF4 (Default 0x00) FDD0 Selection: Bit 7: Reserved. Bit 6: Precomp. Disable. = 1 Disable FDC Precompensation. = 0 Enable FDC Precompensation. Bit 5: Reserved. Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). = 00 Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2: Reserved. Bit 1:0: DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A DRIVE RATE TABLE SELECT DATA RATE SELECTED DATA RATE SELDEN DRTS1 0 DRTS0 0 0 1 1 0 DRATE1 1 0 0 1 1 0 0 1 1 0 0 1 DRATE0 1 0 1 0 1 0 1 0 1 0 1 0 MFM 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K FM --250K 150K 125K --250K 250K 125K --250K --125K 1 1 0 0 1 1 0 0 1 1 0 0 - 72 - W83697HF/ HG TABLE B DTYPE0 DTYPE1 DRVDEN0(PIN 2) DRVDEN1(PIN 3) DRIVE TYPE 0 0 1 1 0 1 0 1 SELDEN DRATE1 SELDEN DRATE0 DRATE0 DRATE0 DRATE0 DRATE1 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” (3-MODE) 7.6 Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Parallel Port. CR74 (Default 0x04) Bit 7 - 3: Reserved. Bit 2 - 0: These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active - 73 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG CRF0 (Default 0x3F) Bit 7: Reserved. Bit 6 - 3: ECP FIFO Threshold. Bit 2 - 0: Parallel Port Mode (CR28 PRTMODS2 = 0) = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. 7.7 Logical Device 2 (UART A) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7 - 2: Reserved. Bit 1 - 0: SUACLKB1, SUACLKB0 = 00 = 01 = 10 = 11 UART A clock source is 1.8462 Mhz (24MHz/13) UART A clock source is 2 Mhz (24MHz/12) UART A clock source is 24 Mhz (24MHz/1) UART A clock source is 14.769 Mhz (24mhz/1.625) - 74 - W83697HF/ HG 7.8 Logical Device 3 (UART B) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. CRF0 (Default 0x00) Bit 7 - 4: Reserved. Bit 3: RXW4C =0 =1 No reception delay when SIR is changed from TX mode to RX mode. Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. No transmission delay when SIR is changed from RX mode to TX mode. Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. UART B clock source is 1.8462 Mhz (24MHz/13) UART B clock source is 2 Mhz (24MHz/12) UART B clock source is 24 Mhz (24MHz/1) UART B clock source is 14.769 Mhz (24mhz/1.625) Bit 2: TXW4C =0 =1 Bit 1 - 0: SUBCLKB1, SUBCLKB0 = 00 = 01 = 10 = 11 CRF1 (Default 0x00) Bit 7: Reserved. Bit 6: IRLOCSEL. IR I/O pins' location select. =0 =1 Through SINB/SOUTB. Through IRRX/IRTX. Bit 5: IRMODE2. IR function mode selection bit 2. Bit 4: IRMODE1. IR function mode selection bit 1. Bit 3: IRMODE0. IR function mode selection bit 0. - 75 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG IR MODE IR FUNCTION IRTX IRRX 00X 010* 011* 100 101 110 111* Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR tri-state Active pulse 1.6 µS Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Note: The notation is normal mode in the IR function. Bit 2: HDUPLX. IR half/full duplex function select. =0 =1 =0 =1 =0 =1 The IR function is Full Duplex. The IR function is Half Duplex. the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. inverse the SOUTB pin of UART B function or IRTX pin of IR function. the SINB pin of UART B function or IRRX pin of IR function in normal condition. inverse the SINB pin of UART B function or IRRX pin of IR function Bit 1: TX2INV. Bit 0: RX2INV. 7.9 Logical Device 6 (CIR) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select CIR I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for CIR. - 76 - W83697HF/ HG 7.10 Logical Device 7 (Game Port GPIO Port 1) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activate Game Port./GP1 = 0 Game Port/GP1 is inactive. CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the Game Port base address [0x100:0xFFF] on 8 byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select the GPIO1 base address [0x100:0xFFF] on 1 byte boundary IO address : CRF1 base address CRF0 (GP10-GP17 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP10-GP17 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP10-GP17 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 77 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 7.11 Logical Device 8 (MIDI Port and GPIO Port 5) CR30 (MIDI Port Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 MIDI/GP5 port is Activate = 0 MIDI/GP5 port is inactive. CR60, CR 61 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the MIDI Port base address [0x100:0xFFF] on 2byte boundary. CR62, CR 63 (Default 0x00, 0x00 ) These two registers select the GPIO5 base address [0x100:0xFFF] on 4byte boundary. IO address : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF4 base address IO address + 3 : CRF5 base address CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for MIDI Port . CRF0 (GP5 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP5 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP5 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 78 - W83697HF/ HG CRF3 (PLED mode register. Default 0x00) Bit 7 ~ 3 : Reserved . Bit 2: select WDTO# count mode. =0 =1 = 00 = 01 = 10 = 11 second minute Power LED pin is tri-stated. Power LED pin is droved low. Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. Bit 1 ~ 0: select PLED mode Power LED pin is a 1Hz toggle pulse with 50 duty cycle. CRF4 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. Bit 7 - 0: = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes CRF5 (Default 0x00) Bit 7 ~ 6 : Reserved . Bit 5: Force Watch Dog Timer Time-out, Write only* = 1 Force Watch Dog Timer time-out event; this bit is self-clearing. Bit 4: Watch Dog Timer Status, R/W = 1 Watch Dog Timer time-out occurred. = 0 Watch Dog Timer counting Bit 3 -0: These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI. - 79 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 7.12 Logical Device 9 (GPIO Port 2 ~ GPIO Port 4 ) CR30 (Default 0x00) Bit 7 ~ 3: Reserved. Bit 2: = 1 Activate GPIO4. = 0 GPIO4 is inactive Bit 1: = 1 Activate GPIO3. = 0 GPIO3 is inactive Bit 0: = 1 Activate GPIO2. = 0 GPIO2 is inactive. CR60,61(Default 0x00,0x00). These two registers select the GP2,3,4 base address(0x100:FFE) ON 3 bytes boundary. IO address: : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF7 base address CRF0 (GP2 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP2 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP2 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (GP3 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF4 (GP3 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF5 (GP3 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF6 (GP4 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. - 80 - W83697HF/ HG CRF7 (GP4 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF8 (GP5 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. - 81 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 7.13 Logical Device A (ACPI) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resources for S M I / PME CRE0 (Default 0x00) Bit7 : ENCIRWAKEUP. Enable CIR to wake-up system . = 0 Disable CIR wake up function = 1 Enable CIR wake up function Bit 5 : CIR_STS. This bit is cleared by reading 1 this register. = 0 Disable = 1 Enable Bit6, 4 ~ 0 : Reserved CRE 1 (Default 0x00) CIR wake up index register The range of CIR wake up index register is 0x20 ~ 0x2F . CRE 2 CIR wake up data register This register holds the value of wake up key register indicated by CRE1. This register can be read/written. CRE5 (Default 0x00) Bit 7 : Reserved Bit 6 ~ 0 :Compared Code Length . When the compared codes are storage in the data register, these data length should be written to this register. CRE6 (Default 0x00) Bit 7 - 6: Reserved. Bit 5 - 0: CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz divided by ( CIR Baud Rate Divisor + 1). - 82 - W83697HF/ HG CRE7 (Default 0x00) Bit 7 - 3: Reserved. Bit 2:Reset CIR Power-On function. After using CIR power-on, the software should write logical 1 to restart CIR power-on function. Bit 1: Invert RX Data. = 1 Inverting RX Data. = 0 Not inverting RX Data. Bit 0: Enable Demodulation. = 1 Enable received signal to demodulate. = 0 Disable received signal to demodulate. CRF0 (Default 0x00) Bit 7: CHIPPME. Chip level auto power management enable. =0 =1 =0 =1 =0 =1 disable the auto power management functions enable the auto power management functions. disable the auto power management functions enable the auto power management functions. disable the auto power management functions enable the auto power management functions. Bit 6: CIRPME. Consumer IR port auto power management enable. Bit 5: MIDIPME. MIDI port auto power management enable. Bit 4: Reserved. Return zero when read. Bit 3: PRTPME. Printer port auto power management enable. =0 =1 =0 =1 =0 =1 =0 =1 disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. Bit 2: FDCPME. FDC auto power management enable. Bit 1: URAPME. UART A auto power management enable. Bit 0: URBPME. UART B auto power management enable. - 83 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG CRF1 (Default 0x00) Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. =0 =1 the chip is in the sleeping state. the chip is in the working state. Bit 6 - 5: Devices' trap status. Bit 4: Reserved. Return zero when read. Bit 3 - 0: Devices' trap status. CRF3 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 3: PRTIRQSTS. printer port IRQ status. Bit 2: FDCIRQSTS. FDC IRQ status. Bit 1: URAIRQSTS. UART A IRQ status. Bit 0: URBIRQSTS. UART B IRQ status. CRF4 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a1. Writing a 0 has no effect. Bit 3: HMIRQSTS. Hardware monitor IRQ status. Bit 2: WDTIRQSTS. Watch dog timer IRQ status. Bit 1: CIRIRQSTS. Consumer IR IRQ status. Bit 0: MIDIIRQSTS. MIDI IRQ status. - 84 - W83697HF/ HG CRF6 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: Enable bits of the PME/ SMI generation due to the device's IRQ. These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. SMI / PME logic output = (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or (IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS) Bit 3: PRTIRQEN. =0 =1 disable the generation of an SMI / PME interrupt due to printer port's IRQ. enable the generation of an SMI / PME interrupt due to printer port's IRQ. Bit 2: FDCIRQEN. =0 =1 disable the generation of an SMI / PME interrupt due to FDC's IRQ. enable the generation of an SMI / PME interrupt due to FDC's IRQ. disable the generation of an SMI / PME interrupt due to UART A's IRQ. enable the generation of an SMI / PME interrupt due to UART A's IRQ. disable the generation of an SMI / PME interrupt due to UART B's IRQ. enable the generation of an SMI / PME interrupt due to UART B's IRQ. Bit 1: URAIRQEN. =0 =1 Bit 0: URBIRQEN. =0 =1 CRF7 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ. Bit 3: HMIRQEN. =0 =1 disable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. enable the generation of an SMI / PME interrupt due to hardware monitor's IRQ. - 85 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Bit 2: WDTIRQEN. =0 =1 disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. enable the generation of an SMI / SMI interrupt due to watch dog timer's IRQ. disable the generation of an SMI / PME interrupt due to CIR's IRQ. enable the generation of an SMI / PME interrupt due to CIR's IRQ. disable the generation of an SMI / PME interrupt due to MIDI's IRQ. enable the generation of an SMI / PME interrupt due to MIDI's IRQ. Bit 1: CIRIRQEN. =0 =1 Bit 0: MIDIIRQEN. =0 =1 CRF9 (Default 0x00) Bit 7 - 3: Reserved. Return zero when read. Bit 2: PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1. = 0 the power management events will generate an SMI event. = 1 the power management events will generate an PME event. Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices. =0 1S = 1 8 mS. Bit 0: SMIPME_OE: This is the SMI and PME output enable bit. = 0 neither SMI nor PME will be generated. Only the IRQ status bit is set. = 1 an SMI or PME event will be generated. - 86 - W83697HF/ HG 7.14 Logical Device B (Hardware Monitor) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Hardware Monitor. - 87 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 8. SPECIFICATIONS 8.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage (5V) Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature -0.5 to 7.0 -0.5 to VDD+0.5 2.2 to 4.0 0 to +70 -55 to +150 V V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8.2 DC CHARACTERISTICS (Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage IBAT IBAT 2.4 2.0 uA mA VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected. I/O8t - TTL level bi-directional pin with 8mA source-sink capability VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V µA µA V V 0.4 2.4 +10 -10 V V µA µA IOL = 12 mA IOH = -12 mA VIN = 5V VIN = 0V IOL = 8 mA IOH = - 8 mA VIN = 5V VIN = 0V I/O12t - TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.0 0.8 - 88 - W83697HF/ HG 82 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O24t - TTL level bi-directional pin with 24mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V µA µA V V 0.4 2.4 +10 -10 V V µA µA IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V IOL = 24 mA IOH = -24 mA VIN = 5V VIN = 0V I/O12tp3 – 3.3V TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.0 0.8 I/O12ts - TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V µA µA VDD=5V IOL = 12 mA IOH = -12 mA VIN = 5V VIN = 0V I/O24ts - TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage VtVt+ VTH VOL VOH 2.4 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V VDD=5V IOL = 24 mA IOH = -24 Ma - 89 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 82 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX . UNIT CONDITIONS Input High Leakage Input Low Leakage ILIH ILIL +10 -10 µA µA VIN = 5V VIN = 0V I/O24tsp3 – 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V µA µA V V 0.4 +10 -10 V µA µA V V 0.4 +10 -10 V µA µA V V 0.4 +10 -10 V µA µA IOL = 24 mA VIN = 5V VIN = 0 V IOL = 24 mA VIN = 5V VIN = 0V IOL = 12 mA VIN = 5V VIN = 0V VDD=3.3V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V I/OD12t - TTL level bi-directional pin and open-drain output with 12mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.8 I/OD24t - TTL level bi-directional pin and open-drain output with 24mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.8 I/OD24c - CMOS level bi-directional pin and open drain output with 24mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 3.5 1.5 - 90 - W83697HF/ HG 82 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/OD24a - Bi-directional pin with analog input and open-drain output with 24mA sink capability Output Low Voltage Input High Leakage Input Low Leakage VOL ILIH ILIL 0.4 +10 -10 V µA µA IOL = 24 mA VIN = 5V VIN = 0V I/OD12ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V µA µA VDD=5V IOL = 12 mA VIN = 5V VIN = 0V I/OD24ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V µA µA VDD=5V IOL = 24 mA VIN = 5V VIN = 0V I/OD12cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V µA µA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5V VIN = 0 V - 91 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 82 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/OD16cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 16mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V µA µA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 16 mA VIN = 5V VIN = 0 V I/OD24cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V µA µA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 24 mA VIN = 5V VIN = 0 V I/OD12csd - CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open drain output with 12mA sink capability Input Low Threshold Vt1.3 1.5 1.7 V VDD = 5 V Voltage Input High Threshold 3.2 3.5 3.8 V VDD = 5 V Vt+ Voltage Hystersis VTH 1.5 2 V VDD = 5 V Output Low Voltage VOL 0.4 V IOL = 12 mA Input High Leakage ILIH +10 VIN = 5V µA ILIL -10 VIN = 0 V µA I/OD12csu - CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open drain output with 12mA sink capability Input Low Threshold Vt1.3 1.5 1.7 V VDD = 5 V Voltage Input High Threshold 3.2 3.5 3.8 V VDD = 5 V Vt+ Voltage Hystersis VTH 1.5 2 V VDD = 5 V Output Low Voltage VOL 0.4 V IOL = 12 mA Input High Leakage ILIH +10 VIN = 5V µA Input Low Leakage - 92 - W83697HF/ HG 82 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS Input Low Leakage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage ILIL VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH 2.4 2.4 2.4 2.4 2.4 -10 0.4 µA V V VIN = 0 V IOL = 4 mA IOH = -4 mA IOL = 8 mA IOH = -8 mA IOL = 12 mA IOH = -12 mA IOL = 16 mA IOH = -16 mA IOL = 24 mA IOH = -24 mA O4 - Output pin with 4mA source-sink capability O8 - Output pin with 8mA source-sink capability 0.4 V V 0.4 V V 0.4 V V 0.4 V V O12 - Output pin with 12mA source-sink capability O16 - Output pin with 16mA source-sink capability O24 - Output pin with 24mA source-sink capability O12p3 - 3.3V output pin with 12mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA O24p3 - 3.3V output pin with 24mA source-sink capability Output Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Output Low Voltage Output Low Voltage VOL VOH VOL VOL VOL VOL 2.4 0.4 0.4 0.4 0.4 0.4 V V V V V V IOL = 24 mA IOH = -24 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA IOL = 12 mA OD8 - Open drain output pin with 8mA sink capability OD12 - Open drain output pin with 12mA sink capability OD24 - Open drain output pin with 24mA sink capability OD12p3 - 3.3V open drain output pin with 12mA sink capability - 93 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 82 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INtp3 - 3.3V TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VIL VIH ILIH ILIL VIL VIH ILIH ILIL VIL VIH ILIH ILIL VtVt+ VTH ILIH ILIL VtVt+ VTH ILIH ILIL 0.8 1.8 0.8 0.9 1.9 1.0 0.8 1.8 0.8 0.9 1.9 1.0 0.8 2.0 +10 -10 0.8 2.0 +10 -10 0.8 2.0 +10 -10 1.0 2.0 +10 -10 1.0 2.0 +10 -10 V V µA µA V V µA µA V V µA µA V V V µA µA V V V µA µA VIN = 5V VIN = 0 V VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5V VIN = 0 V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V VIN = 5V VIN = 0 V VIN = 3.3V VIN = 0 V VIL VIH ILIH ILIL 0.8 2.0 +10 -10 V V µA µA VIN = 5V VIN = 0 V INtd - TTL level input pin with internal pull down resistor INtu - TTL level input pin with internal pull up resistor - TTL level Schmitt-trigger input pin INtsp3 - 3.3 V TTL level Schmitt-trigger input pin - 94 - W83697HF/ HG 82 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS INc - CMOS level input pin VIL VIH ILIH ILIL 3.5 +10 -10 1.5 V V µA µA V V +10 -10 µA µA V V +10 -10 µA µA VIN = 5V VIN = 0 V VIN = 5V VIN = 0 V VIN = 5V VIN = 0 V Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INcu - CMOS level input pin with internal pull up resistor VIL VIH ILIH ILIL 3.5 1.5 Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INcd - CMOS level input pin with internal pull down resistor VIL VIH ILIH ILIL 3.5 1.5 Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INcs - CMOS level Schmitt-trigger input pin VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 +10 -10 1.7 3.8 V V V µA µA VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5 V VIN = 0 V Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INcsu - CMOS level Schmitt-trigger input pin with internal pull up resistor VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 +10 -10 1.7 3.8 V V V µA µA VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5V VIN = 0 V Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage - 95 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 9. APPLICATION CIRCUITS 9.1 Parallel Port Extension FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram - 96 - W83697HF/ HG 9.2 Parallel Port Extension 2FDD JP13 WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP 13A DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2 RWC2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 EXT FDC PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 9.3 Four FDD Mode W83977F DSA DSB MOA MOB G2 A2 B2 74LS139 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 7407(2) DSA DSB DSC DSD MOA MOB MOC MOD - 97 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 10. ORDERING INSTRUNCTION PART NO. PACKAGE REMARKS W83697HF/W83697HG 128-pin QFP W83697HG is Pb-free package 11. HOW TO READ THE TOP MARKING Example: The top marking of W83697HF inbond W83697HF 421A2B28201234 Example: The top marking of W83697HG inbond W83697HG 421A2B28201234 1st line: Winbond logo 2nd line: the type number: W83697HF, W83697HG 3th line: the tracking code 421 A 2 C 28201234 421: packages made in '04, week 21 A: assembly house ID; A means ASE, S means SPIL.... etc. 2: Winbond internal use. B: IC revision; A means version A, B means version B 282012345: wafer production series lot number - 98 - W83697HF/ HG 12. PACKAGE DIMENSIONS (128-pin PQFP) HE E 102 65 Symbol Dimension in mm Dimension in inch Min 0.25 2.57 0.10 0.10 13.90 19.90 Nom 0.35 2.72 0.20 0.15 14.00 20.00 0.50 Max 0.45 2.87 0.30 0.20 14.10 20.10 Min 0.010 0.101 0.004 0.004 0.547 0.783 Nom 0.014 0.107 0.008 0.006 0.551 0.787 0.020 Max 0.018 0.113 0.012 0.008 0.555 0.791 103 64 D HD 128 39 1 e b 38 A1 A2 b c D E e HD HE L L1 y 0 c 17.00 23.00 0.65 17.20 23.20 0.80 1.60 17.40 23.40 0.95 0.669 0.905 0.025 0.677 0.913 0.031 0.063 0.685 0.921 0.037 0.08 0 7 0 0.003 7 Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. A A2 See Detail F Seating Plane A1 L L1 Detail F y 5. PCB layout please use the "mm". - 99 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG 13. APPENDIX A : DEMO CIRCUIT W83697HF XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XA18 XD[0..7] XD[0..7] ROMCS# MEMR# MEMW# PME# CIRRX CASEOPEN XA[0..18] XA[0..18] (To monitor battery voltage, this input should be connected directly to battery) 5VSB VBAT VCC C1 0.1u C2 0.1u C3 0.1u IRTX 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 C4 VCC3V R1 4.7K 0.1u VTIN2 VTIN1 AVCC VREF VCORE +3.3VIN +12VIN -12VIN -5VIN AGND FANIO2 FANIO1 FANPWM2 FANPWM1 OVT# BEEP MSI MSO GPAS2 GPBS2 GPAY GPBY GPBX GPAX GPBS1 GPAS1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VTIN2 VTIN1 AVCC VREF VCORE +3.3VIN +12VIN -12VIN -5VIN AGND FANIO2 FANIO1 FANPWM2 FANPWM1 OVT#/SMI# BEEP MSI/GP51/WDTO MSO/GP50/PLED GSAS2/GP17 GPBS2/GP16 GPAY/GP15 GPBY/GP14 GPBX/GP13 GPAX/GP12 GPBS1/GP11 GPAS1/GP10 VBAT CASEOPEN CIRRX VSB PME# MEMW#/GP52 MEMR#/GP53 ROMCS#/GP54 XD0/GP20 XD1/GP21 XD2/GP22 XD3/GP23 GND XD4/GP24 XD5/GP25 XD6/GP26 XD7/GP27 XA0/GP30 XA1/GP31 XA2/GP32 XA3/GP33 XA4/GP34 XA5/GP35 XA6/GP36 XA7/GP37 XA8/GP40 XA9/GP41 VCC XA10/GP42 XA11/GP43 XA12/GP44 XA13/GP45 XA14/GP46 XA15/GP47 XA16/GP55 XA17/GP56 XA18/GP57 IRTX IR IRRX RIB# DCDB# SOUTB GND SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# VCC AFD# INIT# PD0 PD1 PD2 PD3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 IRRX RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# AFD# INIT# Temperature Sensing & COMB Voltage SENSING U1 W83697HF Fan Speed Seneing & Speed Control COMA MIDI PORT VCC GAME PORT C5 CAP NP 0.1u DRVDEN0 INDEX# MOA# DSB# VCC DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN GND PCICLK LDRQ# SERIRQ VCC3 LAD3 LAD2 LAD1 LAD0 LFRAME# LRESET# SLCT PE BUSY ACK# ERR# SLIN# PD7 PD6 PD5 PD4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 RWC# INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# 1 OSC1 NC OUTPUT 24/48MHz 5 PCICLK LDRQ# SERIRQ LAD[0..3] LFRAME# LRESET# R3 VCC3V VCC3V R R2 4.7K LAD3 LAD2 LAD1 LAD0 R PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Printer PD[0..7] PD[0..7] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VCC3V C6 0.1u C7 0.1u VCC |LINK |697HD2.SCH |697HD3.SCH |697HD4.SCH |697HD5.SCH SLIN# ERR# ACK# BUSY PE SLCT HEADER 17X2 FDC Winbond Electronic Corp. Title Size B Date: 4.7K LAD[0..3] W83697HF (LPC I/O + H/W + FLASH ROM I/N) Document Number 697HD1.SCH Thursday, July 11, 2002 Sheet 1 of 5 Rev 0.4 - 100 - W83697HF/ HG COM PORT VCC RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# 20 16 15 13 19 18 17 14 12 11 U2 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 (SOP20) +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V NRTSA NDTRA NSOUTA NRIA NCTSA NDSRA NSINA NDCDA -12V IR/CIR CONNECTOR NDCDA NSOUTA GND NRTSA NRIA J2 1 3 5 7 9 2 4 6 8 10 NSINA NDTRA NDSRA NCTSA VCC J4 1 2 3 4 5 CN2X5 6 7 8 9 10 CIRRX IOVSB CN2X5B COMA (UARTA) IRRX IRTX VCC RTSB# DTRB# SOUTB RIB# CTSB# DSRB# SINB DCDB# 20 16 15 13 19 18 17 14 12 11 U3 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 (SOP20) +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V NRTSB NDTRB NSOUTB NRIB NCTSB NDSRB NSINB NDCDB -12V NDCDB NSOUTB GND NRTSB NRIB J3 1 3 5 7 9 2 4 6 8 10 NSINB NDTRB NDSRB NCTSB THE IOVSB OF PIN 8 IS FOR CIR WAKE-UP FUNCTION. CN2X5B COMB (UARTB) PRT PORT 1 3 5 7 PD[0..7] PD0 PD1 PD2 PD3 1 3 5 7 RPACK1 2 4 6 8 VCC 1 VCC 1 RP1 10P9R-2.7K RP2 10P9R-2.7K 2 3 4 5 6 7 8 9 10 STB# AFD# INIT# SLIN# PD[0..7] 2 3 4 5 6 7 8 9 10 33 RPACK2 2 4 6 8 33 PD4 PD5 PD6 PD7 1 3 5 7 RPACK3 2 4 6 8 33 ERR# ACK# BUSY PE SLCT C8 180 C9 180 C10 180 C11 180 C12 180 C13 180 C14 180 C15 180 C16 180 C17 180 C18 180 C19 180 C20 180 C21 180 C22 180 C23 180 C24 180 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J5 DB25 WINBOND ELECTRONICS CORP. Title W83697HF (LPC I/O + H/W + FLASH ROM I/F) Size B Date: Document Number 697HD2.SCH Thursday, July 11, 2002 Sheet 2 of 5 Rev 0.4 - 101 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG GAME & MIDI PORT CIRCUIT IO5V IO5V IO5V IO5V IO5V IO5V BATTERY CIRCUIT VBAT BT1 BATTERY R4 1K C25 0.1UF JP5:1-2 Clear CMOS 2-3 Enable ONNOW functions 3 2 1 JP1 HEAD3 R24 100K R23 2.2K R20 2.2K R21 2.2K R22 2.2K L1 INDUCTOR MSI GPSA2 GPSB2 GPY1 GPY2 MSO GPX2 GPX1 GPSB1 GPSA1 R10 1M R14 2.2K R15 2.2K R16 2.2K R17 2.2K R18 2.2K R19 2.2K 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 P1 R11 1M R12 1M R13 1M PRT C32 0.01U C28 0.01U C29 0.01U C30 0.01U C31 0.01U C33 0.01U C34 0.01U C36 0.01U C35 0.01U FLASH ROM SELECT 2M-FLASH ROM, UNINSTALL R19 SELECT 4M-FLASH ROM, INSTALL R19 IOVSB CIRCUIT R9 0 U4 XA17 XA16 XA15 XA14 XA13 XA12 XA11 XA10 XA9 XA8 XA7 XA6 XA5 XA4 XA3 XA2 XA1 XA0 1 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 31 24 22 NC/A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 WE# OE# CE# W29C020/40 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 VCC XD[0..7] 5817 XD[0..7] D2 5VSB 5817 C27 10u D1 IOVSB OnNow or Wake_up function power R23 OFF, D1,D2 ON: Wake_up fuction R23 ON, D1,D2 OFF:NO Wake_up fuction R5 0 XA18 XA[0..18] XA[0..18] VCC R6 4.7K R7 4.7K R8 4.7K VCC VCC GND 32 16 CAP NP 0.1u C26 MEMW# MEMR# ROMCS# WINBOND ELECTRONICS CORP. Title Size B Date: W83697HF (LPC I/O + H/W + FLASH ROM I/F) Document Number 697HD3.SCH Thursday, July 11, 2002 Sheet 3 of 5 Rev 0.4 - 102 - W83697HF/ HG Hardware Monitor circuits Temperature Sensing Voltage Sensing CPUVCOA R27 10K R VCORE -12VIN VREF (for system) VCC3V R28 10K R -5VIN +3.3VIN R33 VTIN1 +12V R26 VTIN2 AGND 30K D+ DC39 3300P D+ DR29 28K 1% (from Deschutes) R R30 10K 1% R +12VIN AGND 56K 1% R34 -5V 120K 1% R31 56K 1% R32 -12V 232K 1% VREF R25 10K 1% RT1 10K 1% THERMISTOR T PWM Circuit for FAN speed control +12V R35 R36 4.7K 1K Q1 PNP 3906 JP2 + 3 2 1 HEADER 3 D3 1N4148 R37 4.7K R38 27K R39 10K Beep Circuits VCC R47 100 LS1 R46 10K SPEAKER FANIO1 BEEP Q5 3904 FANPWM1 R48 510 Q2 MOSFET N 2N7002 C37 10u +12V R41 R42 4.7K 1K Q3 PNP 3906 D4 1N4148 R43 4.7K R44 27K R45 10K L2 AVCC FB L3 AGND FB VCC FANPWM2 R40 510 Q4 MOSFET N 2N7002 C38 10u JP3 + 3 2 1 HEADER 3 FANIO2 R49 VBAT 2M CASEOPEN# S1 CASEOPEN SW Winbond Electronic Corp. Title W83697HF (LPC I/O+ H/W + FLASH ROM I/F) Size B Date: Document Number 697HD4.SCH Thursday, July 11, 2002 Sheet 4 of 5 Rev 0.4 - 103 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG The version 0.1 is first schematics for W83697HF The version 0.2 change 1.update 697's library 2.The sheet 4 in Case open block,part 74HC14 is U4A & U4B changed to U5A & U5B The version 0.3 chage 1.Case-Open circuit(in page 4) The version 0.4 chage add a pull high resistor 100K in midiin(in page 3) WINBOND ELECTRONICS CORP. Title W83627HF (LPC I/O + H/W + FLASH ROM I/F) Size B Date: Document Number CHANGED NOTICS Thursday, July 11, 2002 Sheet 5 of 5 Rev 0.3 - 104 - W83697HF/ HG 14. REVISION HISTORY VERSION DATE PAGE DESCRIPTION 0.40 0.41 0.50 1.0 1.1 08/23/99 11/15/99 11/15/00 12/17/02 02/18/03 n.a. 98, 107, 116 All First published. For Beta Site customers only H/W monitor register correction New composition 　 New update 5,6 1.P7 2.P17~18 3.P74 　 Add Block Diagram 　 1.Add pin buffer type description ofOD8. 　 2.Update the functional description of 　 Pin117~126. 　 3. Update the chip control register CR29 　 4. Add VOH of O12p3,O24p and OD8 　 　 description in DC specification 　WDTO#” 1.2 4.P99 1.3 A1 12/01/04 May 30, 2005 106 　 5. The pin name WDTO” were replaced by 　 6 H/W monitor data correction Add Pb-free part no of W83697HG ADD Important Notice - 105 - Publication Release Date: May 30, 2005 Revision A1 W83697HF/ HG Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 106 -