W83781D

W83781D/W83781G W 83781D/W83781G W INBOND H /W MONITORING IC -I- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G Table Of Contents1. 2. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 1 2.1 2.2 2.3 2.4 3. 4. 5. 6. 7. Monitoring Items ............................................................................................................. 1 Actions Enabling ............................................................................................................. 1 General ........................................................................................................................... 2 Package .......................................................................................................................... 2 KEY SPECIFICATIONS .............................................................................................................. 2 BLOCK DIAGRAM ...................................................................................................................... 3 PIN CONFIGURATION ............................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 4 FUNCTIONAL DESCRIPTION ................................................................................................... 6 7.1 General Description ........................................................................................................ 6 7.1.1 7.1.2 The first serial bus access timing is shown as follows: .....................................................8 The serial bus timing of the temperature 2 and 3 is shown as follows: .............................9 7.2 7.3 7.4 8. Analog Inputs ................................................................................................................ 11 FAN Inputs and FAN Control ........................................................................................ 12 Temperature Measurement Machine ........................................................................... 13 CONTROL AND STATUS REGISTERS................................................................................... 15 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Address Register (Port x5h) ......................................................................................... 15 Data Register (Port x6h) ............................................................................................... 18 Configuration Register – Index 40h (Bank 0) ............................................................... 18 Interrupt Status Register 1 – Index 41h (Bank 0) ......................................................... 19 Interrupt Status Register 2 – Index 42h (Bank 0) ......................................................... 19 SMI# Mask Register 1 – Index 43h (Bank 0)............................................................... 20 SMI# Mask Register 2 – Index 44h (Bank 0)................................................................ 20 IRQ Mask Register 2 – Index 45h (Bank 0).................................................................. 21 Publication Release Date: April 14, 2005 Revision 2.0 - II - W83781D/W83781G 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 8.33 8.34 8.35 IRQ Mask Register 2 – Index 46h (Bank 0).................................................................. 21 VID/Fan Divisor Register – Index 47h (Bank 0) ........................................................... 22 Serial Bus Address Register – Index 48h (Bank 0) ...................................................... 23 Value RAM – Index 20h - 3Fh or 60h - Index 7Fh (auto-increment) (Bank 0) ............. 23 Voltage ID (VID7-4) – Index 49h (Bank 0).................................................................... 25 Temperature 2 and Temperature 3 Serial Bus Address Register Index 4Ah (Bank 0) 26 Pin Control Register – Index 4Bh (Bank 0)................................................................... 27 IRQ/OVT# Property Select – Index 4Ch (Bank 0) ....................................................... 28 FAN IN/OUT and BEEP/GPO# Control Register – Index 4Dh (Bank 0) ...................... 28 Register 50h ~ 5Fh Bank Select – Index 4Eh (No Auto Increase) (Bank 0) ................ 29 Winbond Vendor ID – Index 4Fh (No Auto Increase) (Bank 0) .................................... 30 Resistor-Temperature Table Register – Index 50h - 51h (Bank 0) .............................. 30 Winbond Test Register 1 – Index 52h (Bank 0) ........................................................... 31 Winbond Test Register 2 – Index 53h (Bank 0) ........................................................... 31 Winbond Test Register 3 – Index 54h (Bank 0) ........................................................... 31 Winbond Test Register 4 – Index 55h (Bank 0) ........................................................... 31 BEEP Control Register 1 – Index 56h (Bank 0) (Auto-increment) ............................... 31 BEEP Control Register 2 – Index 57h (Bank 0) ( No Auto-increment)......................... 31 Chip ID – Index 58h (Bank 0) ....................................................................................... 32 Temperature Sensor 2 Temperature Register – Index 50h (Bank 1)........................... 32 Temperature Sensor 2 Temperature Register – Index 51h (Bank 1)........................... 33 Temperature Sensor 2 Configuration Register – Index 52h (Bank 1) .......................... 33 Temperature Sensor 2 Hysteresis (High Byte) Register – Index 53h (Bank 1) ........... 34 Temperature Sensor 2 Hysteresis (Low Byte) Register – Index54h (Bank 1) ............. 34 Temperature Sensor 2 Over-temperature(High Byte) Register – Index 55h (Bank 1). 35 Temperature Sensor 2 Over-temperature (Low Byte) Register – Index 56h (Bank 1)......... 35 Temperature Sensor 3 Temperature Register - Index 50h (Bank 2)............................ 36 Publication Release Date: April 14, 2005 Revision 2.0 - III - W83781D/W83781G 8.36 8.37 8.38 8.39 8.40 8.41 9. Temperature Sensor 3 Temperature Register – Index 51h (Bank 2)........................... 37 Temperature Sensor 3 Configuration Register – Index 52h (Bank 2) .......................... 37 Temperature Sensor 3 Hysteresis (High Byte) Register – Index 53h (Bank 2) ........... 38 Temperature Sensor 3 Hysteresis (Low Byte) Register – Index 54h (Bank 2) ............ 38 Temperature Sensor 3 over temperature (High Byte)Register – Index 55h (Bank 2).. 38 Temperature Sensor 3 Over-temperature (Low Byte) Register – Index 56h (Bank 2) ........ 39 ELECRICAL CHARACTERISTICS ........................................................................................... 40 9.1 9.2 9.3 Absolute Maximum Ratings .......................................................................................... 40 DC Characteristics........................................................................................................ 40 AC Characteristics ........................................................................................................ 42 9.3.1 9.3.2 ISA Read/Write Interface Timing ....................................................................................42 Serial Bus Timing Diagram.............................................................................................44 10. 11. 12. HOW TO READ THE TOP MARKING...................................................................................... 45 PACKAGE DIMENTIONS ......................................................................................................... 46 APPLICATION CIRCUITS OF W83781D ................................................................................. 47 REVISION HISTORY ............................................................................................................................ 49 - IV - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 1. GENERAL DESCRIPTION The W83781D/G is a hardware monitoring IC for personal computers, server computers, or microprocessor based systems. W83781D/G can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stablely and properly. W83781D provides both ISA and I2CTM serial bus interface. A 8-bit analog-to-digital converter (ADC) was built inside W83781D/G. The W83781D/G can monitor 3 external thermistor temperature sensors, 5 positive analog voltage inputs, two inverting inputs (for monitoring negative voltages), and also three fan tachometer outputs. There is also one input for case open detection circuits. With the application software, the users can read all the monitored parameters of system from time to time. The application software could be the popular IntelTM LDCM (LANDesk Client Management) or Winbond 　 application software. Also the users can set up the upper and lower limits of these monitored parameters and to activate two programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters is out of the preset range. Additionally, 5 VID inputs are provided to read the VID of CPU (such as PentiumTM II) if applicable. This is to provide the Vcore correction automatically. Also W83781D uniquely provides an optional feature: early stage (before BIOS was load) beep warning. This is to detect if the fatal elements present --- VcoreA, +3.3V voltage fail, and the system can not be boomed up. 2. FEATURES 2.1 Monitoring Items • • • • • • • 3 thermal inputs from remote thermistors 5 positive voltage inputs (typical for +12V, +5V, +3.3V, VcoreA, VcoreB) 2 op amps for negative voltage monitoring (typical for -12V, -5V) 3 fan speed monitoring inputs Case open detection input WATCHDOG comparison of all monitored values Programmable hysteresis and setting points for all monitored items 2.2 Actions Enabling • • • • Warning signal pop up in application software Beep tone warning Fan ON/OFF control Issue SMI#, IRQ to activate system protection -1- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 2.3 General • • • • • • • • ISA and I2CTM serial bus interface 5 VID input pins for CPU Vcore identification Initial power fault beep (for +3.3V, VcoreA) Master reset input to W83781D/G Independent power plane of digital Vcc and analog Vcc (input to IC) Intel LDCMTM compatible Winbond monitoring application software support Input clock rate optional for 24, 48, 14.318 MHz 2.4 Package • 48-pin LQFP 3. KEY SPECIFICATIONS • • • • • Voltage monitoring accuracy - 40°C to +120°C Supply Voltage Supply Current ±1% (Max) ± 3°C(Max) 5V Operating: 1 mA typ. Shutdown: 10 μA typ. ADC Resolution 8 Bits Monitoring Temperature Range and Accuracy -2- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 4. BLOCK DIAGRAM IN0 : IN6 VID0 : VID4 VTIN3 : VTIN1 FAN3 : FAN1 : : 8-Bit A/D and Mux 16mV LSB 0~4.096V Input SMI# : : Configure and Control Registers : : FAN Speed Counter Watch-Dog and Interrupt Status Registers IRQ OVT# : : CASEOPEN BEEP / GPO# MR ISA/Serial Bus Interface RSTOUT# SS DC AL (Serial Bus) C L K I N I O W R # I O R D # DDDDDDDD CAAA 76543210 S210 # (ISA Bus Interface) -3- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 5. PIN CONFIGURATION B E E P / GV P OI #D 25 24 V C O R E A V C O R E B + ++- 3. 5 12 12 12 3V VVV VI O 5 V O U T 5G VN D IA 36 VREF VTIN3 VTIN2 VTIN1 VID0 OVT# IRQ SMI# A2 A1 A0 CS# 37 W83781D 48 1 12 13 VID2 RSTOUT# SDA SC L FAN1 IN/OUT FAN2 IN/OUT FAN3 IN/OUT VID4 CASEOPEN MR G ND D VCC I O R # I O W # CD DDD D D D D V L7 6543 2 1 0 I D K 1 I N 6. PIN DESCRIPTION I/O12t I/O12ts - TTL level bi-directional pin with 12 mA source-sink capability - TTL level and schmitt trigger OUT12t - TTL level output pin with 12 mA source-sink capability OUT8t - TTL level output pin with 8 mA source-sink capability AOUT - Output pin(Analog) OD 8 OD12 OD48 INt INts AIN - Open-drain output pin with 8 mA sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 48 mA sink capability - TTL level input pin - TTL level input pin and schmitt trigger - Input pin(Analog) -4- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G PIN NAME PIN NO. TYPE DESCRIPTION IOR# IOW# CLKIN D7~D0 VID1 VCC (+5V) GNDD MR 1 2 3 4-11 12 13 14 15 IN t s IN t s IN t I/O12t INt POWER DGROUND IN t s An active low standard ISA bus I/O Read Control. An active low standard ISA bus I/O Write Control. System clock input. Can select 48MHz or 24MHz or 14.318MHz. The default is 24MHz. Bi-directional ISA bus Data lines. D0 corresponds to the low order bit, with D7 the high order bit. Voltage Supply readouts from P6.This value is read in the VID/Fan Divisor Register. +5V VCC power. Bypass with the parallel combination of 10μF (electrolytic or tantalum) and 0.1μF (ceramic) bypass capacitors. Internally connected to all digital circuitry. Master reset input. CASE OPEN. An active high input from an external circuit which latches a Case Open event. This line can go high without any clamping action intrusion regardless of the powered state of the W83781D/G. The W83781D/G provides an internal open drain on this line, controlled by Bit 7 of IRQ Mask Register 2, to provide a minimum 20 ms reset of this line. Voltage Supply readouts from P6.This value is read in the bit of Device ID Register. 0V to +5V amplitude fan tachometer input / Fan on-off control output. These multifunctional pins can be programmable input or output. Serial Bus Clock. Serial Bus bi-directional Data. 8 mA driver (open drain), active low output with a 20 ms minimum pulse width. Available when enabled via Bit 7 in SMI# Mask Register 2. Voltage Supply readouts from P6.This value is read in the VID/Fan Divisor Register. Voltage Supply readouts from P6.This value is read in the VID/Fan Divisor Register. Beep function or General purpose output (active low). This pin is open drain driving 48 mA. This multifunctional pin is programmable selected by CR4D bit 6. Internally connected to all analog circuitry. The ground reference for all analog inputs. Ground-referred inverting op amp input. Output of inverting op amp for Input 6. Output of inverting op amp for Input 5. Publication Release Date: April 14, 2005 Revision 2.0 CASEOPEN 16 I/O12t VID4 FAN3-FAN1 IN/OUT SCL SDA RSTOUT# 17 18-20 21 22 23 24 25 IN t I/O12ts INt s I/O12ts OUT8t IN t IN t VID2 VID3 BEEP/GPO# 26 OD48 GNDA -5VIN -5VOUT -12VOUT 27 28 29 30 AGROUND AIN AOUT AOUT -5- W83781D/W83781G Continued PIN NAME PIN NO. TYPE DESCRIPTION -12VIN +12VIN +5VIN +3.3VIN VCOREB VCOREA VREF VTIN3 VTIN2 VTIN1 VID0 OVT# IRQ SMI# A2-A0 CS# 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45-47 48 AIN AIN AIN AIN AIN AIN AOUT AIN AIN AIN IN t OD12 OUT12t OD12 IN t IN t Ground-referred inverting op amp input. 0V to 4.096V FSR Analog Inputs. This pin is Analog Vcc and connects internal monitor channel IN3 with fixed scale. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. Reference Voltage. Thermistor 3 terminal input. Thermistor 2 terminal input. Thermistor 1 terminal input. Voltage Supply readouts from P6.This value is read in the VID/Fan Divisor Register. Over temperature Shutdown Output. Interrupt Request. System Management Interrupt (open drain). This output is enabled when Bit 1 in the Configuration Register (CR40) is set to 1. The default state is disabled. The three lowest order bits of the 16-bit ISA Address Bus. A0 corresponds to the lowest order bit. Chip Select input from an external decoder which decodes high order address bits on the ISA Address Bus. This is an active low input. # Indicates Active Low("Not") 7. FUNCTIONAL DESCRIPTION 7.1 General Description The W83781D/G provides 5 analog positive inputs, 2 analog negative input, 3 fan speed monitors or fan ON/OFF control, 3 thermistor voltage inputs, case open detection and beep function output when the monitor value exceed the set limit value. When start the monitor function on the chip, the watch dog machine monitor every function and store the value to registers. If the monitor value exceeds the limit value, the interrupt status will be set to 1. The W83781D/G provides two interface for microprocessor to read/write internal registers. The first interface use ISA Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The high byte of these ports is decoded by Chip Select (CS#), the general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: W83781D/G Index register port. Port 296h: Data port. -6- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G The register structure is showed as the diagram next page. The second interface use Serial Bus. In the W83781D/G has three serial bus address. That is, the first address defined at CR48 can read/write all registers excluding Bank 1 and Bank 2 temperature 2/3 registers, the second address defined at CR4A.bit2-0 only read/write temperature sensor 2 registers, and the third address defined at CR4A.bit6-4 only can access (read/write) temperature sensor 3 registers. Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# & IRQ Mask Registers 42h, 43, 44h, 45h VID/Fan Divisor Register 47h Serial Bus Address 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID/Device ID 49h Temperature 2, 3 Serial Bus Address 4Ah Pin Control Register 4Bh IRQ Polarity Select 4Ch Fan IN/OUT and BEEP/GPO# Control Register Port 6h Data Register 4Dh Select Bank for 50h~5Fh Reg. 4Eh Winbond Vendor ID 4Fh BANK 0 R-T Table Value BEEP Control Register Winbond Test Register 50h~58h BANK 1 Temperature 2 Control/Staus Registers 50h~56h BANK 2 Temperature 3 Control/Staus Registers 50h~56h ISA Data Bus ISA Address Bus Port 5h Index Register -7- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7.1.1 The first serial bus access timing is shown as follows: (a) Serial bus write to internal address register followed by the data byte 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 0 1 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte 7 8 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Stop by Master Frame 3 Data Byte Serial Bus Write to Internal Address Register followed by the Data Byte (b) Serial bus w rite to internal address register only 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 0 1 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Stop by Master Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte Serial Bus Write to Internal Address Register Only (c) Serial bus read from a register with the internal address register prefer to desired location 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 0 1 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 Ack by Master Stop by Master Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte Serial Bus Write to Internal Address Register Only -8- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7.1.2 The serial bus timing of the temperature 2 and 3 is shown as follows: (a) Typical 2-byte read from preset pointer location (Temp, TOS, THYST) 0 SCL SDA Start By Master 7 8 0 0 1 0 1 1 0 1 R/W Ack by 781D D7 ... ... 7 8 0 D1 D0 Ack by Master D7 ... ... 7 D1 D0 Ack by Master Stop by Master Frame 1 Serial Bus Address Byte Frame 2 MSB Data Byte Frame 3 LSB Data Byte Typical 2-Byte Read From Preset Pointer Location (b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, THYST) 0 SCL SDA Start By Master 7 8 0 4 1 0 0 1 A2 A1 A0 R/W Ack by 781D 0 0 0 0 0 0 D1 D0 Ack by 781D Frame 1 Serial Bus Address Byte Frame 2 Pointer Byte 0 SCL SDA Start By Master 7 8 0 ... ... D1 Frame 4 MSB Data Byte 7 8 0 ... ... D1 7 1 0 0 1 A2 A1 A0 R/W Ack by 781D D7 D0 Ack by Master D7 D0 No Ack by Master Stop by Master Frame 3 Serial Bus Address Byte 0 Frame 5 LSB Data Byte Typical Pointer Set Followed by Immediate Read for 2-Byte Register (c) Typical read 1-byte from configuration register with preset pointer 0 SCL SDA Start By Master 7 8 0 7 8 1 0 0 1 A2 A1 A0 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 No Ack by Master Stop by Master Frame 1 Serial Bus Address Byte Frame 2 Data Byte Typical 1-Byte Read From Configuration With Reset Pointer -9- Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G (d) Typical pointer set followed by immediate read from configuration register 0 SCL SDA Start By Master 7 8 0 4 7 8 ... 1 0 0 1 A2 A1 A0 R/W Ack by 781D 0 0 0 0 0 0 D1 D0 Ack by 781D ... Frame 1 Serial Bus Address Byte Frame 2 Pointer Byte 0 SCL (Cont..) SDA (Cont..) Repea Start By Master 7 8 0 7 8 1 0 0 1 A2 A1 A0 R/W Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 No Ack by Master Stop by Master Frame 3 Serial Bus Address Byte Frame 4 MSB Data Byte Typical Pointor Set Followed by Immediate Read from Temp 2/3 Configuration Register (e) Temperature 2/3 configuration register Write 0 SCL SDA Start By Master 7 8 0 4 7 8 1 0 0 1 A2 A1 A0 R/W 0 Ack by 781D 0 0 0 0 0 0 D1 D0 Ack by 781D Frame 1 Serial Bus Address Byte Frame 2 Pointer Byte 0 SCL (Cont...) SDA (Cont...) 0 0 0 D4 D3 D2 D1 7 8 D0 Ack by 781D Stop by Master Frame 3 Configuration Data Byte Configuration Register Write - 10 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G (f) Temperature 2/3 TOS and THYST w rite 0 SCL SDA Start By Master 7 8 0 4 7 8 1 0 0 1 A2 A1 A0 R/W Ack by 781D 0 0 0 0 0 0 D1 D0 Ack by 781D Frame 1 Serial Bus Address Byte Frame 2 Pointer Byte 0 SCL (Cont...) SDA (Cont...) D7 D6 D5 D4 D3 D2 D1 7 8 0 7 8 D0 Ack by 781D D7 D6 D5 D4 D3 D2 D1 D0 Ack by 781D Stop by Master Frame 3 MSB Data Byte Frame 4 LSB Data Byte Configuration Register Write 7.2 Analog Inputs The maximum input voltage of the analog pin is 4.096 because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage and 3.3V can directly connected to these analog inputs. The +5V and +12V inputs should be reduced a factor with external resistors so as to obtain the input range. As followed figure is shown. +2.5VINA Positive Inputs R1 Vs Positive Input R2 R F Vs Negative Input R IN -12VOUT Pin 30 -5VOUT Pin 29 -5VIN Pin 28 + +2.5VINB +3.3VIN VDD(+5V) Pin 36 Pin 35 Pin 34 Pin 33 Pin 32 Pin 31 + 8-bit ADC with 16mV LSB +12VIN -12VIN 10K, 1% VREF VTIN3 Pin 37 Pin 38 Pin 39 Pin 40 Typical Thermister Connection R THM VTIN2 VTIN1 The input voltage can be expressed as following equation. - 11 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G R2 R1 + R2 VIN = Vs × The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage is 12V. The Pin 33 is connected to +5V power supply to provide analog power, and this voltage is connected to internal resistors to monitor the +5V voltage. The negative voltage should be connected an op amps to invert and reduce the -5V and -12V voltage. The input voltage can be calculated by following equation. VS = −VIN × ( RF ) RIN The Winbond recommended value is RIN=90.9K Ohms and RF=60.4K Ohms for -5V voltage input, RIN=210K Ohms and RF=60.4K Ohms for -12V voltage input. The temperature sensors are connected by a 10K Ohms, then connect to VREF (Pin 37). The sensors should choose 10K Ohms at 25°C and β-value is 3435 for default R-T table. If the β-value is not 3435, the R-T table should be re-program to generate a correct temperature. 7.3 FAN Inputs and FAN Control Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as following. Determine the fan counter according to: Count = . 135 × 10 6 RPM × Divisor The default divisor is 2 and defined at CR47.bit7~4 and CR4B.bit7~6. The followed table is an example for the relation of divisor, PRM, and count. DIVISOR NOMINAL PRM TIME PER REVOLUTION COUNTS 70% RPM TIME FOR 70% 1 2 8800 4400 2200 1100 6.82 ms 13.64 ms 27.27 ms 54.54 ms 153 153 153 153 6160 3080 1540 770 9.74 ms 19.48 ms 38.96 ms 77.92 ms 4 8 - 12 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G +12V +5V Pull-up resister 4.7K Ohms +12V Pull-up resister 4.7K Ohms +12V FAN Out GND Fan Input Pin 18/19/20 +12V FAN Out GND 14K~39K Fan Input Pin 18/19/20 FAN Connector W83781D FAN Connector 10K W83781D Fan with Tach Pull-Up to +5V Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator +12V +12V Pull-up resister > 1K +12V FAN Out GND Fan Input Pin 18/19/20 +12V FAN Out GND Pull-up resister < 1K or totem-pole output > 1K Fan Input Pin 18/19/20 3.9V Zener FAN Connector W83781D 3.9V Zener FAN Connector W83781D Fan with Tach Pull-Up to +12V and Zener Clamp Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp 7.4 Temperature Measurement Machine The temperature data format is 8-bit two　-complement for sensor 1 and 9-bit two　-complement for sensor 2/3. The table are expressed the temperature data as following. Temperature 8-Bit Digital Output 8-Bit Binary 8-Bit Hex 0111,1101 7Dh 0001,1001 19h 0000,0001 01h 0000,0000 00h 1111,1111 FFh 1110,0111 E7h 1100,1001 C9h 9-Bit Digital Output 9-Bit Binary 9-Bit Hex 0,1111,1010 0FAh 0,0011,0010 032h 0,0000,0010 002h 0,0000,0001 001h 0,0000,0000 000h 1,1111,1111 1FFh 1,1111,1110 1FFh 1,1100,1110 1CEh 1,1001,0010 192h Publication Release Date: April 14, 2005 Revision 2.0 +125°C +25°C +1°C +0.5°C +0°C -0.5°C -1°C -25°C -55°C - 13 - W83781D/W83781G The W83781D/G temperature interrupt has two mode: (1) The first is Interrupt Mode--exceeding TOI causes an interrupt until reset by reading Interrupt Status Register 1 (CR41). Once an interrupt event has occurred over TOI, the interrupt will occur again by the temperature going below THYST. (2) Comparator Mode--setting the THYST limit to 127°C will cause the comparator mode. When temperature exceeds TOI, the interrupt will be generate Interrupt. If the temperature goes below the TOI, the interrupt will be reset. Two interrupt modes are shown as below. T HYST 127 C T OI T OI T HYST IRQ * * * IRQ *Interrupt Reset when Interrupt Status Register 1 is read (1) Interrupt Mode (2) Comparator Mode The temperature sensor 2 or 3 Over-Temperature (OVT) response is same as temperature sensor 1 IRQ signal. T OI T HYST OVT# (Comparator Mode; default) OVT# ((Interrupt Mode) * * * * *Interrupt Reset when Temperature 2/3 is read Over-Temperature Response Diagram - 14 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 8. CONTROL AND STATUS REGISTERS 8.1 Address Register (Port x5h) The main register is the INDEX Register located at Port x5h. The bit designations are as follows: 7 6 5 4 3 2 1 0 INDEX Pointe Busy Bit7: Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another ISA bus transaction. With checking this bit, multiple ISA drivers can use W83781D/G without interfering with each other or a Serial Bus driver. It is the user's responsibility not to have a Serial Bus and ISA bus operations at the same time. This bit is: Set: with a write to Port x5h or when a Serial Bus transaction is in progress. Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus transaction is finished. Bit 6-0: Read/Write INDEX of Control and Status Registers. See the tables below for detail. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Busy (Power On default 0) Index Pointer (A6-A0) Registers Bank Index Pointer (Power On default 00h) A6 A5 A4 A3 A2 A1 A0 A6-A0 in Hex Power On Value of Registers: in Binary Notes Configuration Register Interrupt Status Register 1 Interrupt Status Register 2 0 0 0 40h 41h 42h 00001000 00000000 00000000 Auto-increment to the address of Interrupt Status Register 2 after a read or write to Port x6h. - 15 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G Index Pointer (A6-A0), continued Registers Bank A6-A0 in Hex Power On Value of Registers: in Binary Notes SMI# Mask Register 1 SMI# Mask Register 2 IRQ Mask Register 1 IRQ Mask Register 2 VID/Fan Divisor Register Serial Bus Address Register 0 0 0 0 0 0 43h 44h 45h 46h 47h 48h 00000000 00000000 00000000 00000000 = 0101; = VID3VID0 = 0101101; = 0 is Reserved is 01 binary is mapped to VID = 0000,0001 binary 44h ---0,0001 0001,0101 = Reserved, = 1, = 0 = 5CA3h Auto-increment to the address of SMI# Mask Register 2 after a read or write to Port x6h. Auto-increment to the address of IRQ Mask Register 2 after a read or write to Port x6h Voltage ID 0 49h Temperature 2 and Temperature 3 Serial Bus Address Register Pin Control Register RQ/OVT# Property Select FAN IN/OUT and BEEP/GPO# Control Register Register 50h ~ 5Fh Bank Select Winbond Vendor ID Resistor-Temperature Table Register FAN Input Clock Pre-Divisor Register 2 BEEP Control Register 1 BEEP Control Register 2 0 0 0 0 0 0 0 0 0 0 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50-51h 55h 56h 57h -000,0001 0000,0000 1000-0000 - 16 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G Index Pointer (A6-A0), continued Registers Bank A6-A0 in Hex Power On Value of Registers: in Binary Notes Chip ID Temperature Sensor 2 Temperature Register Temperature Sensor 2 Configuration Register Temperature Sensor 2 Hysteresis (High Byte) Register Temperature Sensor 2 Hysteresis (Low Byte) Register Temperature Sensor 2 Overtemperature(High Byte) Register Temperature Sensor 2 Overtemperature (Low Byte) Register Temperature Sensor 3 Temperature Register Temperature Sensor 3 Configuration Register Temperature Sensor 3 Hysteresis (High Byte) Register Temperature Sensor 3 Hysteresis (Low Byte) Register Temperature Sensor 3 Overtemperature (High Byte)Register Temperature Sensor 2 Overtemperature (Low Byte) Register Value RAM Value RAM 0 1 1 1 1 1 58h 50-51h 52h 53h 54h 55h 0001-0000 = 0x00 = 0x4B = 0x0 = 0x50 1 2 2 2 2 2 56h 50-51h 52h 53h 54h 55h = 0x0 = 0x00 = 0x4B = 0x0 = 0x50 2 0 0 56h 20-3Fh 60-7Fh = 0x0 Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh. Note: Index Pointer (A6-A0) and Value RAM only can be read at the accurate bank. - 17 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 8.2 Data Register (Port x6h) Data Port: Port x6h Power on Default Value 00h Attribute: Read/write Size: 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0: Data to be read from or to be written to RAM and Register. 8.3 Configuration Register – Index 40h (Bank 0) Register Location: 40h Power on Default Value 00000001 binary Attribute: Read/write Size: 8 bits 7 6 5 4 3 2 1 0 START EN_SMI# EN_IRQ INT_CLEAR RST_OUT# IRQPOL BEEP/GPO# INITIALIZATION Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: The logical 1 restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. The logical 1 in this bit drives a zero on GPO# pin. IRQ polarity select. When set to 0, IRQ active high. Set to 1, IRQ active low. Default 0. The logical 1 outputs at least a 20 ms active low reset signal at RST_OUT# if = 1 in SMI# Mask Register 2. This bit is cleared once the pulse has gone inactive. The logical 1 disables the SMI# and IRQ outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. - 18 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G Bit 2: Bit 1: Bit 0: The logical 1 enables the IRQ Interrupt output. The logical 1 enables the SMI# Interrupt output. 1 enables startup of monitoring operations 0 puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_CLEAR'' bit. 8.4 Interrupt Status Register 1 – Index 41h (Bank 0) Register Location: 41h Power on Default Value 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 IN0 IN1 IN2 IN3 TEMP1 TEMP23 FAN1 FAN2 Bit 7: Bit 6: The logical 1 indicates the fan count limit has been exceeded. The logical 1 indicates the fan count limit has been exceeded. Bit 5: The logical 1 indicates a High or Low limit has been exceeded from temperature sensor 2 or sensor 3. The high and low limits value are defined in index registers: 53h56h of the Bank 1. Bit 4: The logical 1 indicates a High or Low limit has been exceeded from temperature sensor 1. Bit 3-0: The logical 1 indicates a High or Low limit has been exceeded. 8.5 Interrupt Status Register 2 – Index 42h (Bank 0) Register Location: 42h Power on Default Value 00h Attribute: Read Only Size: 8 bits - 19 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved Reserved Bit 7-5: Reserved.This bit should be set to 0. Bit 4: Bit 3: The logical 1 indicates Case Open has gone high. The logical 1 indicates the fan count limit has been exceeded. Bit 2-0: The logical 1 indicates a High or Low limit has been exceeded. 8.6 SMI# Mask Register 1 – Index 43h (Bank 0) Register Location: 43h Power on Default Value 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 IN0 IN1 IN2 IN3 TEMP1 TEMP23 FAN1 FAN2 Bit 7-0: The logical 1 disables the corresponding interrupt status bit for SMI# interrupt. 8.7 SMI# Mask Register 2 – Index 44h (Bank 0) Register Location: 44h Power on Default Value 00h Attribute: Read/Write Size: 8 bits - 20 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved RST_OUT# Enable Bit 7: = 1 in SMI# ask Register 2 enables the RST_OUT# in the Configuration Register. 13.8 IRQ Mask Register 1⎯Index 45h Bit 6-5: Reserved. This bit should be set to 0. Bit 4-0: The logical 1 disables the corresponding interrupt status bit for SMI# interrupt. 8.8 IRQ Mask Register 2 – Index 45h (Bank 0) Register Location: 45h Power on Default Value 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 V25INA V25INB V33IN V5IN VTHIN1 VTHIN23 FAN1 FAN2 Bit 7-0: The logical 1 disables the corresponding interrupt status bit for IRQ interrupt. 8.9 IRQ Mask Register 2 – Index 46h (Bank 0) Register Location: 46h Power on Default Value = 01000000 binary Attribute: Read/Write Size: 8 bits - 21 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved Chassis Clear Bit 7: The logical 1 outputs a minimum 20 ms active low pulse on the Case Open pin. The register bit self clears after the pulse has been output. Bit 6-5: Reserved. This bit should be set to 0. Bit 4-0: The logical 1 disables the corresponding interrupt status bit for IRQ interrupt. 8.10 VID/Fan Divisor Register – Index 47h (Bank 0) Register Location: 47h Power on Default Value is 0101, is 0000 Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 VID0 VID1 VID2 VID3 FAN1 RPM Control FAN1 RPM Control FAN2 RPM Control FAN2 RPM Control Bit 7-6: FAN2 Speed Control. = 00 - divide by 1; = 01 - divide by 2; = 10 - divide by 4; = 11 - divide by 8. Bit 5-4: FAN1 Speed Control. = 00 - divide by 1; = 01 - divide by 2; = 10 - divide by 4; = 11 - divide by 8. Bit 3-0: The VID inputs Publication Release Date: April 14, 2005 Revision 2.0 - 22 - W83781D/W83781G 8.11 Serial Bus Address Register – Index 48h (Bank 0) Register Location: 48h Power on Default Value Serial Bus address = 0101101 and = 0 binary Size: 8 bits 7 6 5 4 3 2 1 0 Serial Bus Address Reserved Bit 7: Read Only - Reserved. Bit 6-0: Read/Write - Serial Bus address . 8.12 Value RAM – Index 20h - 3Fh or 60h - Index 7Fh (auto-increment) (Bank 0) INDEX A6-A0 INDEX A6-A0 WITH AUTO-INCREMENT DESCRIPTION 20h 21h 22h 23h 24h 25h 26h 27h 28h 60h 61h 62h 63h 64h 65h 66h 67h 68h IN0 reading IN1 reading IN2 reading IN3 reading IN4 reading -IN5 reading -IN6 reading Temperature reading FAN1 reading Note: This location stores the number of counts of the internal clock per revolution. FAN2 reading 29h 69h Note: This location stores the number of counts of the internal clock per revolution. FAN3 reading 2Ah 2Bh 6Ah 6Bh Note: This location stores the number of counts of the internal clock per revolution. IN0 High Limit, default value is defined by Vcore Voltage +0.2V. Publication Release Date: April 14, 2005 Revision 2.0 - 23 - W83781D/W83781G Value RAM ⎯ Index 20h- 3Fh or 60h – Index 7Fh (auto-increment) (Bank 0), continued INDEX A6-A0 INDEX A6-A0 WITH AUTO-INCREMENT DESCRIPTION 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh IN0 Low Limit, default value is defined by Vcore Voltage 0.2V. IN1 High Limit, , default value is defined by Vcore Voltage +0.2V. IN1 Low Limit, default value is defined by Vcore Voltage 0.2V. IN2 High Limit IN2 Low Limit IN3 High Limit IN3 Low Limit IN4 High Limit IN4 Low Limit -IN5 High Limit -IN5 Low Limit -IN6 High Limit -IN6 Low Limit Over Temperature Limit (High) Temperature Hysteresis Limit (Low) FAN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN2 Fan Count Limit 3Ch 7Ch Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN3 Fan Count Limit 3Dh 3E- 3Fh 7Dh 7E- 7Fh Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. Reserved Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. Note1: For the high limits of the voltages, the device is doing a greater than comparison. For the low limits, however, it is doing a less than or equal comparison. - 24 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G Note 2: V-Core Table: Processor Pins 0 = Connected to Vss 1 = Open or pull-up to Vin Vcore Processor Pins 0 = Connected to Vss 1 = Open or pull-up to Vin Vcore VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (VDC) * * * * * * * * * * 1.80 1.85 1.90 1.95 2.00 2.05 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (VDC) No CPU 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 8.13 Voltage ID (VID7-4) – Index 49h (Bank 0) Register Location: 49h Power on Default Value is 000, 0001b is mapped to VID Size: 8 bits 7 6 5 4 3 2 1 0 VID4 DID Bit 7-1: Read Only - Device ID Bit 0: Read/Write - The VID4 inputs/outputs. Reset by MR. - 25 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 8.14 Temperature 2 and Temperature 3 Serial Bus Address Register Index 4Ah (Bank 0) Register Location: 4Ah Power on Default Value = 0000, 0001 binary. Reset by MR Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3 Bit 7: Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3. Bit 6-4: Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Bit 3: Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2. Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Data Temperature Register (Read Only) SCL Interface SDA Address Pointer (Select Register) Configuration Register THYST Register TOS Register - 26 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G (Select which register will be read from or written to): P7 P6 P5 P4 P3 P2 P1 P0 P7-P2: Must be kept 0. P1-P0: Register select: P1 0 0 1 1 P0 0 1 0 1 Index Register Selection (Bank1 & Bank2) Temperature (Read only) (Power up default) CR50h & CR51h Configuration (Read / Write) CR52h THYST (Read / Write) CR53h & CR54h TOS (Read / Write) CR55h & CR56h 8.15 Pin Control Register – Index 4Bh (Bank 0) Register Location: 4Bh Power on Default Value 44h. Reset by MR. Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3_DIV FAN3_DIV Bit 7-6:Fan3 speed divisor. = 00 - divide by 1; = 01 - divide by 2; = 10 - divide by 4; = 11 - divide by 8;Reset by MR. Bit 5-4: Select A/D Converter Clock Input. = 00 - default. = 01- divided by 4. = 10 - divided by 16. = 11 - divided by 64. Bit 3-2: Clock Input Select. = 00 - Pin 3 (CLKIN) select 14.318M Hz clock. = 01 - Default. Pin 3 (CLKIN) select 24M Hz clock. = 10 - Pin 3 (CLKIN) select 48M Hz clock . = 11 - Reserved. Pin3 no clock input. Bit 1-0: Reserved. User defined. Publication Release Date: April 14, 2005 Revision 2.0 - 27 - W83781D/W83781G 8.16 IRQ/OVT# Property Select – Index 4Ch (Bank 0) Register Location: 4Ch Power on Default Value ---0,0001. Reset by MR. Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved IRQEDGE OVTPOL DIS_OVT1 DIS_OVT2 Reserved Reserved Reserved Bit 7-5: Reserved. User Defined. Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: Disable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, enable OVT2 output through pin OVT#. Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable OVT1 output through pin OVT#. Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. When set to 1, IRQ Edge Active. Set to 0, IRQ Level trigger. Default 0, level trigger interrupt. Reserved. User Defined. 8.17 FAN IN/OUT and BEEP/GPO# Control Register – Index 4Dh (Bank 0) Register Location: 4Dh Power on Default Value 0001,0101. Reset by MR. Attribute: Read/Write Size: 8 bits - 28 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 GPOSEL DIS_ABN Bit 7: Disable power-on abnormal the monitor voltage including V-Core A,, and +3.3V. If these voltage exceed the limit value, the pin (Open Drain) of BEEP will drives low and high frequency signal. Write 1, the frequency will be disable. Default 0. After power on, the system should set this bit to 1 in order to disable BEEP. Bit 6: BEEP/GPO# Pin Function Select. Write 1 Select GPO# function. Set 0, select BEEP function. This bit default 0. Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high signal. Write 0, pin 18 always generates logic low signal. This bit default 0. Bit 4: FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0, this pin 18 acts as FAN control signal and the output value of FAN control is set by this register bit 5. This output pin can connect to power PMOS gate to control FAN ON/OFF. Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high signal. Write 0, pin 19 always generates logic low signal. This bit default 0. Bit 2: FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0, this pin 19 acts as FAN control signal and the output value of FAN control is set by this register bit 3. This output pin can connect to power NMOS gate to control FAN ON/OFF. Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high signal. Write 0, pin 20 always generates logic low signal. This bit default 0. Bit 0: FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0, this pin 20 acts as FAN control signal and the output value of FAN control is set by this register bit 1. This output pin can connect to power PMOS gate to control FAN ON/OFF. 8.18 Register 50h ~ 5Fh Bank Select – Index 4Eh (No Auto Increase) (Bank 0) Register Location: 4Eh Power on Default Value = Reserved, = 1, = 0. Reset by MR Attribute: Read/Write Size: 8 bits - 29 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select. 8.19 Winbond Vendor ID – Index 4Fh (No Auto Increase) (Bank 0) Register Location: 4Fh Power on Default Value = 5CA3h Attribute: Read Only Size: 16 bits 15 8 7 0 VIDH VIDL Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h. 8.20 Resistor-Temperature Table Register – Index 50h - 51h (Bank 0) Note: Index will be auto-increased when read Data Port 0x6, and Index will stop at 0x5F if continue reading Data Port. Any no defined register is read will return 0xFF. A6-A0 NAME READ/WRITE DESCRIPTION 50h 51h RT_IDX RT_DATA Read/Write Read/Write R-T Table index port, which is mapped to data port 51h. The default value is 0x00. R-T Table data port, which is selected by RT_IDX. - 30 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 8.21 Winbond Test Register 1 – Index 52h (Bank 0) Reserved 8.22 Winbond Test Register 2 – Index 53h (Bank 0) Reserved 8.23 Winbond Test Register 3 – Index 54h (Bank 0) Reserved 8.24 Winbond Test Register 4 – Index 55h (Bank 0) Reserved 8.25 BEEP Control Register 1 – Index 56h (Bank 0) (Auto-increment) Register Location: 56h Power on Default Value 0000,0000. Reset by MR. Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 EN_V25A_BP EN_V25B_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T23_BP EN_FAN1_BP EN_FAN2_BP Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0. Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0. Enable BEEP Output from Temperature Sensor 2 and 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0. Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0. Enable BEEP output from VDD (5V), Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Enable BEEP output from 3.3V. Write 1, enable BEEP output. Default value is 0. Enable BEEP output from V-Core B. Write 1, enable BEEP output. Default value is 0. Enable BEEP Output from V-Core A if the monitor value exceed the limits value. Write 1, enable BEEP output. Default value is 0. 8.26 BEEP Control Register 2 – Index 57h (Bank 0) ( No Auto-increment) Register Location: 57h Publication Release Date: April 14, 2005 Revision 2.0 - 31 - W83781D/W83781G Power on Default Value 1000-0000. Reset by MR. Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP Reserved Reserved EN_GBP Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6-5: Reserved. This bit should be set to 0. Bit 4: Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0. Bit 3: Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0. Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. 8.27 Chip ID – Index 58h (Bank 0) Register Location: 58h Power on Default Value 0001-0000. Reset by MR. Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 CHIPID Bit 7: Winbond Chip ID number. Read this register will return 10h. 8.28 Temperature Sensor 2 Temperature Register – Index 50h (Bank 1) Register Location: 50h Publication Release Date: April 14, 2005 Revision 2.0 - 32 - W83781D/W83781G Attribute: Size: Read Only 8 bits 7 6 5 4 3 2 1 0 TEMP2 Bit 7: Temperature of sensor 2, which is high byte. 8.29 Temperature Sensor 2 Temperature Register – Index 51h (Bank 1) Register Location: Attribute: Size: 51h Read Only 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP2 Bit 7: Temperature of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0. 8.30 Temperature Sensor 2 Configuration Register – Index 52h (Bank 1) Register Location: 52h Power on Default Value = 0x00 Size: 8 bits - 33 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Bit 1: Bit 0: Read - Reserved. This bit should be set to 0. Read/Write - Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Read/Write - When set to 1 the sensor will stop monitor. 8.31 Temperature Sensor 2 Hysteresis (High Byte) Register – Index 53h (Bank 1) Register Location: 53h Power on Default Value = 0x4B Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 THYST2 Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 8.32 Temperature Sensor 2 Hysteresis (Low Byte) Register – Index54h (Bank 1) Register Location: 54h Power on Default Value = 0x0 Attribute: Read Only Size: 8 bits - 34 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 Reserved THYST2 Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0. 8.33 Temperature Sensor 2 Over-temperature(High Byte) Register – Index 55h (Bank 1) Register Location: 55h Power on Default Value = 0x50 Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 TOVF2 Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 8.34 Temperature Sensor 2 Over-temperature (Low Byte) Register – Index 56h (Bank 1) Register Location: 56h Power on Default Value Size: 8 bits = 0x0 - 35 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 7 6 5 4 3 2 1 0 Reserved TOVF2 Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0. 8.35 Temperature Sensor 3 Temperature Register - Index 50h (Bank 2) Register Location: Attribute: Size: 50h Read Only 8 bits 7 6 5 4 3 2 1 0 TEMP2 Bit 7-0: Temperature of sensor 2, which is high byte. - 36 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 8.36 Temperature Sensor 3 Temperature Register – Index 51h (Bank 2) Register Location: Attribute: Size: 51h Read Only 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP2 Bit 7: Temperature of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0. 8.37 Temperature Sensor 3 Configuration Register – Index 52h (Bank 2) Register Location: 52h Power on Default Value = 0x00 Size: 8 bits 7 6 5 4 3 2 1 0 STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVF# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. - 37 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 8.38 Temperature Sensor 3 Hysteresis (High Byte) Register – Index 53h (Bank 2) Register Location: 53h Power on Default Value = 0x4B Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 THYST3 Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 8.39 Temperature Sensor 3 Hysteresis (Low Byte) Register – Index 54h (Bank 2) Register Location: 54h Power on Default Value = 0x0 Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 Reserved THYST3 Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0. 8.40 Temperature Sensor 3 over temperature (High Byte)Register – Index 55h (Bank 2) Register Location: 55h Power on Default Value = 0x50 Attribute: Read/Write Size: 8 bits Publication Release Date: April 14, 2005 Revision 2.0 - 38 - W83781D/W83781G 7 6 5 4 3 2 1 0 TOVF3 Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 8.41 Temperature Sensor 3 Over-temperature (Low Byte) Register – Index 56h (Bank 2) Register Location: Power on Default Value Size: 8 bits 7 6 5 4 3 2 1 0 56h = 0x0 Reserved TOVF3 Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0. - 39 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 9. ELECRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage Input Voltage Operating Temperature Storage Temperature -0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150 V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 DC Characteristics (Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 2.0 0.8 0.4 +10 -10 V V V V μA μA IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Output Low Voltage Output High Voltage VtVt+ VTH VOL VOH ILIH ILIL VOL VOH 0.5 1.6 0.5 2.4 0.8 2.0 1.2 1.1 2.4 V V V VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V IOL = 12 mA IOH = -12 mA 0.4 +10 -10 0.4 2.4 V V μA μA V V OUT12t - TTL level output pin with source-sink capability of 12 mA - 40 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G DC Characteristics, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage Output Low Voltage Output Low Voltage INt - TTL level input pin VOL VOL VOL VIL VIH ILIH ILIL VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 2.0 0.4 0.4 0.4 0.8 +10 -10 1.1 2.4 +10 -10 V V V V V μA μA V V V μA μA IOL = 8 mA IOL = 12 mA IOL = 48 mA OD12 - Open-drain output pin with sink capability of 12 mA OD48 - Open-drain output pin with sink capability of 48 mA Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIN = VDD VIN = 0 V VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage - 41 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 9.3 AC Characteristics 9.3.1 ISA Read/Write Interface Timing AEN SA[2:0],CS# tAR t RD t RCU IOR# IOW# t RA RC SD[7:0] t RVD VALID DATA t RDH IRQ t RI ISA Bus Read Timing AEN SA[2:0],CS# tAW VALID t WR t WCU VALID IOW# IOR# t WA WC SD[7:0] VALID DATA t DS t DH IRQ t WI ISA Bus Write Timing - 42 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G ISA Read/Write Timing PARAMETER Valid Address to Read Active Valid Address to Write Active Data Hold Data Setup Address Hold from Inactive Read Read Cycle Update Read Strobe Width Read Data Hold Read Strobe to Clear IRQ Active Read to Valid Data Address Hold from Inactive Write Write Cycle Update Write Strobe to Clear IRQ Write Strobe Width Read Cycle = tAR + tRD+tRCV Write Cycle = tAW+tWR+tWCV SYMBOL t AR tAW tDH tDS tRA tRCU tRD tRDH tRI tRVD tWA tWCU tWI tWR RC WC - MIN. 10 10 5 80 40 200 120 40 MAX. UNIT nS nS nS nS nS nS nS nS 60 115 5 80 60 120 330 210 nS nS nS nS nS nS nS nS - 43 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 9.3.2 Serial Bus Timing Diagram t SCL SCL t HD;SDA t HD;DAT t SU;STO SDA IN VALID DATA t SU;DAT SDA OUT Serial Bus Timing Diagram Serial Bus Timing PARAMETER SYMBOL MIN. MAX. UNIT SCL Clock Period Start Condition Hold Time Stop Condition Setup-up Time DATA to SCL Setup Time DATA to SCL Hold Time SCL and SDA Rise Time SCL and SDA Fall Time t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF - 10 4.7 4.7 120 5 1.0 300 uS uS uS nS nS uS nS - 44 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 10. HOW TO READ THE TOP MARKING The top marking of W83781D W83781D 745AA Left: Winbond logo 1st line: Type number W83781D, D means LQFP (Thickness = 1.4 mm). 745 A A 2nd line: Tracking code 745: packages made in '97, week 45 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B The top marking of W83781G W83781G 745AA Left: Winbond logo 1st line: Type number W83781G, G means lead-free package. 745 A A 2nd line: Tracking code 745: packages made in '97, week 45 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B - 45 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 11. PACKAGE DIMENTIONS (48-pin QFP) HD D 36 25 Symbol Dimension in inch Min. Nom. Max. Dimension in mm Min. --0.05 1.35 0.17 0.09 Nom. ----1.40 0.20 --7.00 7.00 0.50 9.00 9.00 Max. 1.60 0.15 1.45 0.27 0.20 37 24 E HE 48 13 1 e b 12 A A1 A2 b c D E e HD HE L L1 y 0 Notes: c 0.45 0.60 1.00 0.75 --0 0.08 3.5 --7 A2 A1 y A Seating Plane See Detail F L L1 Detail F 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. - 46 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G 12. APPLICATION CIRCUITS OF W83781D NOTE: 1. Selected CLKIN of 2. Pin OVT# connects with PIIX4 48M , 24M OR 14.318M Pin THRM#(H19) PIIX4_3V VCC PIIX4_3V RT3 10K 1% 10K 1% (CPU) RT1 RT2 (MB) 10K 1% 3. If there originally exists Pull-up Resistor on these lines, these resistors are not needed. 4. SMI# is connected to PIIX4 EXTSMI# . 5. To eliminate noise and to be VCC line, this line is as wider as better. (about 15-20 mil) Note2. OVT# IRQ SMI# Note4. VREFOUT VTIN3 VTIN2 VTIN1 VID0 OVT# IRQ SMI# C7 .1uF R14 28K 1% VCOREB VCOREA A2 A1 A0 R6 U1 R16 10K 1% R17 10K 1% R7 60.4K 1% R8 60.4K 1% 10K 1% R13 10 R4 210K 1% C8 .1uF R5 90.9K 1% C6 .1uF Note3. R30 4.7K t .1uF .1uF .1uF t t R15 R R18 R C2 C1 C3 R1 10K 1% R2 10K 1% R3 10K 1% +12V Note5. (+5V) VCC +3.3V -12V -5V R9 10K 1% A[2..0] CS# A[2..0] 37 38 39 40 41 42 43 44 45 46 47 48 VREF VTIN3 VTIN2 VTIN1 VID0 OVT# IRQ SMI# A2 A1 A0 CS# Note1. IOR# IOW# CLKIN D[7..0] D[7..0] IOR# IOW# CLKIN D7 D6 D5 D4 D3 D2 D1 D0 VID1 1 2 3 4 5 6 7 8 9 10 11 12 IOR# IOW# CLKIN D7 D6 D5 D4 D3 D2 D1 D0 VID1 W83781D VCOREA VCOREB +3.3VIN +5VIN +12VIN -12VIN -12VOUT -5VOUT -5VIN GNDA BEEP/GPO# VID3 36 35 34 33 32 31 30 29 28 27 26 25 +2.5VINA +2.5VINB +3.3VIN +5VIN +12VIN -12VIN -12VOUT -5VOUT -5VIN GNDA VID3 C13 .1uF C12 .1uF C14 .1uF C10 .1uF C9 .1uF C5 .1uF C16 10uF C15 .1uF VID2 RSTOUT# SDA SCL FAN1 IN/OUT FAN2 IN/OUT FAN3 IN/OUT VID4 CASEOPEN MR GNDD VCC 24 23 22 21 20 19 18 17 16 15 14 13 VID2 RSTOUT# SDA SCL FAN2IN FAN1IN FAN1OUT VID4 CASEOPEN MR GNDD VCC L1 BEEP/GPO# INDUCTOR Ver 0.5 0.6 Contents Ver0.5 schematic AP1,AP2,AP3 Add R30 Erase R10 in Ver0.5 VCC PIIX4_3V Application Notice 2 (Reserve R & C) C4 .1uF C11 10uF RSTOUT# R25 R 100 C18 CAPACITOR NON-POL 33p R11 R12 R R 4.7K 4.7K Note3. FAN2IN FAN1IN FAN1OUT CASEOPEN ResetDrv SDA SCL WINBOND ELECTRONICS CORP. Title Size B Date: APPLICATION OF W83781D Document Number Wednesday, February 24, 1999 Sheet 1 of 2 Rev 0.6 - 47 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G +12V R19 4.7K R26 3 2 1 CPU FAN 3 HEADER Connecter FAN2IN R 20-27K R27 R 10K R24 100 LS1 VCC D3 DIODE JP1 SPEAKER BEEP/GPO# +12V D4 DIODE JP2 3 2 1 MB FAN HEADER 3 Connecter R22 4.7K R28 FAN1IN R 20-27K R29 R 10K SpeakerBlock Q1 NPN R23 FAN1OUT 4.7K FanBlock D2 5VSB DIODE C18 10uF VRTC D1 BAT DIODE On-board RTC Power Switch Circuit U2A C17 10% 50V 1000pF 1 2 74HC14 These two inveters consume VRTC R20 10K Q CASEOPEN S1 CASEOPEN SW R21 4 U2B 3 74HC14 Q' CaseOpen Switch open close open open 2.2M Q' 1 0 0 1 Q 0 1 1 0 normal state if W83781D does not reset (let Q=0), then stable after reset ps. 'Switch Open' means 'Case Close' CaseBlock WINBOND ELECTRONICS CORP. Title Size B Date: APPLICATION OF W83781D Document Number Wednesday, February 24, 1999 Sheet 2 of 2 Rev 0.6 - 48 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G REVISION HISTORY VERSION DATE PAGE DESCRIPTION n.a. 0.60 0.61 11/07/97 11/19/97 n.a. 5 4 0.62 12/17/97 5 6 33 37 0.63 1/13/98 40 43 48 0.64 1.0 1.1 1.2 2.0 05/19/98 04/11/02 10/25/02 01/06/05 April 14, 2005 13 n.a. 48 n.a. 48 All the version before 0.60 are internal use. First published. Pin 18-20: I/O Type → I/O12ts Pin18-20:I/O Type → Fan 1, Pin18:Fan1→ Fan3 Pin23: I/O Type → OUT8t Pin42: I/O Type → OUT12 8.24 index 55h(Bank 0) → Winbond Test Register 8.30 index 52h(Bank 1) bit2 → Reserve 8.37 index 52h(Bank 2) bit2 → Reserve 9.2 I/O 12ts TTL DC Characteristics Package QFT → LQFP Divisor table 1, 2, 3, 4 → 1, 2, 4, 8 Change all version include version on web site to 1.0 Verify ISA Bus RD Timing. (210 =>330ns) Lead-free package version ADD Important Notice - 49 - Publication Release Date: April 14, 2005 Revision 2.0 W83781D/W83781G Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 50 - Publication Release Date: April 14, 2005 Revision 2.0